init:初始框架
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SkyLi
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/*****************************************************************************
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Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the
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distribution.
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Neither the name of Texas Instruments Incorporated nor the names of
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its contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#ifndef ti_devices_msp_peripherals_hw_wwdt__include
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#define ti_devices_msp_peripherals_hw_wwdt__include
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/* Filename: hw_wwdt.h */
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/* Revised: 2023-05-10 21:36:51 */
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/* Revision: 662977591cca7f583e1df6fe4b402c6c07949212 */
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#ifndef __CORTEX_M
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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#endif
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/* Use standard integer types with explicit width */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/******************************************************************************
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* WWDT Registers
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******************************************************************************/
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#define WWDT_CPU_INT_OFS ((uint32_t)0x00001020U)
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#define WWDT_GPRCM_OFS ((uint32_t)0x00000800U)
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/** @addtogroup WWDT_CPU_INT
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@{
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*/
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typedef struct {
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__I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */
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uint32_t RESERVED0;
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__IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */
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uint32_t RESERVED1;
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__I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */
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uint32_t RESERVED2;
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__I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */
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uint32_t RESERVED3;
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__O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */
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uint32_t RESERVED4;
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__O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */
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} WWDT_CPU_INT_Regs;
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/*@}*/ /* end of group WWDT_CPU_INT */
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/** @addtogroup WWDT_GPRCM
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@{
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*/
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typedef struct {
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__IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */
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__O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */
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uint32_t RESERVED0[3];
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__I uint32_t STAT; /* !< (@ 0x00000814) Status Register */
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} WWDT_GPRCM_Regs;
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/*@}*/ /* end of group WWDT_GPRCM */
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/** @addtogroup WWDT
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@{
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*/
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typedef struct {
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uint32_t RESERVED0[512];
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WWDT_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */
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uint32_t RESERVED1[512];
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__IO uint32_t PDBGCTL; /* !< (@ 0x00001018) Peripheral Debug Control */
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uint32_t RESERVED2;
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WWDT_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */
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uint32_t RESERVED3[37];
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__IO uint32_t EVT_MODE; /* !< (@ 0x000010E0) Event Mode */
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uint32_t RESERVED4[6];
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__I uint32_t DESC; /* !< (@ 0x000010FC) Module Description */
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__IO uint32_t WWDTCTL0; /* !< (@ 0x00001100) Window Watchdog Timer Control Register 0 */
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__IO uint32_t WWDTCTL1; /* !< (@ 0x00001104) Window Watchdog Timer Control Register 0 */
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__IO uint32_t WWDTCNTRST; /* !< (@ 0x00001108) Window Watchdog Timer Counter Reset Register */
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__I uint32_t WWDTSTAT; /* !< (@ 0x0000110C) Window Watchdog Timer Status Register */
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} WWDT_Regs;
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/*@}*/ /* end of group WWDT */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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/******************************************************************************
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* WWDT Register Control Bits
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******************************************************************************/
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/* WWDT_IIDX Bits */
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/* WWDT_IIDX[STAT] Bits */
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#define WWDT_IIDX_STAT_OFS (0) /* !< STAT Offset */
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#define WWDT_IIDX_STAT_MASK ((uint32_t)0x0000001FU) /* !< Module Interrupt Vector Value.
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This register provides the highest
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priority interrupt index. A read
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clears the corresponding interrupt
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flag in RIS and MISC. */
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#define WWDT_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */
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#define WWDT_IIDX_STAT_INTTIM ((uint32_t)0x00000001U) /* !< Interval Timer Interrupt; Interrupt
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Flag: INTTIM; Interrupt Priority:
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Highest */
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/* WWDT_IMASK Bits */
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/* WWDT_IMASK[INTTIM] Bits */
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#define WWDT_IMASK_INTTIM_OFS (0) /* !< INTTIM Offset */
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#define WWDT_IMASK_INTTIM_MASK ((uint32_t)0x00000001U) /* !< Interval Timer Interrupt. */
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#define WWDT_IMASK_INTTIM_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */
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#define WWDT_IMASK_INTTIM_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */
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/* WWDT_RIS Bits */
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/* WWDT_RIS[INTTIM] Bits */
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#define WWDT_RIS_INTTIM_OFS (0) /* !< INTTIM Offset */
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#define WWDT_RIS_INTTIM_MASK ((uint32_t)0x00000001U) /* !< Interval Timer Interrupt. */
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#define WWDT_RIS_INTTIM_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */
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#define WWDT_RIS_INTTIM_SET ((uint32_t)0x00000001U) /* !< Interrupt occurred */
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/* WWDT_MIS Bits */
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/* WWDT_MIS[INTTIM] Bits */
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#define WWDT_MIS_INTTIM_OFS (0) /* !< INTTIM Offset */
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#define WWDT_MIS_INTTIM_MASK ((uint32_t)0x00000001U) /* !< Interval Timer Interrupt. */
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#define WWDT_MIS_INTTIM_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */
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#define WWDT_MIS_INTTIM_SET ((uint32_t)0x00000001U) /* !< Interrupt occurred */
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/* WWDT_ISET Bits */
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/* WWDT_ISET[INTTIM] Bits */
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#define WWDT_ISET_INTTIM_OFS (0) /* !< INTTIM Offset */
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#define WWDT_ISET_INTTIM_MASK ((uint32_t)0x00000001U) /* !< Interval Timer Interrupt. */
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#define WWDT_ISET_INTTIM_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
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#define WWDT_ISET_INTTIM_SET ((uint32_t)0x00000001U) /* !< Set Interrupt */
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/* WWDT_ICLR Bits */
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/* WWDT_ICLR[INTTIM] Bits */
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#define WWDT_ICLR_INTTIM_OFS (0) /* !< INTTIM Offset */
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#define WWDT_ICLR_INTTIM_MASK ((uint32_t)0x00000001U) /* !< Interval Timer Interrupt. */
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#define WWDT_ICLR_INTTIM_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
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#define WWDT_ICLR_INTTIM_CLR ((uint32_t)0x00000001U) /* !< Clear Interrupt */
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/* WWDT_PWREN Bits */
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/* WWDT_PWREN[ENABLE] Bits */
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#define WWDT_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */
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#define WWDT_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power Note: For safety
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devices the power cannot be disabled
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once enabled. */
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#define WWDT_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */
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#define WWDT_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */
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/* WWDT_PWREN[KEY] Bits */
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#define WWDT_PWREN_KEY_OFS (24) /* !< KEY Offset */
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#define WWDT_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */
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#define WWDT_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this
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register */
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/* WWDT_RSTCTL Bits */
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/* WWDT_RSTCTL[RESETSTKYCLR] Bits */
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#define WWDT_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */
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#define WWDT_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear [GPRCM.STAT.RESETSTKY] */
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#define WWDT_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
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#define WWDT_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */
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/* WWDT_RSTCTL[RESETASSERT] Bits */
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#define WWDT_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */
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#define WWDT_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral
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Note: For safety devices a watchdog
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reset by software is not possible. */
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#define WWDT_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
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#define WWDT_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */
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/* WWDT_RSTCTL[KEY] Bits */
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#define WWDT_RSTCTL_KEY_OFS (24) /* !< KEY Offset */
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#define WWDT_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */
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#define WWDT_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this
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register */
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/* WWDT_STAT Bits */
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/* WWDT_STAT[RESETSTKY] Bits */
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#define WWDT_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */
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#define WWDT_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the
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peripheral was reset, since this bit
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was cleared by RESETSTKYCLR in the
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RSTCTL register */
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#define WWDT_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset
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since this bit was last cleared by
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RESETSTKYCLR in the RSTCTL register */
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#define WWDT_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the
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last bit clear */
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/* WWDT_PDBGCTL Bits */
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/* WWDT_PDBGCTL[FREE] Bits */
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#define WWDT_PDBGCTL_FREE_OFS (0) /* !< FREE Offset */
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#define WWDT_PDBGCTL_FREE_MASK ((uint32_t)0x00000001U) /* !< Free run control */
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#define WWDT_PDBGCTL_FREE_STOP ((uint32_t)0x00000000U) /* !< The peripheral freezes
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functionality while the Core Halted
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input is asserted and resumes when it
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is deasserted. */
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#define WWDT_PDBGCTL_FREE_RUN ((uint32_t)0x00000001U) /* !< The peripheral ignores the state of
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the Core Halted input */
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/* WWDT_EVT_MODE Bits */
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/* WWDT_EVT_MODE[INT0_CFG] Bits */
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#define WWDT_EVT_MODE_INT0_CFG_OFS (0) /* !< INT0_CFG Offset */
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#define WWDT_EVT_MODE_INT0_CFG_MASK ((uint32_t)0x00000003U) /* !< Event line mode select for event
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corresponding to
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[IPSTANDARD.CPU_INT][0] */
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#define WWDT_EVT_MODE_INT0_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
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disabled. */
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#define WWDT_EVT_MODE_INT0_CFG_SOFTWARE ((uint32_t)0x00000001U) /* !< The interrupt or event line is in
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software mode. Software must clear
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the RIS. */
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#define WWDT_EVT_MODE_INT0_CFG_HARDWARE ((uint32_t)0x00000002U) /* !< The interrupt or event line is in
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hardware mode. The hardware (another
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module) clears automatically the
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associated RIS flag. */
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/* WWDT_DESC Bits */
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/* WWDT_DESC[MINREV] Bits */
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#define WWDT_DESC_MINREV_OFS (0) /* !< MINREV Offset */
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#define WWDT_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */
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#define WWDT_DESC_MINREV_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
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#define WWDT_DESC_MINREV_MAXIMUM ((uint32_t)0x0000000FU) /* !< Highest possible value */
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/* WWDT_DESC[MAJREV] Bits */
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#define WWDT_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */
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#define WWDT_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */
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#define WWDT_DESC_MAJREV_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
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#define WWDT_DESC_MAJREV_MAXIMUM ((uint32_t)0x000000F0U) /* !< Highest possible value */
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/* WWDT_DESC[INSTNUM] Bits */
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#define WWDT_DESC_INSTNUM_OFS (8) /* !< INSTNUM Offset */
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#define WWDT_DESC_INSTNUM_MASK ((uint32_t)0x00000F00U) /* !< Instance Number within the device.
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This will be a parameter to the RTL
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for modules that can have multiple
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instances */
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#define WWDT_DESC_INSTNUM_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
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#define WWDT_DESC_INSTNUM_MAXIMUM ((uint32_t)0x00000F00U) /* !< Highest possible value */
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/* WWDT_DESC[FEATUREVER] Bits */
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#define WWDT_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */
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#define WWDT_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module
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*instance* */
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#define WWDT_DESC_FEATUREVER_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
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#define WWDT_DESC_FEATUREVER_MAXIMUM ((uint32_t)0x0000F000U) /* !< Highest possible value */
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/* WWDT_DESC[MODULEID] Bits */
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#define WWDT_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */
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#define WWDT_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module identification contains a
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unique peripheral identification
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number. The assignments are
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maintained in a central database for
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all of the platform modules to ensure
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uniqueness. */
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#define WWDT_DESC_MODULEID_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
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#define WWDT_DESC_MODULEID_MAXIMUM ((uint32_t)0xFFFF0000U) /* !< Highest possible value */
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/* WWDT_WWDTCTL0 Bits */
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/* WWDT_WWDTCTL0[PER] Bits */
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#define WWDT_WWDTCTL0_PER_OFS (4) /* !< PER Offset */
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#define WWDT_WWDTCTL0_PER_MASK ((uint32_t)0x00000070U) /* !< Timer Period of the WWDT. These
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bits select the total watchdog timer
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count. */
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#define WWDT_WWDTCTL0_PER_EN_25 ((uint32_t)0x00000000U) /* !< Total timer count is 2^25 */
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#define WWDT_WWDTCTL0_PER_EN_21 ((uint32_t)0x00000010U) /* !< Total timer count is 2^21 */
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#define WWDT_WWDTCTL0_PER_EN_18 ((uint32_t)0x00000020U) /* !< Total timer count is 2^18 */
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#define WWDT_WWDTCTL0_PER_EN_15 ((uint32_t)0x00000030U) /* !< Total timer count is 2^15 */
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#define WWDT_WWDTCTL0_PER_EN_12 ((uint32_t)0x00000040U) /* !< Total timer count is 2^12 (default) */
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#define WWDT_WWDTCTL0_PER_EN_10 ((uint32_t)0x00000050U) /* !< Total timer count is 2^10 */
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#define WWDT_WWDTCTL0_PER_EN_8 ((uint32_t)0x00000060U) /* !< Total timer count is 2^8 */
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#define WWDT_WWDTCTL0_PER_EN_6 ((uint32_t)0x00000070U) /* !< Total timer count is 2^6 */
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/* WWDT_WWDTCTL0[WINDOW0] Bits */
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#define WWDT_WWDTCTL0_WINDOW0_OFS (8) /* !< WINDOW0 Offset */
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#define WWDT_WWDTCTL0_WINDOW0_MASK ((uint32_t)0x00000700U) /* !< Closed window period in percentage
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of the timer interval.
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WWDTCTL1.WINSEL determines the active
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window setting (WWDTCTL0.WINDOW0 or
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WWDTCTL0.WINDOW1). */
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#define WWDT_WWDTCTL0_WINDOW0_SIZE_0 ((uint32_t)0x00000000U) /* !< 0% (No closed Window) */
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#define WWDT_WWDTCTL0_WINDOW0_SIZE_12 ((uint32_t)0x00000100U) /* !< 12.50% of the total timer period is
|
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closed window */
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#define WWDT_WWDTCTL0_WINDOW0_SIZE_18 ((uint32_t)0x00000200U) /* !< 18.75% of the total timer period is
|
||||
closed window */
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||||
#define WWDT_WWDTCTL0_WINDOW0_SIZE_25 ((uint32_t)0x00000300U) /* !< 25% of the total timer period is
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||||
closed window */
|
||||
#define WWDT_WWDTCTL0_WINDOW0_SIZE_50 ((uint32_t)0x00000400U) /* !< 50% of the total timer period is
|
||||
closed window */
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||||
#define WWDT_WWDTCTL0_WINDOW0_SIZE_75 ((uint32_t)0x00000500U) /* !< 75% of the total timer period is
|
||||
closed window */
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||||
#define WWDT_WWDTCTL0_WINDOW0_SIZE_81 ((uint32_t)0x00000600U) /* !< 81.25% of the total timer period is
|
||||
closed window */
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||||
#define WWDT_WWDTCTL0_WINDOW0_SIZE_87 ((uint32_t)0x00000700U) /* !< 87.50% of the total timer period is
|
||||
closed window */
|
||||
/* WWDT_WWDTCTL0[MODE] Bits */
|
||||
#define WWDT_WWDTCTL0_MODE_OFS (16) /* !< MODE Offset */
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||||
#define WWDT_WWDTCTL0_MODE_MASK ((uint32_t)0x00010000U) /* !< Window Watchdog Timer Mode */
|
||||
#define WWDT_WWDTCTL0_MODE_WINDOW ((uint32_t)0x00000000U) /* !< Window Watchdog Timer Mode. The
|
||||
WWDT will generate a error signal to
|
||||
the ESM when following conditions
|
||||
occur: - Timer Expiration (Timeout) -
|
||||
Reset WWDT during the active window
|
||||
closed period - Keyword violation */
|
||||
#define WWDT_WWDTCTL0_MODE_INTERVAL ((uint32_t)0x00010000U) /* !< Interval Timer Mode. The WWDT acts
|
||||
as an interval timer. It generates an
|
||||
interrupt on timeout. */
|
||||
/* WWDT_WWDTCTL0[STISM] Bits */
|
||||
#define WWDT_WWDTCTL0_STISM_OFS (17) /* !< STISM Offset */
|
||||
#define WWDT_WWDTCTL0_STISM_MASK ((uint32_t)0x00020000U) /* !< Stop In Sleep Mode. The
|
||||
functionality of this bit requires
|
||||
that POLICY.HWCEN = 0. If
|
||||
POLICY.HWCEN = 1 the WWDT resets
|
||||
during sleep and needs
|
||||
re-configuration. Note: This bit has
|
||||
no effect for the global Window
|
||||
Watchdog as Sleep Mode is not
|
||||
supported. */
|
||||
#define WWDT_WWDTCTL0_STISM_CONT ((uint32_t)0x00000000U) /* !< The WWDT continues to function in
|
||||
Sleep mode. */
|
||||
#define WWDT_WWDTCTL0_STISM_STOP ((uint32_t)0x00020000U) /* !< The WWDT stops in Sleep mode and
|
||||
resumes where it was stopped after
|
||||
wakeup. */
|
||||
/* WWDT_WWDTCTL0[KEY] Bits */
|
||||
#define WWDT_WWDTCTL0_KEY_OFS (24) /* !< KEY Offset */
|
||||
#define WWDT_WWDTCTL0_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow write access to this
|
||||
register. Writing to this register
|
||||
with an incorrect key activates the
|
||||
WWDT error signal to the ESM. Read as
|
||||
0. */
|
||||
#define WWDT_WWDTCTL0_KEY_UNLOCK_W ((uint32_t)0xC9000000U) /* !< KEY to allow write access to this
|
||||
register */
|
||||
/* WWDT_WWDTCTL0[CLKDIV] Bits */
|
||||
#define WWDT_WWDTCTL0_CLKDIV_OFS (0) /* !< CLKDIV Offset */
|
||||
#define WWDT_WWDTCTL0_CLKDIV_MASK ((uint32_t)0x00000007U) /* !< Module Clock Divider, Divide the
|
||||
clock source by CLKDIV+1. Divider
|
||||
values from /1 to /8 are possible.
|
||||
The clock divider is currently 4
|
||||
bits. Bit 4 has no effect and should
|
||||
always be written with 0. */
|
||||
#define WWDT_WWDTCTL0_CLKDIV_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum value */
|
||||
#define WWDT_WWDTCTL0_CLKDIV_MAXIMUM ((uint32_t)0x00000007U) /* !< Maximum value */
|
||||
/* WWDT_WWDTCTL0[WINDOW1] Bits */
|
||||
#define WWDT_WWDTCTL0_WINDOW1_OFS (12) /* !< WINDOW1 Offset */
|
||||
#define WWDT_WWDTCTL0_WINDOW1_MASK ((uint32_t)0x00007000U) /* !< Closed window period in percentage
|
||||
of the timer interval.
|
||||
WWDTCTL1.WINSEL determines the active
|
||||
window setting (WWDTCTL0.WINDOW0 or
|
||||
WWDTCTL0.WINDOW1). */
|
||||
#define WWDT_WWDTCTL0_WINDOW1_SIZE_0 ((uint32_t)0x00000000U) /* !< 0% (No closed Window) */
|
||||
#define WWDT_WWDTCTL0_WINDOW1_SIZE_12 ((uint32_t)0x00001000U) /* !< 12.50% of the total timer period is
|
||||
closed window */
|
||||
#define WWDT_WWDTCTL0_WINDOW1_SIZE_18 ((uint32_t)0x00002000U) /* !< 18.75% of the total timer period is
|
||||
closed window */
|
||||
#define WWDT_WWDTCTL0_WINDOW1_SIZE_25 ((uint32_t)0x00003000U) /* !< 25% of the total timer period is
|
||||
closed window */
|
||||
#define WWDT_WWDTCTL0_WINDOW1_SIZE_50 ((uint32_t)0x00004000U) /* !< 50% of the total timer period is
|
||||
closed window */
|
||||
#define WWDT_WWDTCTL0_WINDOW1_SIZE_75 ((uint32_t)0x00005000U) /* !< 75% of the total timer period is
|
||||
closed window */
|
||||
#define WWDT_WWDTCTL0_WINDOW1_SIZE_81 ((uint32_t)0x00006000U) /* !< 81.25% of the total timer period is
|
||||
closed window */
|
||||
#define WWDT_WWDTCTL0_WINDOW1_SIZE_87 ((uint32_t)0x00007000U) /* !< 87.50% of the total timer period is
|
||||
closed window */
|
||||
|
||||
/* WWDT_WWDTCTL1 Bits */
|
||||
/* WWDT_WWDTCTL1[KEY] Bits */
|
||||
#define WWDT_WWDTCTL1_KEY_OFS (24) /* !< KEY Offset */
|
||||
#define WWDT_WWDTCTL1_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow write access to this
|
||||
register. Writing to this register
|
||||
with an incorrect key activates the
|
||||
WWDT error signal to the ESM. Read as
|
||||
0. */
|
||||
#define WWDT_WWDTCTL1_KEY_UNLOCK_W ((uint32_t)0xBE000000U) /* !< KEY to allow write access to this
|
||||
register */
|
||||
/* WWDT_WWDTCTL1[WINSEL] Bits */
|
||||
#define WWDT_WWDTCTL1_WINSEL_OFS (0) /* !< WINSEL Offset */
|
||||
#define WWDT_WWDTCTL1_WINSEL_MASK ((uint32_t)0x00000001U) /* !< Close Window Select */
|
||||
#define WWDT_WWDTCTL1_WINSEL_WIN0 ((uint32_t)0x00000000U) /* !< In window mode field WINDOW0 of
|
||||
WDDTCTL0 defines the closed window
|
||||
size. */
|
||||
#define WWDT_WWDTCTL1_WINSEL_WIN1 ((uint32_t)0x00000001U) /* !< In window mode field WINDOW1 of
|
||||
WDDTCTL0 defines the closed window
|
||||
size. */
|
||||
|
||||
/* WWDT_WWDTCNTRST Bits */
|
||||
/* WWDT_WWDTCNTRST[RESTART] Bits */
|
||||
#define WWDT_WWDTCNTRST_RESTART_OFS (0) /* !< RESTART Offset */
|
||||
#define WWDT_WWDTCNTRST_RESTART_MASK ((uint32_t)0xFFFFFFFFU) /* !< Window Watchdog Timer Counter
|
||||
Restart Writing 00A7h to this
|
||||
register restarts the WWDT Counter.
|
||||
Writing any other value causes an
|
||||
error generation to the ESM. Read as
|
||||
0. */
|
||||
#define WWDT_WWDTCNTRST_RESTART_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum value */
|
||||
#define WWDT_WWDTCNTRST_RESTART_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Maximum value */
|
||||
|
||||
/* WWDT_WWDTSTAT Bits */
|
||||
/* WWDT_WWDTSTAT[RUN] Bits */
|
||||
#define WWDT_WWDTSTAT_RUN_OFS (0) /* !< RUN Offset */
|
||||
#define WWDT_WWDTSTAT_RUN_MASK ((uint32_t)0x00000001U) /* !< Watchdog running status flag. */
|
||||
#define WWDT_WWDTSTAT_RUN_OFF ((uint32_t)0x00000000U) /* !< Watchdog counter stopped. */
|
||||
#define WWDT_WWDTSTAT_RUN_ON ((uint32_t)0x00000001U) /* !< Watchdog running. */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ti_devices_msp_peripherals_hw_wwdt__include */
|
||||
Reference in New Issue
Block a user