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libraries/sdk/ti/devices/msp/peripherals/m0p/hw_cpuss.h
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/*****************************************************************************
Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_m0p_hw_cpuss__include
#define ti_devices_msp_peripherals_m0p_hw_cpuss__include
/* Filename: hw_cpuss.h */
/* Revised: 2023-04-30 21:36:20 */
/* Revision: ec4f3de051dafa6135b4867f4e796eec5f1a339b */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* CPUSS Registers
******************************************************************************/
#define CPUSS_INT_GROUP_OFS ((uint32_t)0x00001100U)
/** @addtogroup CPUSS_INT_GROUP
@{
*/
typedef struct {
__I uint32_t IIDX; /* !< (@ 0x00001100) Interrupt index */
uint32_t RESERVED0;
__I uint32_t IMASK; /* !< (@ 0x00001108) Interrupt mask */
uint32_t RESERVED1;
__I uint32_t RIS; /* !< (@ 0x00001110) Raw interrupt status */
uint32_t RESERVED2;
__I uint32_t MIS; /* !< (@ 0x00001118) Masked interrupt status */
uint32_t RESERVED3;
__O uint32_t ISET; /* !< (@ 0x00001120) Interrupt set */
uint32_t RESERVED4;
__O uint32_t ICLR; /* !< (@ 0x00001128) Interrupt clear */
uint32_t RESERVED5;
} CPUSS_INT_GROUP_Regs;
/*@}*/ /* end of group CPUSS_INT_GROUP */
/** @addtogroup CPUSS
@{
*/
typedef struct {
uint32_t RESERVED0[1080];
__I uint32_t EVT_MODE; /* !< (@ 0x000010E0) Event Mode */
uint32_t RESERVED1[6];
__I uint32_t DESC; /* !< (@ 0x000010FC) Module Description */
CPUSS_INT_GROUP_Regs INT_GROUP[5]; /* !< (@ 0x00001100) */
uint32_t RESERVED2[68];
__IO uint32_t CTL; /* !< (@ 0x00001300) Prefetch/Cache control */
} CPUSS_Regs;
/*@}*/ /* end of group CPUSS */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* CPUSS Register Control Bits
******************************************************************************/
/* CPUSS_INT_GROUP_IIDX Bits */
/* CPUSS_INT_GROUP_IIDX[STAT] Bits */
#define CPUSS_INT_GROUP_IIDX_STAT_OFS (0) /* !< STAT Offset */
#define CPUSS_INT_GROUP_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */
#define CPUSS_INT_GROUP_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No pending interrupt */
#define CPUSS_INT_GROUP_IIDX_STAT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
#define CPUSS_INT_GROUP_IIDX_STAT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
#define CPUSS_INT_GROUP_IIDX_STAT_INT2 ((uint32_t)0x00000003U) /* !< Interrupt 2 */
#define CPUSS_INT_GROUP_IIDX_STAT_INT3 ((uint32_t)0x00000004U) /* !< Interrupt 3 */
#define CPUSS_INT_GROUP_IIDX_STAT_INT4 ((uint32_t)0x00000005U) /* !< Interrupt 4 */
#define CPUSS_INT_GROUP_IIDX_STAT_INT5 ((uint32_t)0x00000006U) /* !< Interrupt 5 */
#define CPUSS_INT_GROUP_IIDX_STAT_INT6 ((uint32_t)0x00000007U) /* !< Interrupt 6 */
#define CPUSS_INT_GROUP_IIDX_STAT_INT7 ((uint32_t)0x00000008U) /* !< Interrupt 7 */
/* CPUSS_INT_GROUP_IMASK Bits */
/* CPUSS_INT_GROUP_IMASK[INT] Bits */
#define CPUSS_INT_GROUP_IMASK_INT_OFS (0) /* !< INT Offset */
#define CPUSS_INT_GROUP_IMASK_INT_MASK ((uint32_t)0x000000FFU) /* !< Masks the corresponding interrupt */
#define CPUSS_INT_GROUP_IMASK_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
#define CPUSS_INT_GROUP_IMASK_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
#define CPUSS_INT_GROUP_IMASK_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
#define CPUSS_INT_GROUP_IMASK_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
#define CPUSS_INT_GROUP_IMASK_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
#define CPUSS_INT_GROUP_IMASK_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
#define CPUSS_INT_GROUP_IMASK_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
#define CPUSS_INT_GROUP_IMASK_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
/* CPUSS_INT_GROUP_RIS Bits */
/* CPUSS_INT_GROUP_RIS[INT] Bits */
#define CPUSS_INT_GROUP_RIS_INT_OFS (0) /* !< INT Offset */
#define CPUSS_INT_GROUP_RIS_INT_MASK ((uint32_t)0x000000FFU) /* !< Raw interrupt status for INT */
#define CPUSS_INT_GROUP_RIS_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
#define CPUSS_INT_GROUP_RIS_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
#define CPUSS_INT_GROUP_RIS_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
#define CPUSS_INT_GROUP_RIS_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
#define CPUSS_INT_GROUP_RIS_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
#define CPUSS_INT_GROUP_RIS_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
#define CPUSS_INT_GROUP_RIS_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
#define CPUSS_INT_GROUP_RIS_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
/* CPUSS_INT_GROUP_MIS Bits */
/* CPUSS_INT_GROUP_MIS[INT] Bits */
#define CPUSS_INT_GROUP_MIS_INT_OFS (0) /* !< INT Offset */
#define CPUSS_INT_GROUP_MIS_INT_MASK ((uint32_t)0x000000FFU) /* !< Masked interrupt status for INT0 */
#define CPUSS_INT_GROUP_MIS_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
#define CPUSS_INT_GROUP_MIS_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
#define CPUSS_INT_GROUP_MIS_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
#define CPUSS_INT_GROUP_MIS_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
#define CPUSS_INT_GROUP_MIS_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
#define CPUSS_INT_GROUP_MIS_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
#define CPUSS_INT_GROUP_MIS_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
#define CPUSS_INT_GROUP_MIS_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
/* CPUSS_INT_GROUP_ISET Bits */
/* CPUSS_INT_GROUP_ISET[INT] Bits */
#define CPUSS_INT_GROUP_ISET_INT_OFS (0) /* !< INT Offset */
#define CPUSS_INT_GROUP_ISET_INT_MASK ((uint32_t)0x000000FFU) /* !< Sets INT in RIS register */
#define CPUSS_INT_GROUP_ISET_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
#define CPUSS_INT_GROUP_ISET_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
#define CPUSS_INT_GROUP_ISET_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
#define CPUSS_INT_GROUP_ISET_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
#define CPUSS_INT_GROUP_ISET_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
#define CPUSS_INT_GROUP_ISET_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
#define CPUSS_INT_GROUP_ISET_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
#define CPUSS_INT_GROUP_ISET_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
/* CPUSS_INT_GROUP_ICLR Bits */
/* CPUSS_INT_GROUP_ICLR[INT] Bits */
#define CPUSS_INT_GROUP_ICLR_INT_OFS (0) /* !< INT Offset */
#define CPUSS_INT_GROUP_ICLR_INT_MASK ((uint32_t)0x000000FFU) /* !< Clears INT in RIS register */
#define CPUSS_INT_GROUP_ICLR_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
#define CPUSS_INT_GROUP_ICLR_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
#define CPUSS_INT_GROUP_ICLR_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
#define CPUSS_INT_GROUP_ICLR_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
#define CPUSS_INT_GROUP_ICLR_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
#define CPUSS_INT_GROUP_ICLR_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
#define CPUSS_INT_GROUP_ICLR_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
#define CPUSS_INT_GROUP_ICLR_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
/* CPUSS_EVT_MODE Bits */
/* CPUSS_EVT_MODE[INT_CFG] Bits */
#define CPUSS_EVT_MODE_INT_CFG_OFS (0) /* !< INT_CFG Offset */
#define CPUSS_EVT_MODE_INT_CFG_MASK ((uint32_t)0x00000003U) /* !< Event line mode select */
#define CPUSS_EVT_MODE_INT_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
disabled. */
#define CPUSS_EVT_MODE_INT_CFG_SOFTWARE ((uint32_t)0x00000001U) /* !< Event handled by software. Software
must clear the associated RIS flag. */
#define CPUSS_EVT_MODE_INT_CFG_HARDWARE ((uint32_t)0x00000002U) /* !< Event handled by hardware. The
hardware (another module) clears
automatically the associated RIS
flag. */
/* CPUSS_DESC Bits */
/* CPUSS_DESC[MINREV] Bits */
#define CPUSS_DESC_MINREV_OFS (0) /* !< MINREV Offset */
#define CPUSS_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */
/* CPUSS_DESC[MAJREV] Bits */
#define CPUSS_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */
#define CPUSS_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */
/* CPUSS_DESC[FEATUREVER] Bits */
#define CPUSS_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */
#define CPUSS_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module
*instance* */
/* CPUSS_DESC[MODULEID] Bits */
#define CPUSS_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */
#define CPUSS_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module identification contains a
unique peripheral identification
number. The assignments are
maintained in a central database for
all of the platform modules to ensure
uniqueness. */
/* CPUSS_CTL Bits */
/* CPUSS_CTL[PREFETCH] Bits */
#define CPUSS_CTL_PREFETCH_OFS (0) /* !< PREFETCH Offset */
#define CPUSS_CTL_PREFETCH_MASK ((uint32_t)0x00000001U) /* !< Used to enable/disable instruction
prefetch to Flash. */
#define CPUSS_CTL_PREFETCH_DISABLE ((uint32_t)0x00000000U) /* !< Disable instruction prefetch. */
#define CPUSS_CTL_PREFETCH_ENABLE ((uint32_t)0x00000001U) /* !< Enable instruction prefetch. */
/* CPUSS_CTL[ICACHE] Bits */
#define CPUSS_CTL_ICACHE_OFS (1) /* !< ICACHE Offset */
#define CPUSS_CTL_ICACHE_MASK ((uint32_t)0x00000002U) /* !< Used to enable/disable Instruction
caching on flash access. */
#define CPUSS_CTL_ICACHE_DISABLE ((uint32_t)0x00000000U) /* !< Disable instruction caching. */
#define CPUSS_CTL_ICACHE_ENABLE ((uint32_t)0x00000002U) /* !< Enable instruction caching. */
/* CPUSS_CTL[LITEN] Bits */
#define CPUSS_CTL_LITEN_OFS (2) /* !< LITEN Offset */
#define CPUSS_CTL_LITEN_MASK ((uint32_t)0x00000004U) /* !< Literal caching and prefetch
enable. This bit is a subset of
ICACHE/PREFETCH bit i.e. literal
caching or literal prefetching will
only happen if ICACHE or PREFETCH
bits have been set respectively When
enabled, the cache and prefetcher
structures inside CPUSS will cache
and prefetch literals When disabled,
the cache and prefetcher structures
inside CPUSS will not cache and
prefetch literals */
#define CPUSS_CTL_LITEN_DISABLE ((uint32_t)0x00000000U) /* !< Literal caching disabled */
#define CPUSS_CTL_LITEN_ENABLE ((uint32_t)0x00000004U) /* !< Literal caching enabled */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_m0p_hw_cpuss__include */
libraries/sdk/ti/devices/msp/peripherals/m0p/hw_debugss.h
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/*****************************************************************************
Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_m0p_hw_debugss__include
#define ti_devices_msp_peripherals_m0p_hw_debugss__include
/* Filename: hw_debugss.h */
/* Revised: 2023-05-10 21:16:53 */
/* Revision: 2f29710894b537f621c6ebedd563efb234664827 */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* DEBUGSS Registers
******************************************************************************/
#define DEBUGSS_CPU_INT_OFS ((uint32_t)0x00001020U)
/** @addtogroup DEBUGSS_CPU_INT
@{
*/
typedef struct {
__I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */
uint32_t RESERVED0;
__IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */
uint32_t RESERVED1;
__I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */
uint32_t RESERVED2;
__I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */
uint32_t RESERVED3;
__O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */
uint32_t RESERVED4;
__O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */
} DEBUGSS_CPU_INT_Regs;
/*@}*/ /* end of group DEBUGSS_CPU_INT */
/** @addtogroup DEBUGSS
@{
*/
typedef struct {
uint32_t RESERVED0[1032];
DEBUGSS_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */
uint32_t RESERVED1[37];
__I uint32_t EVT_MODE; /* !< (@ 0x000010E0) Event Mode */
uint32_t RESERVED2[6];
__I uint32_t DESC; /* !< (@ 0x000010FC) Module Description */
__I uint32_t TXD; /* !< (@ 0x00001100) Transmit data register */
__I uint32_t TXCTL; /* !< (@ 0x00001104) Transmit control register */
__IO uint32_t RXD; /* !< (@ 0x00001108) Receive data register */
__IO uint32_t RXCTL; /* !< (@ 0x0000110C) Receive control register */
uint32_t RESERVED3[60];
__I uint32_t SPECIAL_AUTH; /* !< (@ 0x00001200) Special enable authorization register */
uint32_t RESERVED4[3];
__I uint32_t APP_AUTH; /* !< (@ 0x00001210) Application CPU0 authorization register */
} DEBUGSS_Regs;
/*@}*/ /* end of group DEBUGSS */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* DEBUGSS Register Control Bits
******************************************************************************/
/* DEBUGSS_IIDX Bits */
/* DEBUGSS_IIDX[STAT] Bits */
#define DEBUGSS_IIDX_STAT_OFS (0) /* !< STAT Offset */
#define DEBUGSS_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */
#define DEBUGSS_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No pending interrupt request */
#define DEBUGSS_IIDX_STAT_TXIFG ((uint32_t)0x00000001U) /* !< TX interrupt */
#define DEBUGSS_IIDX_STAT_RXIFG ((uint32_t)0x00000002U) /* !< RX interrupt */
#define DEBUGSS_IIDX_STAT_PWRUP ((uint32_t)0x00000003U) /* !< Power-up interrupt. A debug session
has started. */
#define DEBUGSS_IIDX_STAT_PWRDWN ((uint32_t)0x00000004U) /* !< Power-up interrupt. A debug session
has started. */
/* DEBUGSS_IMASK Bits */
/* DEBUGSS_IMASK[TXIFG] Bits */
#define DEBUGSS_IMASK_TXIFG_OFS (0) /* !< TXIFG Offset */
#define DEBUGSS_IMASK_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Masks TXIFG in MIS register */
#define DEBUGSS_IMASK_TXIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define DEBUGSS_IMASK_TXIFG_SET ((uint32_t)0x00000001U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* DEBUGSS_IMASK[RXIFG] Bits */
#define DEBUGSS_IMASK_RXIFG_OFS (1) /* !< RXIFG Offset */
#define DEBUGSS_IMASK_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Masks RXIFG in MIS register */
#define DEBUGSS_IMASK_RXIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define DEBUGSS_IMASK_RXIFG_SET ((uint32_t)0x00000002U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* DEBUGSS_IMASK[PWRUPIFG] Bits */
#define DEBUGSS_IMASK_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
#define DEBUGSS_IMASK_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Masks PWRUPIFG in MIS register */
#define DEBUGSS_IMASK_PWRUPIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define DEBUGSS_IMASK_PWRUPIFG_SET ((uint32_t)0x00000004U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* DEBUGSS_IMASK[PWRDWNIFG] Bits */
#define DEBUGSS_IMASK_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
#define DEBUGSS_IMASK_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Masks PWRDWNIFG in MIS register */
#define DEBUGSS_IMASK_PWRDWNIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define DEBUGSS_IMASK_PWRDWNIFG_SET ((uint32_t)0x00000008U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* DEBUGSS_RIS Bits */
/* DEBUGSS_RIS[TXIFG] Bits */
#define DEBUGSS_RIS_TXIFG_OFS (0) /* !< TXIFG Offset */
#define DEBUGSS_RIS_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Raw interrupt status for TXIFG */
#define DEBUGSS_RIS_TXIFG_CLR ((uint32_t)0x00000000U) /* !< TXIFG did not occur */
#define DEBUGSS_RIS_TXIFG_SET ((uint32_t)0x00000001U) /* !< TXIFG occurred */
/* DEBUGSS_RIS[RXIFG] Bits */
#define DEBUGSS_RIS_RXIFG_OFS (1) /* !< RXIFG Offset */
#define DEBUGSS_RIS_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Raw interrupt status for RXIFG */
#define DEBUGSS_RIS_RXIFG_CLR ((uint32_t)0x00000000U) /* !< RXIFG did not occur */
#define DEBUGSS_RIS_RXIFG_SET ((uint32_t)0x00000002U) /* !< RXIFG occurred */
/* DEBUGSS_RIS[PWRUPIFG] Bits */
#define DEBUGSS_RIS_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
#define DEBUGSS_RIS_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Raw interrupt status for PWRUPIFG */
#define DEBUGSS_RIS_PWRUPIFG_CLR ((uint32_t)0x00000000U) /* !< PWRUPIFG did not occur */
#define DEBUGSS_RIS_PWRUPIFG_SET ((uint32_t)0x00000004U) /* !< PWRUPIFG occurred */
/* DEBUGSS_RIS[PWRDWNIFG] Bits */
#define DEBUGSS_RIS_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
#define DEBUGSS_RIS_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Raw interrupt status for PWRDWNIFG */
#define DEBUGSS_RIS_PWRDWNIFG_CLR ((uint32_t)0x00000000U) /* !< PWRUPIFG did not occur */
#define DEBUGSS_RIS_PWRDWNIFG_SET ((uint32_t)0x00000008U) /* !< PWRUPIFG occurred */
/* DEBUGSS_MIS Bits */
/* DEBUGSS_MIS[TXIFG] Bits */
#define DEBUGSS_MIS_TXIFG_OFS (0) /* !< TXIFG Offset */
#define DEBUGSS_MIS_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Masked interrupt status for TXIFG */
#define DEBUGSS_MIS_TXIFG_CLR ((uint32_t)0x00000000U) /* !< TXIFG did not request an interrupt
service routine */
#define DEBUGSS_MIS_TXIFG_SET ((uint32_t)0x00000001U) /* !< TXIFG requests an interrupt service
routine */
/* DEBUGSS_MIS[RXIFG] Bits */
#define DEBUGSS_MIS_RXIFG_OFS (1) /* !< RXIFG Offset */
#define DEBUGSS_MIS_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt status for RXIFG */
#define DEBUGSS_MIS_RXIFG_CLR ((uint32_t)0x00000000U) /* !< RXIFG did not request an interrupt
service routine */
#define DEBUGSS_MIS_RXIFG_SET ((uint32_t)0x00000002U) /* !< RXIFG requests an interrupt service
routine */
/* DEBUGSS_MIS[PWRUPIFG] Bits */
#define DEBUGSS_MIS_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
#define DEBUGSS_MIS_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Masked interrupt status for
PWRUPIFG */
#define DEBUGSS_MIS_PWRUPIFG_CLR ((uint32_t)0x00000000U) /* !< PWRUPIFG did not request an
interrupt service routine */
#define DEBUGSS_MIS_PWRUPIFG_SET ((uint32_t)0x00000004U) /* !< PWRUPIFG requests an interrupt
service routine */
/* DEBUGSS_MIS[PWRDWNIFG] Bits */
#define DEBUGSS_MIS_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
#define DEBUGSS_MIS_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Masked interrupt status for
PWRDWNIFG */
#define DEBUGSS_MIS_PWRDWNIFG_CLR ((uint32_t)0x00000000U) /* !< PWRUPIFG did not request an
interrupt service routine */
#define DEBUGSS_MIS_PWRDWNIFG_SET ((uint32_t)0x00000008U) /* !< PWRUPIFG requests an interrupt
service routine */
/* DEBUGSS_ISET Bits */
/* DEBUGSS_ISET[TXIFG] Bits */
#define DEBUGSS_ISET_TXIFG_OFS (0) /* !< TXIFG Offset */
#define DEBUGSS_ISET_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Sets TXIFG in RIS register */
#define DEBUGSS_ISET_TXIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ISET_TXIFG_SET ((uint32_t)0x00000001U) /* !< RIS bit corresponding to TXIFG is
set */
/* DEBUGSS_ISET[RXIFG] Bits */
#define DEBUGSS_ISET_RXIFG_OFS (1) /* !< RXIFG Offset */
#define DEBUGSS_ISET_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Sets RXIFG in RIS register */
#define DEBUGSS_ISET_RXIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ISET_RXIFG_SET ((uint32_t)0x00000002U) /* !< RIS bit corresponding to RXIFG is
set */
/* DEBUGSS_ISET[PWRUPIFG] Bits */
#define DEBUGSS_ISET_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
#define DEBUGSS_ISET_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Sets PWRUPIFG in RIS register */
#define DEBUGSS_ISET_PWRUPIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ISET_PWRUPIFG_SET ((uint32_t)0x00000004U) /* !< RIS bit corresponding to PWRUPIFG
is set */
/* DEBUGSS_ISET[PWRDWNIFG] Bits */
#define DEBUGSS_ISET_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
#define DEBUGSS_ISET_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Sets PWRDWNIFG in RIS register */
#define DEBUGSS_ISET_PWRDWNIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ISET_PWRDWNIFG_SET ((uint32_t)0x00000008U) /* !< RIS bit corresponding to PWRUPIFG
is set */
/* DEBUGSS_ICLR Bits */
/* DEBUGSS_ICLR[TXIFG] Bits */
#define DEBUGSS_ICLR_TXIFG_OFS (0) /* !< TXIFG Offset */
#define DEBUGSS_ICLR_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Clears TXIFG in RIS register */
#define DEBUGSS_ICLR_TXIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ICLR_TXIFG_CLR ((uint32_t)0x00000001U) /* !< RIS bit corresponding to TXIFG is
cleared */
/* DEBUGSS_ICLR[RXIFG] Bits */
#define DEBUGSS_ICLR_RXIFG_OFS (1) /* !< RXIFG Offset */
#define DEBUGSS_ICLR_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Clears RXIFG in RIS register */
#define DEBUGSS_ICLR_RXIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ICLR_RXIFG_CLR ((uint32_t)0x00000002U) /* !< RIS bit corresponding to RXIFG is
cleared */
/* DEBUGSS_ICLR[PWRUPIFG] Bits */
#define DEBUGSS_ICLR_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
#define DEBUGSS_ICLR_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Clears PWRUPIFG in RIS register */
#define DEBUGSS_ICLR_PWRUPIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ICLR_PWRUPIFG_CLR ((uint32_t)0x00000004U) /* !< RIS bit corresponding to PWRUPIFG
is cleared */
/* DEBUGSS_ICLR[PWRDWNIFG] Bits */
#define DEBUGSS_ICLR_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
#define DEBUGSS_ICLR_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Clears PWRDWNIFG in RIS register */
#define DEBUGSS_ICLR_PWRDWNIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ICLR_PWRDWNIFG_CLR ((uint32_t)0x00000008U) /* !< RIS bit corresponding to PWRUPIFG
is cleared */
/* DEBUGSS_EVT_MODE Bits */
/* DEBUGSS_EVT_MODE[INT0_CFG] Bits */
#define DEBUGSS_EVT_MODE_INT0_CFG_OFS (0) /* !< INT0_CFG Offset */
#define DEBUGSS_EVT_MODE_INT0_CFG_MASK ((uint32_t)0x00000003U) /* !< Event line mode select for
peripheral events */
#define DEBUGSS_EVT_MODE_INT0_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
disabled. */
#define DEBUGSS_EVT_MODE_INT0_CFG_SOFTWARE ((uint32_t)0x00000001U) /* !< The interrupt or event line is in
software mode. Software must clear
the RIS. */
#define DEBUGSS_EVT_MODE_INT0_CFG_HARDWARE ((uint32_t)0x00000002U) /* !< The interrupt or event line is in
hardware mode. The hardware (another
module) clears automatically the
associated RIS flag. */
/* DEBUGSS_DESC Bits */
/* DEBUGSS_DESC[MINREV] Bits */
#define DEBUGSS_DESC_MINREV_OFS (0) /* !< MINREV Offset */
#define DEBUGSS_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */
/* DEBUGSS_DESC[MAJREV] Bits */
#define DEBUGSS_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */
#define DEBUGSS_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */
/* DEBUGSS_DESC[INSTNUM] Bits */
#define DEBUGSS_DESC_INSTNUM_OFS (8) /* !< INSTNUM Offset */
#define DEBUGSS_DESC_INSTNUM_MASK ((uint32_t)0x00000F00U) /* !< Instance Number within the device.
This will be a parameter to the RTL
for modules that can have multiple
instances */
/* DEBUGSS_DESC[FEATUREVER] Bits */
#define DEBUGSS_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */
#define DEBUGSS_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module
*instance* */
/* DEBUGSS_DESC[MODULEID] Bits */
#define DEBUGSS_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */
#define DEBUGSS_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module identification contains a
unique peripheral identification
number. The assignments are
maintained in a central database for
all of the platform modules to ensure
uniqueness. */
/* DEBUGSS_TXD Bits */
/* DEBUGSS_TXD[TX_DATA] Bits */
#define DEBUGSS_TXD_TX_DATA_OFS (0) /* !< TX_DATA Offset */
#define DEBUGSS_TXD_TX_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Contains data written by an
external debug tool to the SEC-AP
TXDATA register */
/* DEBUGSS_TXCTL Bits */
/* DEBUGSS_TXCTL[TRANSMIT] Bits */
#define DEBUGSS_TXCTL_TRANSMIT_OFS (0) /* !< TRANSMIT Offset */
#define DEBUGSS_TXCTL_TRANSMIT_MASK ((uint32_t)0x00000001U) /* !< Indicates data request in DSSM.TXD,
set on write via Debug AP to
DSSM.TXD. A read of the DSSM.TXD
register by SW will clear the TX
field. The tool can check that TXD is
empty by reading this field. */
#define DEBUGSS_TXCTL_TRANSMIT_EMPTY ((uint32_t)0x00000000U) /* !< TXD is empty */
#define DEBUGSS_TXCTL_TRANSMIT_FULL ((uint32_t)0x00000001U) /* !< TXD is full */
/* DEBUGSS_TXCTL[TRANSMIT_FLAGS] Bits */
#define DEBUGSS_TXCTL_TRANSMIT_FLAGS_OFS (1) /* !< TRANSMIT_FLAGS Offset */
#define DEBUGSS_TXCTL_TRANSMIT_FLAGS_MASK ((uint32_t)0xFFFFFFFEU) /* !< Generic TX flags that can be set by
external debug tool. Functionality is
defined by SW. */
/* DEBUGSS_RXD Bits */
/* DEBUGSS_RXD[RX_DATA] Bits */
#define DEBUGSS_RXD_RX_DATA_OFS (0) /* !< RX_DATA Offset */
#define DEBUGSS_RXD_RX_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Contains data written by SM/OW. */
/* DEBUGSS_RXCTL Bits */
/* DEBUGSS_RXCTL[RECEIVE] Bits */
#define DEBUGSS_RXCTL_RECEIVE_OFS (0) /* !< RECEIVE Offset */
#define DEBUGSS_RXCTL_RECEIVE_MASK ((uint32_t)0x00000001U) /* !< Indicates SW write to the DSSM.RXD
register. A read of the DSSM.RXD
register by SWD Access Port will
clear the RX field. */
#define DEBUGSS_RXCTL_RECEIVE_EMPTY ((uint32_t)0x00000000U) /* !< RXD empty */
#define DEBUGSS_RXCTL_RECEIVE_FULL ((uint32_t)0x00000001U) /* !< RXD full */
/* DEBUGSS_RXCTL[RECEIVE_FLAGS] Bits */
#define DEBUGSS_RXCTL_RECEIVE_FLAGS_OFS (1) /* !< RECEIVE_FLAGS Offset */
#define DEBUGSS_RXCTL_RECEIVE_FLAGS_MASK ((uint32_t)0x000000FEU) /* !< Generic RX flags that can be set by
SW and read by external debug tool.
Functionality is defined by SW. */
/* DEBUGSS_SPECIAL_AUTH Bits */
/* DEBUGSS_SPECIAL_AUTH[SECAPEN] Bits */
#define DEBUGSS_SPECIAL_AUTH_SECAPEN_OFS (0) /* !< SECAPEN Offset */
#define DEBUGSS_SPECIAL_AUTH_SECAPEN_MASK ((uint32_t)0x00000001U) /* !< An active high input. When asserted
(and SWD access is also permitted),
the debug tools can use the
Security-AP to communicate with
security control logic. When
deasserted, a DAPBUS firewall will
isolate the AP and prevent access to
the Security-AP. */
#define DEBUGSS_SPECIAL_AUTH_SECAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable SEC-AP */
#define DEBUGSS_SPECIAL_AUTH_SECAPEN_ENABLE ((uint32_t)0x00000001U) /* !< Enable SEC-AP */
/* DEBUGSS_SPECIAL_AUTH[SWDPORTEN] Bits */
#define DEBUGSS_SPECIAL_AUTH_SWDPORTEN_OFS (1) /* !< SWDPORTEN Offset */
#define DEBUGSS_SPECIAL_AUTH_SWDPORTEN_MASK ((uint32_t)0x00000002U) /* !< When asserted, the SW-DP functions
normally. When deasserted, the SW-DP
effectively disables all external
debug access. */
#define DEBUGSS_SPECIAL_AUTH_SWDPORTEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable SWD port */
#define DEBUGSS_SPECIAL_AUTH_SWDPORTEN_ENABLE ((uint32_t)0x00000002U) /* !< Enable SWD port */
/* DEBUGSS_SPECIAL_AUTH[DFTAPEN] Bits */
#define DEBUGSS_SPECIAL_AUTH_DFTAPEN_OFS (2) /* !< DFTAPEN Offset */
#define DEBUGSS_SPECIAL_AUTH_DFTAPEN_MASK ((uint32_t)0x00000004U) /* !< An active high input. When asserted
(and SWD access is also permitted),
the debug tools can then access the
DFT-AP external to the DebugSS lite.
When deasserted, a DAPBUS firewall
will isolate the AP and prevent
access. */
#define DEBUGSS_SPECIAL_AUTH_DFTAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable DFT-TAP */
#define DEBUGSS_SPECIAL_AUTH_DFTAPEN_ENABLE ((uint32_t)0x00000004U) /* !< Enable DFT-TAP */
/* DEBUGSS_SPECIAL_AUTH[ETAPEN] Bits */
#define DEBUGSS_SPECIAL_AUTH_ETAPEN_OFS (3) /* !< ETAPEN Offset */
#define DEBUGSS_SPECIAL_AUTH_ETAPEN_MASK ((uint32_t)0x00000008U) /* !< An active high input. When asserted
(and SWD access is also permitted),
the debug tools can then access an
ET-AP external to the DebugSS lite.
When deasserted, a DAPBUS firewall
will isolate the AP and prevent
access. */
#define DEBUGSS_SPECIAL_AUTH_ETAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable ET+ -AP */
#define DEBUGSS_SPECIAL_AUTH_ETAPEN_ENABLE ((uint32_t)0x00000008U) /* !< Enable ET+ -AP */
/* DEBUGSS_SPECIAL_AUTH[CFGAPEN] Bits */
#define DEBUGSS_SPECIAL_AUTH_CFGAPEN_OFS (4) /* !< CFGAPEN Offset */
#define DEBUGSS_SPECIAL_AUTH_CFGAPEN_MASK ((uint32_t)0x00000010U) /* !< An active high input. When asserted
(and SWD access is also permitted),
the debug tools can use the Config-AP
to read device configuration
information. When deasserted, a
DAPBUS firewall will isolate the AP
and prevent access to the Config-AP. */
#define DEBUGSS_SPECIAL_AUTH_CFGAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable CFG-AP */
#define DEBUGSS_SPECIAL_AUTH_CFGAPEN_ENABLE ((uint32_t)0x00000010U) /* !< Enable CFG-AP */
/* DEBUGSS_SPECIAL_AUTH[AHBAPEN] Bits */
#define DEBUGSS_SPECIAL_AUTH_AHBAPEN_OFS (5) /* !< AHBAPEN Offset */
#define DEBUGSS_SPECIAL_AUTH_AHBAPEN_MASK ((uint32_t)0x00000020U) /* !< Disabling / enabling debug access
to the M0+ Core via the AHB-AP DAP
bus isolation. */
#define DEBUGSS_SPECIAL_AUTH_AHBAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable AHB-AP */
#define DEBUGSS_SPECIAL_AUTH_AHBAPEN_ENABLE ((uint32_t)0x00000020U) /* !< Enable AHB-AP */
/* DEBUGSS_SPECIAL_AUTH[PWRAPEN] Bits */
#define DEBUGSS_SPECIAL_AUTH_PWRAPEN_OFS (6) /* !< PWRAPEN Offset */
#define DEBUGSS_SPECIAL_AUTH_PWRAPEN_MASK ((uint32_t)0x00000040U) /* !< An active high input. When asserted
(and SWD access is also permitted),
the debug tools can then access the
PWR-AP to power and reset state of
the CPU. When deasserted, a DAPBUS
firewall will isolate the AP and
prevent access. */
#define DEBUGSS_SPECIAL_AUTH_PWRAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable PWR-AP */
#define DEBUGSS_SPECIAL_AUTH_PWRAPEN_ENABLE ((uint32_t)0x00000040U) /* !< Enable PWR-AP */
/* DEBUGSS_APP_AUTH Bits */
/* DEBUGSS_APP_AUTH[DBGEN] Bits */
#define DEBUGSS_APP_AUTH_DBGEN_OFS (0) /* !< DBGEN Offset */
#define DEBUGSS_APP_AUTH_DBGEN_MASK ((uint32_t)0x00000001U) /* !< Controls invasive debug enable. */
#define DEBUGSS_APP_AUTH_DBGEN_DISABLE ((uint32_t)0x00000000U) /* !< Invasive debug disabled */
#define DEBUGSS_APP_AUTH_DBGEN_ENABLE ((uint32_t)0x00000001U) /* !< Invasive debug enabled */
/* DEBUGSS_APP_AUTH[NIDEN] Bits */
#define DEBUGSS_APP_AUTH_NIDEN_OFS (1) /* !< NIDEN Offset */
#define DEBUGSS_APP_AUTH_NIDEN_MASK ((uint32_t)0x00000002U) /* !< Controls non-invasive debug enable. */
#define DEBUGSS_APP_AUTH_NIDEN_DISABLE ((uint32_t)0x00000000U) /* !< Non-invasive debug disabled */
#define DEBUGSS_APP_AUTH_NIDEN_ENABLE ((uint32_t)0x00000002U) /* !< Non-invasive debug enabled */
/* DEBUGSS_APP_AUTH[SPIDEN] Bits */
#define DEBUGSS_APP_AUTH_SPIDEN_OFS (2) /* !< SPIDEN Offset */
#define DEBUGSS_APP_AUTH_SPIDEN_MASK ((uint32_t)0x00000004U) /* !< Secure invasive debug enable. */
#define DEBUGSS_APP_AUTH_SPIDEN_DISABLE ((uint32_t)0x00000000U) /* !< Invasive debug disabled */
#define DEBUGSS_APP_AUTH_SPIDEN_ENABLE ((uint32_t)0x00000004U) /* !< Invasive debug enabled */
/* DEBUGSS_APP_AUTH[SPNIDEN] Bits */
#define DEBUGSS_APP_AUTH_SPNIDEN_OFS (3) /* !< SPNIDEN Offset */
#define DEBUGSS_APP_AUTH_SPNIDEN_MASK ((uint32_t)0x00000008U) /* !< Secure non-invasive debug enable. */
#define DEBUGSS_APP_AUTH_SPNIDEN_DISABLE ((uint32_t)0x00000000U) /* !< Invasive debug disabled */
#define DEBUGSS_APP_AUTH_SPNIDEN_ENABLE ((uint32_t)0x00000008U) /* !< Invasive debug enabled */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_m0p_hw_debugss__include */
libraries/sdk/ti/devices/msp/peripherals/m0p/hw_factoryregion.h
+441
View File
@@ -0,0 +1,441 @@
/*****************************************************************************
Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_hw_factoryregion__include
#define ti_devices_msp_peripherals_hw_factoryregion__include
/* This preliminary header file does not have a version number */
/* MMR repo: https://bitbucket.itg.ti.com/projects/cmcu_msp65soc/repos/trim_platform_constants */
/* MMR revision: ff4b6bcad5d93ca548bdb94b818a30dc3f4acd3f */
/* Generator revision: c98c4ac511e2bd0d918c5d427bd46b7a359dacf1
(MInT: ec7ec7482a60c6871be32db8b378ec27aa4771f6) */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* FACTORYREGION Registers
******************************************************************************/
#define FACTORYREGION_OPEN_OFS ((uint32_t)0x41C40000U)
/** @addtogroup FACTORYREGION_OPEN
@{
*/
typedef struct {
__I uint32_t TRACEID; /* !< (@ 0x41C40000) Defined by TI, during ATE, based on wafer */
__I uint32_t DEVICEID; /* !< (@ 0x41C40004) This is the JTAGIDCODE that comes from the Ramp
system */
__I uint32_t USERID; /* !< (@ 0x41C40008) Defined by TI, depending on device spin */
__I uint32_t BSLPIN_UART; /* !< (@ 0x41C4000C) BSL UART Pin Configuration */
__I uint32_t BSLPIN_I2C; /* !< (@ 0x41C40010) BSL I2C Pin Configuration */
__I uint32_t BSLPIN_INVOKE; /* !< (@ 0x41C40014) BSL Pin Invocation Configuration */
__I uint32_t SRAMFLASH; /* !< (@ 0x41C40018) */
__I uint32_t PLLSTARTUP0_4_8MHZ; /* !< (@ 0x41C4001C) */
__I uint32_t PLLSTARTUP1_4_8MHZ; /* !< (@ 0x41C40020) System PLL Paramater 1 MMR --- Data from Flash
Table Lookup */
__I uint32_t PLLSTARTUP0_8_16MHZ; /* !< (@ 0x41C40024) */
__I uint32_t PLLSTARTUP1_8_16MHZ; /* !< (@ 0x41C40028) System PLL Paramater 1 MMR --- Data from Flash
Table Lookup */
__I uint32_t PLLSTARTUP0_16_32MHZ; /* !< (@ 0x41C4002C) */
__I uint32_t PLLSTARTUP1_16_32MHZ; /* !< (@ 0x41C40030) System PLL Paramater 1 MMR --- Data from Flash
Table Lookup */
__I uint32_t PLLSTARTUP0_32_48MHZ; /* !< (@ 0x41C40034) */
__I uint32_t PLLSTARTUP1_32_48MHZ; /* !< (@ 0x41C40038) System PLL Paramater 1 MMR --- Data from Flash
Table Lookup */
__I uint32_t TEMP_SENSE0; /* !< (@ 0x41C4003C) Temperature sensor room temperature calibration
code. This is ADC conversion results of temperature sensor output
voltage. Included in BOOTCRC calculation. */
__I uint32_t RESERVED0; /* !< (@ 0x41C40040) */
__I uint32_t RESERVED1; /* !< (@ 0x41C40044) */
__I uint32_t RESERVED2; /* !< (@ 0x41C40048) */
__I uint32_t RESERVED3; /* !< (@ 0x41C4004C) */
__I uint32_t RESERVED4; /* !< (@ 0x41C40050) */
__I uint32_t RESERVED5; /* !< (@ 0x41C40054) */
__I uint32_t RESERVED6; /* !< (@ 0x41C40058) */
__I uint32_t RESERVED7; /* !< (@ 0x41C4005C) */
__I uint32_t RESERVED8; /* !< (@ 0x41C40060) */
__I uint32_t RESERVED9; /* !< (@ 0x41C40064) */
__I uint32_t RESERVED10; /* !< (@ 0x41C40068) */
__I uint32_t RESERVED11; /* !< (@ 0x41C4006C) */
__I uint32_t RESERVED12; /* !< (@ 0x41C40070) */
__I uint32_t RESERVED13; /* !< (@ 0x41C40074) */
__I uint32_t RESERVED14; /* !< (@ 0x41C40078) */
__I uint32_t BOOTCRC; /* !< (@ 0x41C4007C) BOOTCRC records the 32-bit CRC of all locations in
OPEN including reserved locations. */
} FACTORYREGION_OPEN_Regs;
/*@}*/ /* end of group FACTORYREGION_OPEN */
/** @addtogroup FACTORYREGION
@{
*/
typedef struct {
uint32_t RESERVED0[275841024];
FACTORYREGION_OPEN_Regs OPEN; /* !< (@ 0x41C40000) Customer-visible data (IDs, PLL trims,...) */
} FACTORYREGION_Regs;
/*@}*/ /* end of group FACTORYREGION */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* FACTORYREGION Register Control Bits
******************************************************************************/
/* FACTORYREGION_TRACEID Bits */
/* FACTORYREGION_TRACEID[DATA] Bits */
#define FACTORYREGION_TRACEID_DATA_OFS (0) /* !< DATA Offset */
#define FACTORYREGION_TRACEID_DATA_MASK ((uint32_t)0xFFFFFFFFU)
/* FACTORYREGION_DEVICEID Bits */
/* FACTORYREGION_DEVICEID[VERSION] Bits */
#define FACTORYREGION_DEVICEID_VERSION_OFS (28) /* !< VERSION Offset */
#define FACTORYREGION_DEVICEID_VERSION_MASK ((uint32_t)0xF0000000U) /* !< Revision of the device. This field
should change each time that the
logic or mask set of the device is
revised. */
/* FACTORYREGION_DEVICEID[PARTNUM] Bits */
#define FACTORYREGION_DEVICEID_PARTNUM_OFS (12) /* !< PARTNUM Offset */
#define FACTORYREGION_DEVICEID_PARTNUM_MASK ((uint32_t)0x0FFFF000U) /* !< Part number of the device. */
/* FACTORYREGION_DEVICEID[MANUFACTURER] Bits */
#define FACTORYREGION_DEVICEID_MANUFACTURER_OFS (1) /* !< MANUFACTURER Offset */
#define FACTORYREGION_DEVICEID_MANUFACTURER_MASK ((uint32_t)0x00000FFEU) /* !< TI's JEDEC bank and company code,
which is: 00000010111b */
/* FACTORYREGION_DEVICEID[ALWAYS_1] Bits */
#define FACTORYREGION_DEVICEID_ALWAYS_1_OFS (0) /* !< ALWAYS_1 Offset */
#define FACTORYREGION_DEVICEID_ALWAYS_1_MASK ((uint32_t)0x00000001U) /* !< This is always 1 */
/* FACTORYREGION_USERID Bits */
/* FACTORYREGION_USERID[PART] Bits */
#define FACTORYREGION_USERID_PART_OFS (0) /* !< PART Offset */
#define FACTORYREGION_USERID_PART_MASK ((uint32_t)0x0000FFFFU) /* !< Bit pattern that uniquely
identifying a part. This is used to
identify the specific part based on
the die identified in
DEVICEID.device. This number shall be
selected at random among the
remaining numbers for DEVICEID.device
such that the order of creation
cannot be inferred by the number.
This value does not encode the part
number directly. */
/* FACTORYREGION_USERID[VARIANT] Bits */
#define FACTORYREGION_USERID_VARIANT_OFS (16) /* !< VARIANT Offset */
#define FACTORYREGION_USERID_VARIANT_MASK ((uint32_t)0x00FF0000U) /* !< Bit pattern uniquely identifying a
variant of a part. This is used to
indicate memory or package variations
of the same part number. This number
shall be selected at random among the
remaining numbers for the relevant
combination of IDCODE.device and
USERCODE.part such that the order of
creation cannot be inferred by the
number. The variant number does not
encode specifics of the variant
directly. */
/* FACTORYREGION_USERID[MINORREV] Bits */
#define FACTORYREGION_USERID_MINORREV_OFS (24) /* !< MINORREV Offset */
#define FACTORYREGION_USERID_MINORREV_MASK ((uint32_t)0x0F000000U) /* !< Monotonic increasing value
indicating a new revision of the SKU
that preserves compatibility with
lesser minorrev values. New
capability may be introduced such
that lesser minorrev numbers may not
be compatible with greater if the new
capability is used. */
/* FACTORYREGION_USERID[MAJORREV] Bits */
#define FACTORYREGION_USERID_MAJORREV_OFS (28) /* !< MAJORREV Offset */
#define FACTORYREGION_USERID_MAJORREV_MASK ((uint32_t)0x70000000U) /* !< Monotonic increasing value
indicating a new revision of the SKU
significant enough that users of the
device may have to revise PCB or or
software design */
/* FACTORYREGION_USERID[START] Bits */
#define FACTORYREGION_USERID_START_OFS (31) /* !< START Offset */
#define FACTORYREGION_USERID_START_MASK ((uint32_t)0x80000000U)
/* FACTORYREGION_BSLPIN_UART Bits */
/* FACTORYREGION_BSLPIN_UART[UART_RXD_PAD] Bits */
#define FACTORYREGION_BSLPIN_UART_UART_RXD_PAD_OFS (0) /* !< UART_RXD_PAD Offset */
#define FACTORYREGION_BSLPIN_UART_UART_RXD_PAD_MASK ((uint32_t)0x000000FFU) /* !< UART RXD Pad used by BSL */
/* FACTORYREGION_BSLPIN_UART[UART_RXD_PF] Bits */
#define FACTORYREGION_BSLPIN_UART_UART_RXD_PF_OFS (8) /* !< UART_RXD_PF Offset */
#define FACTORYREGION_BSLPIN_UART_UART_RXD_PF_MASK ((uint32_t)0x0000FF00U) /* !< UART RXD Pin Function Selection
Value */
/* FACTORYREGION_BSLPIN_UART[UART_TXD_PAD] Bits */
#define FACTORYREGION_BSLPIN_UART_UART_TXD_PAD_OFS (16) /* !< UART_TXD_PAD Offset */
#define FACTORYREGION_BSLPIN_UART_UART_TXD_PAD_MASK ((uint32_t)0x00FF0000U) /* !< UART TXD Pin used by BSL */
/* FACTORYREGION_BSLPIN_UART[UART_TXD_PF] Bits */
#define FACTORYREGION_BSLPIN_UART_UART_TXD_PF_OFS (24) /* !< UART_TXD_PF Offset */
#define FACTORYREGION_BSLPIN_UART_UART_TXD_PF_MASK ((uint32_t)0xFF000000U) /* !< UART TXD Pin Function Selection
Value */
/* FACTORYREGION_BSLPIN_I2C Bits */
/* FACTORYREGION_BSLPIN_I2C[I2C_SDA_PAD] Bits */
#define FACTORYREGION_BSLPIN_I2C_I2C_SDA_PAD_OFS (0) /* !< I2C_SDA_PAD Offset */
#define FACTORYREGION_BSLPIN_I2C_I2C_SDA_PAD_MASK ((uint32_t)0x000000FFU) /* !< I2C SDA Pin used by BSL */
/* FACTORYREGION_BSLPIN_I2C[I2C_SDA_PF] Bits */
#define FACTORYREGION_BSLPIN_I2C_I2C_SDA_PF_OFS (8) /* !< I2C_SDA_PF Offset */
#define FACTORYREGION_BSLPIN_I2C_I2C_SDA_PF_MASK ((uint32_t)0x0000FF00U) /* !< I2C SDA Pin Function Selection
Value */
/* FACTORYREGION_BSLPIN_I2C[I2C_SCL_PAD] Bits */
#define FACTORYREGION_BSLPIN_I2C_I2C_SCL_PAD_OFS (16) /* !< I2C_SCL_PAD Offset */
#define FACTORYREGION_BSLPIN_I2C_I2C_SCL_PAD_MASK ((uint32_t)0x00FF0000U) /* !< I2C SCL Pin used by BSL */
/* FACTORYREGION_BSLPIN_I2C[I2C_SCL_PF] Bits */
#define FACTORYREGION_BSLPIN_I2C_I2C_SCL_PF_OFS (24) /* !< I2C_SCL_PF Offset */
#define FACTORYREGION_BSLPIN_I2C_I2C_SCL_PF_MASK ((uint32_t)0xFF000000U) /* !< I2C SCL Pin Function Selection
Value */
/* FACTORYREGION_BSLPIN_INVOKE Bits */
/* FACTORYREGION_BSLPIN_INVOKE[BSL_PAD] Bits */
#define FACTORYREGION_BSLPIN_INVOKE_BSL_PAD_OFS (0) /* !< BSL_PAD Offset */
#define FACTORYREGION_BSLPIN_INVOKE_BSL_PAD_MASK ((uint32_t)0x0000007FU) /* !< BSL Invocation Pin Number */
/* FACTORYREGION_BSLPIN_INVOKE[GPIO_LEVEL] Bits */
#define FACTORYREGION_BSLPIN_INVOKE_GPIO_LEVEL_OFS (7) /* !< GPIO_LEVEL Offset */
#define FACTORYREGION_BSLPIN_INVOKE_GPIO_LEVEL_MASK ((uint32_t)0x00000080U) /* !< GPIO Level Configuration for BSL
Invocation */
/* FACTORYREGION_BSLPIN_INVOKE[GPIO_PIN_SEL] Bits */
#define FACTORYREGION_BSLPIN_INVOKE_GPIO_PIN_SEL_OFS (8) /* !< GPIO_PIN_SEL Offset */
#define FACTORYREGION_BSLPIN_INVOKE_GPIO_PIN_SEL_MASK ((uint32_t)0x00001F00U) /* !< GPIO Pin Number in GPIO Module */
/* FACTORYREGION_BSLPIN_INVOKE[GPIO_REG_SEL] Bits */
#define FACTORYREGION_BSLPIN_INVOKE_GPIO_REG_SEL_OFS (13) /* !< GPIO_REG_SEL Offset */
#define FACTORYREGION_BSLPIN_INVOKE_GPIO_REG_SEL_MASK ((uint32_t)0x00006000U) /* !< GPIO Module Selection */
/* FACTORYREGION_SRAMFLASH Bits */
/* FACTORYREGION_SRAMFLASH[MAINFLASH_SZ] Bits */
#define FACTORYREGION_SRAMFLASH_MAINFLASH_SZ_OFS (0) /* !< MAINFLASH_SZ Offset */
#define FACTORYREGION_SRAMFLASH_MAINFLASH_SZ_MASK ((uint32_t)0x00000FFFU) /* !< The encoding of the field is that
the value of the field is an integer
to be interpreted as number of KBs.
For eg: if the value of the field id
4, then it is 4KB, if the value is
32, then 32KB, and so on. */
/* FACTORYREGION_SRAMFLASH[SRAM_SZ] Bits */
#define FACTORYREGION_SRAMFLASH_SRAM_SZ_OFS (16) /* !< SRAM_SZ Offset */
#define FACTORYREGION_SRAMFLASH_SRAM_SZ_MASK ((uint32_t)0x03FF0000U) /* !< The encoding of the field is that
the value of the field is an integer
to be interpreted as number of KBs.
For eg: if the value of the field id
4, then it is 4KB, if the value is
32, then 32KB, and so on. */
/* FACTORYREGION_SRAMFLASH[DATAFLASH_SZ] Bits */
#define FACTORYREGION_SRAMFLASH_DATAFLASH_SZ_OFS (26) /* !< DATAFLASH_SZ Offset */
#define FACTORYREGION_SRAMFLASH_DATAFLASH_SZ_MASK ((uint32_t)0xFC000000U) /* !< The encoding of the field is that
the value of the field is an integer
to be interpreted as number of KBs.
For eg: if the value of the field id
4, then it is 4KB, if the value is
32, then 32KB, and so on. */
/* FACTORYREGION_SRAMFLASH[MAINNUMBANKS] Bits */
#define FACTORYREGION_SRAMFLASH_MAINNUMBANKS_OFS (12) /* !< MAINNUMBANKS Offset */
#define FACTORYREGION_SRAMFLASH_MAINNUMBANKS_MASK ((uint32_t)0x00003000U)
#define FACTORYREGION_SRAMFLASH_MAINNUMBANKS_ONEBANK ((uint32_t)0x00000000U)
#define FACTORYREGION_SRAMFLASH_MAINNUMBANKS_TWOBANKS ((uint32_t)0x00001000U)
#define FACTORYREGION_SRAMFLASH_MAINNUMBANKS_THREEBANKS ((uint32_t)0x00002000U)
#define FACTORYREGION_SRAMFLASH_MAINNUMBANKS_FOURBANKS ((uint32_t)0x00003000U)
/* FACTORYREGION_PLLSTARTUP0_4_8MHZ Bits */
/* FACTORYREGION_PLLSTARTUP0_4_8MHZ[STARTTIME] Bits */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_STARTTIME_OFS (0) /* !< STARTTIME Offset */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_STARTTIME_MASK ((uint32_t)0x0000003FU) /* !< Startup time from Enable to Locked
Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_4_8MHZ[STARTTIMELP] Bits */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_STARTTIMELP_OFS (8) /* !< STARTTIMELP Offset */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_STARTTIMELP_MASK ((uint32_t)0x00003F00U) /* !< Startup time from Low Power Exit to
Locked Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_4_8MHZ[CPCURRENT] Bits */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CPCURRENT_OFS (16) /* !< CPCURRENT Offset */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CPCURRENT_MASK ((uint32_t)0x003F0000U) /* !< Charge Pump Current */
/* FACTORYREGION_PLLSTARTUP0_4_8MHZ[CAPBVAL] Bits */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CAPBVAL_OFS (24) /* !< CAPBVAL Offset */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CAPBVAL_MASK ((uint32_t)0x1F000000U) /* !< Override Value for Cap B */
/* FACTORYREGION_PLLSTARTUP0_4_8MHZ[CAPBOVERRIDE] Bits */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CAPBOVERRIDE_OFS (31) /* !< CAPBOVERRIDE Offset */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CAPBOVERRIDE_MASK ((uint32_t)0x80000000U) /* !< Override Enable For Cap B */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CAPBOVERRIDE_DISABLE ((uint32_t)0x00000000U)
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CAPBOVERRIDE_ENABLE ((uint32_t)0x80000000U)
/* FACTORYREGION_PLLSTARTUP1_4_8MHZ Bits */
/* FACTORYREGION_PLLSTARTUP1_4_8MHZ[LPFCAPA] Bits */
#define FACTORYREGION_PLLSTARTUP1_4_8MHZ_LPFCAPA_OFS (0) /* !< LPFCAPA Offset */
#define FACTORYREGION_PLLSTARTUP1_4_8MHZ_LPFCAPA_MASK ((uint32_t)0x0000001FU) /* !< Loop Filter Cap A */
/* FACTORYREGION_PLLSTARTUP1_4_8MHZ[LPFRESA] Bits */
#define FACTORYREGION_PLLSTARTUP1_4_8MHZ_LPFRESA_OFS (8) /* !< LPFRESA Offset */
#define FACTORYREGION_PLLSTARTUP1_4_8MHZ_LPFRESA_MASK ((uint32_t)0x0003FF00U) /* !< Loop Filter Res A */
/* FACTORYREGION_PLLSTARTUP1_4_8MHZ[LPFRESC] Bits */
#define FACTORYREGION_PLLSTARTUP1_4_8MHZ_LPFRESC_OFS (24) /* !< LPFRESC Offset */
#define FACTORYREGION_PLLSTARTUP1_4_8MHZ_LPFRESC_MASK ((uint32_t)0xFF000000U) /* !< Loop Filter Res C */
/* FACTORYREGION_PLLSTARTUP0_8_16MHZ Bits */
/* FACTORYREGION_PLLSTARTUP0_8_16MHZ[STARTTIME] Bits */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_STARTTIME_OFS (0) /* !< STARTTIME Offset */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_STARTTIME_MASK ((uint32_t)0x0000003FU) /* !< Startup time from Enable to Locked
Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_8_16MHZ[STARTTIMELP] Bits */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_STARTTIMELP_OFS (8) /* !< STARTTIMELP Offset */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_STARTTIMELP_MASK ((uint32_t)0x00003F00U) /* !< Startup time from Low Power Exit to
Locked Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_8_16MHZ[CPCURRENT] Bits */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CPCURRENT_OFS (16) /* !< CPCURRENT Offset */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CPCURRENT_MASK ((uint32_t)0x003F0000U) /* !< Charge Pump Current */
/* FACTORYREGION_PLLSTARTUP0_8_16MHZ[CAPBVAL] Bits */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CAPBVAL_OFS (24) /* !< CAPBVAL Offset */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CAPBVAL_MASK ((uint32_t)0x1F000000U) /* !< Override Value for Cap B */
/* FACTORYREGION_PLLSTARTUP0_8_16MHZ[CAPBOVERRIDE] Bits */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CAPBOVERRIDE_OFS (31) /* !< CAPBOVERRIDE Offset */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CAPBOVERRIDE_MASK ((uint32_t)0x80000000U) /* !< Override Enable For Cap B */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CAPBOVERRIDE_DISABLE ((uint32_t)0x00000000U)
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CAPBOVERRIDE_ENABLE ((uint32_t)0x80000000U)
/* FACTORYREGION_PLLSTARTUP1_8_16MHZ Bits */
/* FACTORYREGION_PLLSTARTUP1_8_16MHZ[LPFCAPA] Bits */
#define FACTORYREGION_PLLSTARTUP1_8_16MHZ_LPFCAPA_OFS (0) /* !< LPFCAPA Offset */
#define FACTORYREGION_PLLSTARTUP1_8_16MHZ_LPFCAPA_MASK ((uint32_t)0x0000001FU) /* !< Loop Filter Cap A */
/* FACTORYREGION_PLLSTARTUP1_8_16MHZ[LPFRESA] Bits */
#define FACTORYREGION_PLLSTARTUP1_8_16MHZ_LPFRESA_OFS (8) /* !< LPFRESA Offset */
#define FACTORYREGION_PLLSTARTUP1_8_16MHZ_LPFRESA_MASK ((uint32_t)0x0003FF00U) /* !< Loop Filter Res A */
/* FACTORYREGION_PLLSTARTUP1_8_16MHZ[LPFRESC] Bits */
#define FACTORYREGION_PLLSTARTUP1_8_16MHZ_LPFRESC_OFS (24) /* !< LPFRESC Offset */
#define FACTORYREGION_PLLSTARTUP1_8_16MHZ_LPFRESC_MASK ((uint32_t)0xFF000000U) /* !< Loop Filter Res C */
/* FACTORYREGION_PLLSTARTUP0_16_32MHZ Bits */
/* FACTORYREGION_PLLSTARTUP0_16_32MHZ[STARTTIME] Bits */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_STARTTIME_OFS (0) /* !< STARTTIME Offset */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_STARTTIME_MASK ((uint32_t)0x0000003FU) /* !< Startup time from Enable to Locked
Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_16_32MHZ[STARTTIMELP] Bits */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_STARTTIMELP_OFS (8) /* !< STARTTIMELP Offset */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_STARTTIMELP_MASK ((uint32_t)0x00003F00U) /* !< Startup time from Low Power Exit to
Locked Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_16_32MHZ[CPCURRENT] Bits */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CPCURRENT_OFS (16) /* !< CPCURRENT Offset */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CPCURRENT_MASK ((uint32_t)0x003F0000U) /* !< Charge Pump Current */
/* FACTORYREGION_PLLSTARTUP0_16_32MHZ[CAPBVAL] Bits */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CAPBVAL_OFS (24) /* !< CAPBVAL Offset */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CAPBVAL_MASK ((uint32_t)0x1F000000U) /* !< Override Value for Cap B */
/* FACTORYREGION_PLLSTARTUP0_16_32MHZ[CAPBOVERRIDE] Bits */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CAPBOVERRIDE_OFS (31) /* !< CAPBOVERRIDE Offset */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CAPBOVERRIDE_MASK ((uint32_t)0x80000000U) /* !< Override Enable For Cap B */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CAPBOVERRIDE_DISABLE ((uint32_t)0x00000000U)
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CAPBOVERRIDE_ENABLE ((uint32_t)0x80000000U)
/* FACTORYREGION_PLLSTARTUP1_16_32MHZ Bits */
/* FACTORYREGION_PLLSTARTUP1_16_32MHZ[LPFCAPA] Bits */
#define FACTORYREGION_PLLSTARTUP1_16_32MHZ_LPFCAPA_OFS (0) /* !< LPFCAPA Offset */
#define FACTORYREGION_PLLSTARTUP1_16_32MHZ_LPFCAPA_MASK ((uint32_t)0x0000001FU) /* !< Loop Filter Cap A */
/* FACTORYREGION_PLLSTARTUP1_16_32MHZ[LPFRESA] Bits */
#define FACTORYREGION_PLLSTARTUP1_16_32MHZ_LPFRESA_OFS (8) /* !< LPFRESA Offset */
#define FACTORYREGION_PLLSTARTUP1_16_32MHZ_LPFRESA_MASK ((uint32_t)0x0003FF00U) /* !< Loop Filter Res A */
/* FACTORYREGION_PLLSTARTUP1_16_32MHZ[LPFRESC] Bits */
#define FACTORYREGION_PLLSTARTUP1_16_32MHZ_LPFRESC_OFS (24) /* !< LPFRESC Offset */
#define FACTORYREGION_PLLSTARTUP1_16_32MHZ_LPFRESC_MASK ((uint32_t)0xFF000000U) /* !< Loop Filter Res C */
/* FACTORYREGION_PLLSTARTUP0_32_48MHZ Bits */
/* FACTORYREGION_PLLSTARTUP0_32_48MHZ[STARTTIME] Bits */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_STARTTIME_OFS (0) /* !< STARTTIME Offset */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_STARTTIME_MASK ((uint32_t)0x0000003FU) /* !< Startup time from Enable to Locked
Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_32_48MHZ[STARTTIMELP] Bits */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_STARTTIMELP_OFS (8) /* !< STARTTIMELP Offset */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_STARTTIMELP_MASK ((uint32_t)0x00003F00U) /* !< Startup time from Low Power Exit to
Locked Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_32_48MHZ[CPCURRENT] Bits */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CPCURRENT_OFS (16) /* !< CPCURRENT Offset */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CPCURRENT_MASK ((uint32_t)0x003F0000U) /* !< Charge Pump Current */
/* FACTORYREGION_PLLSTARTUP0_32_48MHZ[CAPBVAL] Bits */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CAPBVAL_OFS (24) /* !< CAPBVAL Offset */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CAPBVAL_MASK ((uint32_t)0x1F000000U) /* !< Override Value for Cap B */
/* FACTORYREGION_PLLSTARTUP0_32_48MHZ[CAPBOVERRIDE] Bits */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CAPBOVERRIDE_OFS (31) /* !< CAPBOVERRIDE Offset */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CAPBOVERRIDE_MASK ((uint32_t)0x80000000U) /* !< Override Enable For Cap B */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CAPBOVERRIDE_DISABLE ((uint32_t)0x00000000U)
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CAPBOVERRIDE_ENABLE ((uint32_t)0x80000000U)
/* FACTORYREGION_PLLSTARTUP1_32_48MHZ Bits */
/* FACTORYREGION_PLLSTARTUP1_32_48MHZ[LPFCAPA] Bits */
#define FACTORYREGION_PLLSTARTUP1_32_48MHZ_LPFCAPA_OFS (0) /* !< LPFCAPA Offset */
#define FACTORYREGION_PLLSTARTUP1_32_48MHZ_LPFCAPA_MASK ((uint32_t)0x0000001FU) /* !< Loop Filter Cap A */
/* FACTORYREGION_PLLSTARTUP1_32_48MHZ[LPFRESA] Bits */
#define FACTORYREGION_PLLSTARTUP1_32_48MHZ_LPFRESA_OFS (8) /* !< LPFRESA Offset */
#define FACTORYREGION_PLLSTARTUP1_32_48MHZ_LPFRESA_MASK ((uint32_t)0x0003FF00U) /* !< Loop Filter Res A */
/* FACTORYREGION_PLLSTARTUP1_32_48MHZ[LPFRESC] Bits */
#define FACTORYREGION_PLLSTARTUP1_32_48MHZ_LPFRESC_OFS (24) /* !< LPFRESC Offset */
#define FACTORYREGION_PLLSTARTUP1_32_48MHZ_LPFRESC_MASK ((uint32_t)0xFF000000U) /* !< Loop Filter Res C */
/* FACTORYREGION_TEMP_SENSE0 Bits */
/* FACTORYREGION_TEMP_SENSE0[DATA] Bits */
#define FACTORYREGION_TEMP_SENSE0_DATA_OFS (0) /* !< DATA Offset */
#define FACTORYREGION_TEMP_SENSE0_DATA_MASK ((uint32_t)0xFFFFFFFFU)
/* FACTORYREGION_BOOTCRC Bits */
/* FACTORYREGION_BOOTCRC[DATA] Bits */
#define FACTORYREGION_BOOTCRC_DATA_OFS (0) /* !< DATA Offset */
#define FACTORYREGION_BOOTCRC_DATA_MASK ((uint32_t)0xFFFFFFFFU)
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_hw_factoryregion__include */
libraries/sdk/ti/devices/msp/peripherals/m0p/hw_sysctl.h
+70
View File
@@ -0,0 +1,70 @@
/*****************************************************************************
Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
/* This file automatically includes the specific device sysctl header file
without the need to include a specific device sysctl header.
The device #define is set automatically through the toolchain on basis
of the device chosen in the device selection menu (.e.g -D__MICRO1__). */
#ifndef ti_devices_msp_peripheral_m0p_sysctl__include
#define ti_devices_msp_peripheral_m0p_sysctl__include
/******************************************************************************
* MSP devices
******************************************************************************/
#include <ti/devices/DeviceFamily.h>
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G1X0X_G3X0X)
#include <ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0g1x0x_g3x0x.h>
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L11XX_L13XX)
#include <ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0l11xx_l13xx.h>
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0C110X) || (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPS003FX)
#include <ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0c110x.h>
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L122X_L222X)
#include <ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0l122x_l222x.h>
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0GX51X)
#include <ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0gx51x.h>
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L111X)
#include <ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0l111x.h>
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0H321X)
#include <ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0h321x.h>
/********************************************************************
*
********************************************************************/
#else
#error "Failed to match a default include file"
#endif
#endif /* ti_devices_msp_peripheral_m0p_sysctl__include */
libraries/sdk/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0c110x.h
+991
View File
@@ -0,0 +1,991 @@
/*****************************************************************************
Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0c110x__include
#define ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0c110x__include
/* Filename: hw_sysctl_mspm0c110x.h */
/* Revised: 2024-11-18 03:51:42 */
/* Revision: 71ad117d0ac260e84eba242c6eff6a9062e15e6c */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* SYSCTL Registers
******************************************************************************/
#define SYSCTL_SOCLOCK_OFS ((uint32_t)0x00001000U)
/** @addtogroup SYSCTL_SOCLOCK
@{
*/
typedef struct {
uint32_t RESERVED0[8];
__I uint32_t IIDX; /* !< (@ 0x00001020) SYSCTL interrupt index */
uint32_t RESERVED1;
__IO uint32_t IMASK; /* !< (@ 0x00001028) SYSCTL interrupt mask */
uint32_t RESERVED2;
__I uint32_t RIS; /* !< (@ 0x00001030) SYSCTL raw interrupt status */
uint32_t RESERVED3;
__I uint32_t MIS; /* !< (@ 0x00001038) SYSCTL masked interrupt status */
uint32_t RESERVED4;
__O uint32_t ISET; /* !< (@ 0x00001040) SYSCTL interrupt set */
uint32_t RESERVED5;
__O uint32_t ICLR; /* !< (@ 0x00001048) SYSCTL interrupt clear */
uint32_t RESERVED6;
__I uint32_t NMIIIDX; /* !< (@ 0x00001050) NMI interrupt index */
uint32_t RESERVED7[3];
__I uint32_t NMIRIS; /* !< (@ 0x00001060) NMI raw interrupt status */
uint32_t RESERVED8[3];
__O uint32_t NMIISET; /* !< (@ 0x00001070) NMI interrupt set */
uint32_t RESERVED9;
__O uint32_t NMIICLR; /* !< (@ 0x00001078) NMI interrupt clear */
uint32_t RESERVED10[33];
__IO uint32_t SYSOSCCFG; /* !< (@ 0x00001100) SYSOSC configuration */
__IO uint32_t MCLKCFG; /* !< (@ 0x00001104) Main clock (MCLK) configuration */
__IO uint32_t HSCLKEN; /* !< (@ 0x00001108) High-speed clock (HSCLK) source enable/disable */
uint32_t RESERVED11[11];
__IO uint32_t GENCLKCFG; /* !< (@ 0x00001138) General clock configuration */
__IO uint32_t GENCLKEN; /* !< (@ 0x0000113C) General clock enable control */
__IO uint32_t PMODECFG; /* !< (@ 0x00001140) Power mode configuration */
uint32_t RESERVED12[3];
__I uint32_t FCC; /* !< (@ 0x00001150) Frequency clock counter (FCC) count */
uint32_t RESERVED13[9];
__IO uint32_t SRAMBOUNDARY; /* !< (@ 0x00001178) SRAM Write Boundary */
uint32_t RESERVED14;
__IO uint32_t SYSTEMCFG; /* !< (@ 0x00001180) System configuration */
uint32_t RESERVED15[3];
__IO uint32_t BEEPCFG; /* !< (@ 0x00001190) BEEPER Configuration */
uint32_t RESERVED16[27];
__IO uint32_t WRITELOCK; /* !< (@ 0x00001200) SYSCTL register write lockout */
__I uint32_t CLKSTATUS; /* !< (@ 0x00001204) Clock module (CKM) status */
__I uint32_t SYSSTATUS; /* !< (@ 0x00001208) System status information */
uint32_t RESERVED17[5];
__I uint32_t RSTCAUSE; /* !< (@ 0x00001220) Reset cause */
uint32_t RESERVED18[55];
__IO uint32_t RESETLEVEL; /* !< (@ 0x00001300) Reset level for application-triggered reset
command */
__O uint32_t RESETCMD; /* !< (@ 0x00001304) Execute an application-triggered reset command */
__IO uint32_t BORTHRESHOLD; /* !< (@ 0x00001308) BOR threshold selection */
__O uint32_t BORCLRCMD; /* !< (@ 0x0000130C) Set the BOR threshold */
__O uint32_t SYSOSCFCLCTL; /* !< (@ 0x00001310) SYSOSC frequency correction loop (FCL) ROSC enable */
uint32_t RESERVED19;
__O uint32_t EXLFCTL; /* !< (@ 0x00001318) LFCLK_IN and LFCLK control */
__O uint32_t SHDNIOREL; /* !< (@ 0x0000131C) SHUTDOWN IO release control */
__O uint32_t EXRSTPIN; /* !< (@ 0x00001320) Disable the reset function of the NRST pin */
__O uint32_t SYSSTATUSCLR; /* !< (@ 0x00001324) Clear sticky bits of SYSSTATUS */
__O uint32_t SWDCFG; /* !< (@ 0x00001328) Disable the SWD function on the SWD pins */
__O uint32_t FCCCMD; /* !< (@ 0x0000132C) Frequency clock counter start capture */
uint32_t RESERVED20[52];
__IO uint32_t SHUTDNSTORE0; /* !< (@ 0x00001400) Shutdown storage memory (byte 0) */
__IO uint32_t SHUTDNSTORE1; /* !< (@ 0x00001404) Shutdown storage memory (byte 1) */
__IO uint32_t SHUTDNSTORE2; /* !< (@ 0x00001408) Shutdown storage memory (byte 2) */
__IO uint32_t SHUTDNSTORE3; /* !< (@ 0x0000140C) Shutdown storage memory (byte 3) */
} SYSCTL_SOCLOCK_Regs;
/*@}*/ /* end of group SYSCTL_SOCLOCK */
/** @addtogroup SYSCTL
@{
*/
typedef struct {
uint32_t RESERVED0[1024];
SYSCTL_SOCLOCK_Regs SOCLOCK; /* !< (@ 0x00001000) SYSCTL SOCLOCK Region */
} SYSCTL_Regs;
/*@}*/ /* end of group SYSCTL */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* SYSCTL Register Control Bits
******************************************************************************/
/* SYSCTL_IIDX Bits */
/* SYSCTL_IIDX[STAT] Bits */
#define SYSCTL_IIDX_STAT_OFS (0) /* !< STAT Offset */
#define SYSCTL_IIDX_STAT_MASK ((uint32_t)0x00000003U) /* !< The SYSCTL interrupt index (IIDX)
register generates a value
corresponding to the highest priority
pending interrupt source. This value
may be used as an address offset for
fast, deterministic handling in the
interrupt service routine. A read of
the IIDX register will clear the
corresponding interrupt status in the
RIS and MIS registers. */
#define SYSCTL_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define SYSCTL_IIDX_STAT_LFOSCGOOD ((uint32_t)0x00000001U) /* !< LFOSCGOOD interrupt pending */
#define SYSCTL_IIDX_STAT_ANACLKERR ((uint32_t)0x00000002U)
/* SYSCTL_IMASK Bits */
/* SYSCTL_IMASK[LFOSCGOOD] Bits */
#define SYSCTL_IMASK_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */
#define SYSCTL_IMASK_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Enable or disable the LFOSCGOOD
interrupt. LFOSCGOOD indicates that
the LFOSC has started successfully. */
#define SYSCTL_IMASK_LFOSCGOOD_DISABLE ((uint32_t)0x00000000U) /* !< Interrupt disabled */
#define SYSCTL_IMASK_LFOSCGOOD_ENABLE ((uint32_t)0x00000001U) /* !< Interrupt enabled */
/* SYSCTL_IMASK[ANACLKERR] Bits */
#define SYSCTL_IMASK_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */
#define SYSCTL_IMASK_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */
#define SYSCTL_IMASK_ANACLKERR_DISABLE ((uint32_t)0x00000000U)
#define SYSCTL_IMASK_ANACLKERR_ENABLE ((uint32_t)0x00000002U)
/* SYSCTL_RIS Bits */
/* SYSCTL_RIS[LFOSCGOOD] Bits */
#define SYSCTL_RIS_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */
#define SYSCTL_RIS_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Raw status of the LFOSCGOOD
interrupt. */
#define SYSCTL_RIS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define SYSCTL_RIS_LFOSCGOOD_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */
/* SYSCTL_RIS[ANACLKERR] Bits */
#define SYSCTL_RIS_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */
#define SYSCTL_RIS_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */
#define SYSCTL_RIS_ANACLKERR_FALSE ((uint32_t)0x00000000U)
#define SYSCTL_RIS_ANACLKERR_TRUE ((uint32_t)0x00000002U)
/* SYSCTL_MIS Bits */
/* SYSCTL_MIS[LFOSCGOOD] Bits */
#define SYSCTL_MIS_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */
#define SYSCTL_MIS_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Masked status of the LFOSCGOOD
interrupt. */
#define SYSCTL_MIS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define SYSCTL_MIS_LFOSCGOOD_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */
/* SYSCTL_MIS[ANACLKERR] Bits */
#define SYSCTL_MIS_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */
#define SYSCTL_MIS_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */
#define SYSCTL_MIS_ANACLKERR_FALSE ((uint32_t)0x00000000U)
#define SYSCTL_MIS_ANACLKERR_TRUE ((uint32_t)0x00000002U)
/* SYSCTL_ISET Bits */
/* SYSCTL_ISET[LFOSCGOOD] Bits */
#define SYSCTL_ISET_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */
#define SYSCTL_ISET_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Set the LFOSCGOOD interrupt. */
#define SYSCTL_ISET_LFOSCGOOD_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */
#define SYSCTL_ISET_LFOSCGOOD_SET ((uint32_t)0x00000001U) /* !< Set interrupt */
/* SYSCTL_ISET[ANACLKERR] Bits */
#define SYSCTL_ISET_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */
#define SYSCTL_ISET_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */
#define SYSCTL_ISET_ANACLKERR_NO_EFFECT ((uint32_t)0x00000000U)
#define SYSCTL_ISET_ANACLKERR_SET ((uint32_t)0x00000002U)
/* SYSCTL_ICLR Bits */
/* SYSCTL_ICLR[LFOSCGOOD] Bits */
#define SYSCTL_ICLR_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */
#define SYSCTL_ICLR_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Clear the LFOSCGOOD interrupt. */
#define SYSCTL_ICLR_LFOSCGOOD_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h has no effect */
#define SYSCTL_ICLR_LFOSCGOOD_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */
/* SYSCTL_ICLR[ANACLKERR] Bits */
#define SYSCTL_ICLR_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */
#define SYSCTL_ICLR_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */
#define SYSCTL_ICLR_ANACLKERR_NO_EFFECT ((uint32_t)0x00000000U)
#define SYSCTL_ICLR_ANACLKERR_CLR ((uint32_t)0x00000002U)
/* SYSCTL_NMIIIDX Bits */
/* SYSCTL_NMIIIDX[STAT] Bits */
#define SYSCTL_NMIIIDX_STAT_OFS (0) /* !< STAT Offset */
#define SYSCTL_NMIIIDX_STAT_MASK ((uint32_t)0x00000003U) /* !< The NMI interrupt index (NMIIIDX)
register generates a value
corresponding to the highest priority
pending NMI source. This value may
be used as an address offset for
fast, deterministic handling in the
NMI service routine. A read of the
NMIIIDX register will clear the
corresponding interrupt status in the
NMIRIS register. */
#define SYSCTL_NMIIIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No NMI pending */
#define SYSCTL_NMIIIDX_STAT_BORLVL ((uint32_t)0x00000001U) /* !< BOR Threshold NMI pending */
#define SYSCTL_NMIIIDX_STAT_WWDT0 ((uint32_t)0x00000002U)
/* SYSCTL_NMIRIS Bits */
/* SYSCTL_NMIRIS[BORLVL] Bits */
#define SYSCTL_NMIRIS_BORLVL_OFS (0) /* !< BORLVL Offset */
#define SYSCTL_NMIRIS_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Raw status of the BORLVL NMI */
#define SYSCTL_NMIRIS_BORLVL_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define SYSCTL_NMIRIS_BORLVL_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */
/* SYSCTL_NMIRIS[WWDT0] Bits */
#define SYSCTL_NMIRIS_WWDT0_OFS (1) /* !< WWDT0 Offset */
#define SYSCTL_NMIRIS_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */
#define SYSCTL_NMIRIS_WWDT0_FALSE ((uint32_t)0x00000000U)
#define SYSCTL_NMIRIS_WWDT0_TRUE ((uint32_t)0x00000002U)
/* SYSCTL_NMIISET Bits */
/* SYSCTL_NMIISET[BORLVL] Bits */
#define SYSCTL_NMIISET_BORLVL_OFS (0) /* !< BORLVL Offset */
#define SYSCTL_NMIISET_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Set the BORLVL NMI */
#define SYSCTL_NMIISET_BORLVL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */
#define SYSCTL_NMIISET_BORLVL_SET ((uint32_t)0x00000001U) /* !< Set interrupt */
/* SYSCTL_NMIISET[WWDT0] Bits */
#define SYSCTL_NMIISET_WWDT0_OFS (1) /* !< WWDT0 Offset */
#define SYSCTL_NMIISET_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */
#define SYSCTL_NMIISET_WWDT0_NO_EFFECT ((uint32_t)0x00000000U)
#define SYSCTL_NMIISET_WWDT0_SET ((uint32_t)0x00000002U)
/* SYSCTL_NMIICLR Bits */
/* SYSCTL_NMIICLR[BORLVL] Bits */
#define SYSCTL_NMIICLR_BORLVL_OFS (0) /* !< BORLVL Offset */
#define SYSCTL_NMIICLR_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Clr the BORLVL NMI */
#define SYSCTL_NMIICLR_BORLVL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */
#define SYSCTL_NMIICLR_BORLVL_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */
/* SYSCTL_NMIICLR[WWDT0] Bits */
#define SYSCTL_NMIICLR_WWDT0_OFS (1) /* !< WWDT0 Offset */
#define SYSCTL_NMIICLR_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */
#define SYSCTL_NMIICLR_WWDT0_NO_EFFECT ((uint32_t)0x00000000U)
#define SYSCTL_NMIICLR_WWDT0_CLR ((uint32_t)0x00000002U)
/* SYSCTL_SYSOSCCFG Bits */
/* SYSCTL_SYSOSCCFG[DISABLESTOP] Bits */
#define SYSCTL_SYSOSCCFG_DISABLESTOP_OFS (9) /* !< DISABLESTOP Offset */
#define SYSCTL_SYSOSCCFG_DISABLESTOP_MASK ((uint32_t)0x00000200U) /* !< DISABLESTOP sets the SYSOSC stop
mode enable/disable policy. When
operating in STOP mode, the SYSOSC
may be automatically disabled. When
set, ULPCLK will run from LFCLK in
STOP mode and SYSOSC will be disabled
to reduce power consumption. */
#define SYSCTL_SYSOSCCFG_DISABLESTOP_DISABLE ((uint32_t)0x00000000U) /* !< Do not disable SYSOSC in STOP mode */
#define SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE ((uint32_t)0x00000200U) /* !< Disable SYSOSC in STOP mode and
source ULPCLK from LFCLK */
/* SYSCTL_SYSOSCCFG[BLOCKASYNCALL] Bits */
#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_OFS (16) /* !< BLOCKASYNCALL Offset */
#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_MASK ((uint32_t)0x00010000U) /* !< BLOCKASYNCALL may be used to mask
block all asynchronous fast clock
requests, preventing hardware from
dynamically changing the active clock
configuration when operating in a
given mode. */
#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_DISABLE ((uint32_t)0x00000000U) /* !< Asynchronous fast clock requests
are controlled by the requesting
peripheral */
#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE ((uint32_t)0x00010000U) /* !< All asynchronous fast clock
requests are blocked */
/* SYSCTL_SYSOSCCFG[DISABLE] Bits */
#define SYSCTL_SYSOSCCFG_DISABLE_OFS (10) /* !< DISABLE Offset */
#define SYSCTL_SYSOSCCFG_DISABLE_MASK ((uint32_t)0x00000400U) /* !< DISABLE sets the SYSOSC
enable/disable policy. SYSOSC may be
powered off in RUN, SLEEP, and STOP
modes to reduce power consumption.
When SYSOSC is disabled, MCLK and
ULPCLK are sourced from LFCLK. */
#define SYSCTL_SYSOSCCFG_DISABLE_DISABLE ((uint32_t)0x00000000U) /* !< Do not disable SYSOSC */
#define SYSCTL_SYSOSCCFG_DISABLE_ENABLE ((uint32_t)0x00000400U) /* !< Disable SYSOSC immediately and
source MCLK and ULPCLK from LFCLK */
/* SYSCTL_SYSOSCCFG[FASTCPUEVENT] Bits */
#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_OFS (17) /* !< FASTCPUEVENT Offset */
#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_MASK ((uint32_t)0x00020000U) /* !< FASTCPUEVENT may be used to assert
a fast clock request when an
interrupt is asserted to the CPU,
reducing interrupt latency. */
#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_DISABLE ((uint32_t)0x00000000U) /* !< An interrupt to the CPU will not
assert a fast clock request */
#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE ((uint32_t)0x00020000U) /* !< An interrupt to the CPU will assert
a fast clock request */
/* SYSCTL_SYSOSCCFG[FREQ] Bits */
#define SYSCTL_SYSOSCCFG_FREQ_OFS (0) /* !< FREQ Offset */
#define SYSCTL_SYSOSCCFG_FREQ_MASK ((uint32_t)0x00000003U) /* !< Target operating frequency for the
system oscillator (SYSOSC) */
#define SYSCTL_SYSOSCCFG_FREQ_SYSOSCBASE ((uint32_t)0x00000000U) /* !< Base frequency (32MHz) */
#define SYSCTL_SYSOSCCFG_FREQ_SYSOSC4M ((uint32_t)0x00000001U) /* !< Low frequency (4MHz) */
#define SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER ((uint32_t)0x00000002U) /* !< User-trimmed frequency (16 or 24
MHz) */
/* SYSCTL_MCLKCFG Bits */
/* SYSCTL_MCLKCFG[USEMFTICK] Bits */
#define SYSCTL_MCLKCFG_USEMFTICK_OFS (12) /* !< USEMFTICK Offset */
#define SYSCTL_MCLKCFG_USEMFTICK_MASK ((uint32_t)0x00001000U) /* !< USEMFTICK specifies whether the
4MHz constant-rate clock (MFCLK) to
peripherals is enabled or disabled.
When enabled, MDIV must be disabled
(set to 0h=/1). */
#define SYSCTL_MCLKCFG_USEMFTICK_DISABLE ((uint32_t)0x00000000U) /* !< The 4MHz rate MFCLK to peripherals
is enabled */
#define SYSCTL_MCLKCFG_USEMFTICK_ENABLE ((uint32_t)0x00001000U) /* !< The 4MHz rate MFCLK to peripherals
is enabled. */
/* SYSCTL_MCLKCFG[MDIV] Bits */
#define SYSCTL_MCLKCFG_MDIV_OFS (0) /* !< MDIV Offset */
#define SYSCTL_MCLKCFG_MDIV_MASK ((uint32_t)0x0000000FU) /* !< MDIV may be used to divide the MCLK
frequency when MCLK is sourced from
SYSOSC. MDIV=0h corresponds to /1
(no divider). MDIV=1h corresponds to
/2 (divide-by-2). MDIV=Fh
corresponds to /16 (divide-by-16).
MDIV may be set between /1 and /16 on
an integer basis. */
/* SYSCTL_MCLKCFG[USEHSCLK] Bits */
#define SYSCTL_MCLKCFG_USEHSCLK_OFS (16) /* !< USEHSCLK Offset */
#define SYSCTL_MCLKCFG_USEHSCLK_MASK ((uint32_t)0x00010000U) /* !< USEHSCLK, together with USELFCLK,
sets the MCLK source policy. Set
USEHSCLK to use HSCLK (HFCLK or
SYSPLL) as the MCLK source in RUN and
SLEEP modes. */
#define SYSCTL_MCLKCFG_USEHSCLK_DISABLE ((uint32_t)0x00000000U) /* !< MCLK will not use the high speed
clock (HSCLK) */
#define SYSCTL_MCLKCFG_USEHSCLK_ENABLE ((uint32_t)0x00010000U) /* !< MCLK will use the high speed clock
(HSCLK) in RUN and SLEEP mode */
/* SYSCTL_MCLKCFG[USELFCLK] Bits */
#define SYSCTL_MCLKCFG_USELFCLK_OFS (20) /* !< USELFCLK Offset */
#define SYSCTL_MCLKCFG_USELFCLK_MASK ((uint32_t)0x00100000U) /* !< USELFCLK sets the MCLK source
policy. Set USELFCLK to use LFCLK as
the MCLK source. Note that setting
USELFCLK does not disable SYSOSC, and
SYSOSC remains available for direct
use by analog modules. */
#define SYSCTL_MCLKCFG_USELFCLK_DISABLE ((uint32_t)0x00000000U) /* !< MCLK will not use the low frequency
clock (LFCLK) */
#define SYSCTL_MCLKCFG_USELFCLK_ENABLE ((uint32_t)0x00100000U) /* !< MCLK will use the low frequency
clock (LFCLK) */
/* SYSCTL_MCLKCFG[STOPCLKSTBY] Bits */
#define SYSCTL_MCLKCFG_STOPCLKSTBY_OFS (21) /* !< STOPCLKSTBY Offset */
#define SYSCTL_MCLKCFG_STOPCLKSTBY_MASK ((uint32_t)0x00200000U) /* !< STOPCLKSTBY sets the STANDBY mode
policy (STANDBY0 or STANDBY1). When
set, ULPCLK and LFCLK are disabled to
all peripherals in STANDBY mode, with
the exception of TIMG0 and TIMG1
which continue to run. Wake-up is
only possible via an asynchronous
fast clock request. */
#define SYSCTL_MCLKCFG_STOPCLKSTBY_DISABLE ((uint32_t)0x00000000U) /* !< ULPCLK/LFCLK runs to all PD0
peripherals in STANDBY mode */
#define SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE ((uint32_t)0x00200000U) /* !< ULPCLK/LFCLK is disabled to all
peripherals in STANDBY mode except
TIMG0 and TIMG1 */
/* SYSCTL_MCLKCFG[MCLKDEADCHK] Bits */
#define SYSCTL_MCLKCFG_MCLKDEADCHK_OFS (22) /* !< MCLKDEADCHK Offset */
#define SYSCTL_MCLKCFG_MCLKDEADCHK_MASK ((uint32_t)0x00400000U) /* !< MCLKDEADCHK enables or disables the
continuous MCLK dead check monitor.
LFCLK must be running before
MCLKDEADCHK is enabled. */
#define SYSCTL_MCLKCFG_MCLKDEADCHK_DISABLE ((uint32_t)0x00000000U) /* !< The MCLK dead check monitor is
disabled */
#define SYSCTL_MCLKCFG_MCLKDEADCHK_ENABLE ((uint32_t)0x00400000U) /* !< The MCLK dead check monitor is
enabled */
/* SYSCTL_HSCLKEN Bits */
/* SYSCTL_HSCLKEN[USEEXTHFCLK] Bits */
#define SYSCTL_HSCLKEN_USEEXTHFCLK_OFS (16) /* !< USEEXTHFCLK Offset */
#define SYSCTL_HSCLKEN_USEEXTHFCLK_MASK ((uint32_t)0x00010000U) /* !< USEEXTHFCLK selects the HFCLK_IN
digital clock input to be the source
for HFCLK. When disabled, HFXT is
the HFCLK source and HFXTEN may be
set. Do not set HFXTEN and
USEEXTHFCLK simultaneously. */
#define SYSCTL_HSCLKEN_USEEXTHFCLK_DISABLE ((uint32_t)0x00000000U) /* !< Use HFXT as the HFCLK source */
#define SYSCTL_HSCLKEN_USEEXTHFCLK_ENABLE ((uint32_t)0x00010000U) /* !< Use the HFCLK_IN digital clock
input as the HFCLK source */
/* SYSCTL_GENCLKCFG Bits */
/* SYSCTL_GENCLKCFG[HFCLK4MFPCLKDIV] Bits */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS (12) /* !< HFCLK4MFPCLKDIV Offset */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK ((uint32_t)0x0000F000U) /* !< HFCLK4MFPCLKDIV selects the divider
applied to HFCLK when HFCLK is used
as the MFPCLK source. Integer
dividers from /1 to /16 may be
selected. */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV1 ((uint32_t)0x00000000U) /* !< HFCLK is not divided before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV2 ((uint32_t)0x00001000U) /* !< HFCLK is divided by 2 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV3 ((uint32_t)0x00002000U) /* !< HFCLK is divided by 3 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV4 ((uint32_t)0x00003000U) /* !< HFCLK is divided by 4 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV5 ((uint32_t)0x00004000U) /* !< HFCLK is divided by 5 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV6 ((uint32_t)0x00005000U) /* !< HFCLK is divided by 6 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV7 ((uint32_t)0x00006000U) /* !< HFCLK is divided by 7 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV8 ((uint32_t)0x00007000U) /* !< HFCLK is divided by 8 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV9 ((uint32_t)0x00008000U) /* !< HFCLK is divided by 9 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV10 ((uint32_t)0x00009000U) /* !< HFCLK is divided by 10 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV11 ((uint32_t)0x0000A000U) /* !< HFCLK is divided by 11 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV12 ((uint32_t)0x0000B000U) /* !< HFCLK is divided by 12 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV13 ((uint32_t)0x0000C000U) /* !< HFCLK is divided by 13 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV14 ((uint32_t)0x0000D000U) /* !< HFCLK is divided by 14 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV15 ((uint32_t)0x0000E000U) /* !< HFCLK is divided by 15 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV16 ((uint32_t)0x0000F000U) /* !< HFCLK is divided by 16 before being
used for MFPCLK */
/* SYSCTL_GENCLKCFG[MFPCLKSRC] Bits */
#define SYSCTL_GENCLKCFG_MFPCLKSRC_OFS (9) /* !< MFPCLKSRC Offset */
#define SYSCTL_GENCLKCFG_MFPCLKSRC_MASK ((uint32_t)0x00000200U) /* !< MFPCLKSRC selects the MFPCLK
(middle frequency precision clock)
source. */
#define SYSCTL_GENCLKCFG_MFPCLKSRC_SYSOSC ((uint32_t)0x00000000U) /* !< MFPCLK is sourced from SYSOSC */
#define SYSCTL_GENCLKCFG_MFPCLKSRC_HFCLK ((uint32_t)0x00000200U) /* !< MFPCLK is sourced from HFCLK */
/* SYSCTL_GENCLKCFG[FCCTRIGCNT] Bits */
#define SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS (24) /* !< FCCTRIGCNT Offset */
#define SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK ((uint32_t)0x1F000000U) /* !< FCCTRIGCNT specifies the number of
trigger clock periods in the trigger
window. FCCTRIGCNT=0h (one trigger
clock period) up to 1Fh (32 trigger
clock periods) may be specified. */
/* SYSCTL_GENCLKCFG[ANACPUMPCFG] Bits */
#define SYSCTL_GENCLKCFG_ANACPUMPCFG_OFS (22) /* !< ANACPUMPCFG Offset */
#define SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK ((uint32_t)0x00C00000U) /* !< ANACPUMPCFG selects the analog mux
charge pump (VBOOST) enable method. */
#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONDEMAND ((uint32_t)0x00000000U) /* !< VBOOST is enabled on request from a
COMP, GPAMP, or OPA */
#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONACTIVE ((uint32_t)0x00400000U) /* !< VBOOST is enabled when the device
is in RUN or SLEEP mode, or when a
COMP/GPAMP/OPA is enabled */
#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONALWAYS ((uint32_t)0x00800000U) /* !< VBOOST is always enabled */
/* SYSCTL_GENCLKCFG[FCCSELCLK] Bits */
#define SYSCTL_GENCLKCFG_FCCSELCLK_OFS (16) /* !< FCCSELCLK Offset */
#define SYSCTL_GENCLKCFG_FCCSELCLK_MASK ((uint32_t)0x000F0000U) /* !< FCCSELCLK selectes the frequency
clock counter (FCC) clock source. */
#define SYSCTL_GENCLKCFG_FCCSELCLK_MCLK ((uint32_t)0x00000000U) /* !< FCC clock is MCLK */
#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSOSC ((uint32_t)0x00010000U) /* !< FCC clock is SYSOSC */
#define SYSCTL_GENCLKCFG_FCCSELCLK_HFCLK ((uint32_t)0x00020000U) /* !< FCC clock is HFCLK */
#define SYSCTL_GENCLKCFG_FCCSELCLK_EXTCLK ((uint32_t)0x00030000U) /* !< FCC clock is the CLK_OUT selection */
#define SYSCTL_GENCLKCFG_FCCSELCLK_FCCIN ((uint32_t)0x00070000U) /* !< FCC clock is the FCCIN external
input */
/* SYSCTL_GENCLKCFG[FCCTRIGSRC] Bits */
#define SYSCTL_GENCLKCFG_FCCTRIGSRC_OFS (20) /* !< FCCTRIGSRC Offset */
#define SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK ((uint32_t)0x00100000U) /* !< FCCTRIGSRC selects the frequency
clock counter (FCC) trigger source. */
#define SYSCTL_GENCLKCFG_FCCTRIGSRC_EXTPIN ((uint32_t)0x00000000U) /* !< FCC trigger is the external pin */
#define SYSCTL_GENCLKCFG_FCCTRIGSRC_LFCLK ((uint32_t)0x00100000U) /* !< FCC trigger is the LFCLK */
/* SYSCTL_GENCLKCFG[FCCLVLTRIG] Bits */
#define SYSCTL_GENCLKCFG_FCCLVLTRIG_OFS (21) /* !< FCCLVLTRIG Offset */
#define SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK ((uint32_t)0x00200000U) /* !< FCCLVLTRIG selects the frequency
clock counter (FCC) trigger mode. */
#define SYSCTL_GENCLKCFG_FCCLVLTRIG_RISE2RISE ((uint32_t)0x00000000U) /* !< Rising edge to rising edge
triggered */
#define SYSCTL_GENCLKCFG_FCCLVLTRIG_LEVEL ((uint32_t)0x00200000U) /* !< Level triggered */
/* SYSCTL_GENCLKCFG[EXCLKSRC] Bits */
#define SYSCTL_GENCLKCFG_EXCLKSRC_OFS (0) /* !< EXCLKSRC Offset */
#define SYSCTL_GENCLKCFG_EXCLKSRC_MASK ((uint32_t)0x00000007U) /* !< EXCLKSRC selects the source for the
CLK_OUT external clock output block.
ULPCLK and MFPCLK require the CLK_OUT
divider (EXCLKDIVEN) to be enabled */
#define SYSCTL_GENCLKCFG_EXCLKSRC_SYSOSC ((uint32_t)0x00000000U) /* !< CLK_OUT is SYSOSC */
#define SYSCTL_GENCLKCFG_EXCLKSRC_ULPCLK ((uint32_t)0x00000001U) /* !< CLK_OUT is ULPCLK (EXCLKDIVEN must
be enabled) */
#define SYSCTL_GENCLKCFG_EXCLKSRC_LFCLK ((uint32_t)0x00000002U) /* !< CLK_OUT is LFCLK */
#define SYSCTL_GENCLKCFG_EXCLKSRC_MFPCLK ((uint32_t)0x00000003U) /* !< CLK_OUT is MFPCLK (EXCLKDIVEN must
be enabled) */
#define SYSCTL_GENCLKCFG_EXCLKSRC_HFCLK ((uint32_t)0x00000004U) /* !< CLK_OUT is HFCLK */
/* SYSCTL_GENCLKCFG[EXCLKDIVVAL] Bits */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_OFS (4) /* !< EXCLKDIVVAL Offset */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_MASK ((uint32_t)0x00000070U) /* !< EXCLKDIVVAL selects the divider
value for the divider in the CLK_OUT
external clock output block. */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV2 ((uint32_t)0x00000000U) /* !< CLK_OUT source is divided by 2 */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV4 ((uint32_t)0x00000010U) /* !< CLK_OUT source is divided by 4 */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV6 ((uint32_t)0x00000020U) /* !< CLK_OUT source is divided by 6 */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV8 ((uint32_t)0x00000030U) /* !< CLK_OUT source is divided by 8 */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV10 ((uint32_t)0x00000040U) /* !< CLK_OUT source is divided by 10 */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV12 ((uint32_t)0x00000050U) /* !< CLK_OUT source is divided by 12 */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV14 ((uint32_t)0x00000060U) /* !< CLK_OUT source is divided by 14 */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV16 ((uint32_t)0x00000070U) /* !< CLK_OUT source is divided by 16 */
/* SYSCTL_GENCLKCFG[EXCLKDIVEN] Bits */
#define SYSCTL_GENCLKCFG_EXCLKDIVEN_OFS (7) /* !< EXCLKDIVEN Offset */
#define SYSCTL_GENCLKCFG_EXCLKDIVEN_MASK ((uint32_t)0x00000080U) /* !< EXCLKDIVEN enables or disables the
divider function of the CLK_OUT
external clock output block. */
#define SYSCTL_GENCLKCFG_EXCLKDIVEN_PASSTHRU ((uint32_t)0x00000000U) /* !< CLock divider is disabled
(passthrough, EXCLKDIVVAL is not
applied) */
#define SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE ((uint32_t)0x00000080U) /* !< Clock divider is enabled
(EXCLKDIVVAL is applied) */
/* SYSCTL_GENCLKEN Bits */
/* SYSCTL_GENCLKEN[EXCLKEN] Bits */
#define SYSCTL_GENCLKEN_EXCLKEN_OFS (0) /* !< EXCLKEN Offset */
#define SYSCTL_GENCLKEN_EXCLKEN_MASK ((uint32_t)0x00000001U) /* !< EXCLKEN enables the CLK_OUT
external clock output block. */
#define SYSCTL_GENCLKEN_EXCLKEN_DISABLE ((uint32_t)0x00000000U) /* !< CLK_OUT block is disabled */
#define SYSCTL_GENCLKEN_EXCLKEN_ENABLE ((uint32_t)0x00000001U) /* !< CLK_OUT block is enabled */
/* SYSCTL_GENCLKEN[MFPCLKEN] Bits */
#define SYSCTL_GENCLKEN_MFPCLKEN_OFS (4) /* !< MFPCLKEN Offset */
#define SYSCTL_GENCLKEN_MFPCLKEN_MASK ((uint32_t)0x00000010U) /* !< MFPCLKEN enables the middle
frequency precision clock (MFPCLK). */
#define SYSCTL_GENCLKEN_MFPCLKEN_DISABLE ((uint32_t)0x00000000U) /* !< MFPCLK is disabled */
#define SYSCTL_GENCLKEN_MFPCLKEN_ENABLE ((uint32_t)0x00000010U) /* !< MFPCLK is enabled */
/* SYSCTL_PMODECFG Bits */
/* SYSCTL_PMODECFG[DSLEEP] Bits */
#define SYSCTL_PMODECFG_DSLEEP_OFS (0) /* !< DSLEEP Offset */
#define SYSCTL_PMODECFG_DSLEEP_MASK ((uint32_t)0x00000003U) /* !< DSLEEP selects the operating mode
to enter upon a DEEPSLEEP request
from the CPU. */
#define SYSCTL_PMODECFG_DSLEEP_STOP ((uint32_t)0x00000000U) /* !< STOP mode is entered */
#define SYSCTL_PMODECFG_DSLEEP_STANDBY ((uint32_t)0x00000001U) /* !< STANDBY mode is entered */
#define SYSCTL_PMODECFG_DSLEEP_SHUTDOWN ((uint32_t)0x00000002U) /* !< SHUTDOWN mode is entered */
/* SYSCTL_FCC Bits */
/* SYSCTL_FCC[DATA] Bits */
#define SYSCTL_FCC_DATA_OFS (0) /* !< DATA Offset */
#define SYSCTL_FCC_DATA_MASK ((uint32_t)0x003FFFFFU) /* !< Frequency clock counter (FCC) count
value. */
/* SYSCTL_SRAMBOUNDARY Bits */
/* SYSCTL_SRAMBOUNDARY[ADDR] Bits */
#define SYSCTL_SRAMBOUNDARY_ADDR_OFS (5) /* !< ADDR Offset */
#define SYSCTL_SRAMBOUNDARY_ADDR_MASK ((uint32_t)0x000FFFE0U) /* !< SRAM boundary configuration. The
value configured into this acts such
that: SRAM accesses to addresses less
than or equal value will be RW only.
SRAM accesses to addresses greater
than value will be RX only. Value of
0 is not valid (system will have no
stack). If set to 0, the system acts
as if the entire SRAM is RWX. Any
non-zero value can be configured,
including a value = SRAM size. */
/* SYSCTL_SYSTEMCFG Bits */
/* SYSCTL_SYSTEMCFG[KEY] Bits */
#define SYSCTL_SYSTEMCFG_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_SYSTEMCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 1Bh (27) must be
written to KEY together with contents
to be updated. Reads as 0 */
#define SYSCTL_SYSTEMCFG_KEY_VALUE ((uint32_t)0x1B000000U) /* !< Issue write */
/* SYSCTL_SYSTEMCFG[WWDTLP0RSTDIS] Bits */
#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS (0) /* !< WWDTLP0RSTDIS Offset */
#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK ((uint32_t)0x00000001U) /* !< WWDTLP0RSTDIS specifies whether a
WWDT Error Event will trigger a
BOOTRST or an NMI. */
#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_FALSE ((uint32_t)0x00000000U) /* !< WWDTLP0 Error Event will trigger a
BOOTRST */
#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_TRUE ((uint32_t)0x00000001U) /* !< WWDTLP0 Error Event will trigger an
NMI */
/* SYSCTL_BEEPCFG Bits */
/* SYSCTL_BEEPCFG[FREQ] Bits */
#define SYSCTL_BEEPCFG_FREQ_OFS (4) /* !< FREQ Offset */
#define SYSCTL_BEEPCFG_FREQ_MASK ((uint32_t)0x00000030U) /* !< Beeper Output Frequency
Configuration */
#define SYSCTL_BEEPCFG_FREQ_8KHZ ((uint32_t)0x00000000U) /* !< Beeper runs at 8KHz */
#define SYSCTL_BEEPCFG_FREQ_4KHZ ((uint32_t)0x00000010U) /* !< Beeper runs at 4KHz */
#define SYSCTL_BEEPCFG_FREQ_2KHZ ((uint32_t)0x00000020U) /* !< Beeper runs at 2KHz */
#define SYSCTL_BEEPCFG_FREQ_1KHZ ((uint32_t)0x00000030U) /* !< Beeper runs at 1KHz */
/* SYSCTL_BEEPCFG[EN] Bits */
#define SYSCTL_BEEPCFG_EN_OFS (0) /* !< EN Offset */
#define SYSCTL_BEEPCFG_EN_MASK ((uint32_t)0x00000001U) /* !< Beeper Output Enable */
#define SYSCTL_BEEPCFG_EN_DISABLE ((uint32_t)0x00000000U) /* !< Beeper Output Disabled */
#define SYSCTL_BEEPCFG_EN_ENABLE ((uint32_t)0x00000001U) /* !< Beeper Output Enabled */
/* SYSCTL_WRITELOCK Bits */
/* SYSCTL_WRITELOCK[ACTIVE] Bits */
#define SYSCTL_WRITELOCK_ACTIVE_OFS (0) /* !< ACTIVE Offset */
#define SYSCTL_WRITELOCK_ACTIVE_MASK ((uint32_t)0x00000001U) /* !< ACTIVE controls whether critical
SYSCTL registers are write protected
or not. */
#define SYSCTL_WRITELOCK_ACTIVE_DISABLE ((uint32_t)0x00000000U) /* !< Allow writes to lockable registers */
#define SYSCTL_WRITELOCK_ACTIVE_ENABLE ((uint32_t)0x00000001U) /* !< Disallow writes to lockable
registers */
/* SYSCTL_CLKSTATUS Bits */
/* SYSCTL_CLKSTATUS[LFOSCGOOD] Bits */
#define SYSCTL_CLKSTATUS_LFOSCGOOD_OFS (11) /* !< LFOSCGOOD Offset */
#define SYSCTL_CLKSTATUS_LFOSCGOOD_MASK ((uint32_t)0x00000800U) /* !< LFOSCGOOD indicates when the LFOSC
startup has completed and the LFOSC
is ready for use. */
#define SYSCTL_CLKSTATUS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< LFOSC is not ready */
#define SYSCTL_CLKSTATUS_LFOSCGOOD_TRUE ((uint32_t)0x00000800U) /* !< LFOSC is ready */
/* SYSCTL_CLKSTATUS[ANACLKERR] Bits */
#define SYSCTL_CLKSTATUS_ANACLKERR_OFS (31) /* !< ANACLKERR Offset */
#define SYSCTL_CLKSTATUS_ANACLKERR_MASK ((uint32_t)0x80000000U) /* !< ANACLKERR is set when the device
clock configuration does not support
an enabled analog peripheral mode and
the analog peripheral may not be
functioning as expected. */
#define SYSCTL_CLKSTATUS_ANACLKERR_FALSE ((uint32_t)0x00000000U) /* !< No analog clock errors detected */
#define SYSCTL_CLKSTATUS_ANACLKERR_TRUE ((uint32_t)0x80000000U) /* !< Analog clock error detected */
/* SYSCTL_CLKSTATUS[HSCLKMUX] Bits */
#define SYSCTL_CLKSTATUS_HSCLKMUX_OFS (4) /* !< HSCLKMUX Offset */
#define SYSCTL_CLKSTATUS_HSCLKMUX_MASK ((uint32_t)0x00000010U) /* !< HSCLKMUX indicates if MCLK is
currently sourced from the high-speed
clock (HSCLK). */
#define SYSCTL_CLKSTATUS_HSCLKMUX_SYSOSC ((uint32_t)0x00000000U) /* !< MCLK is not sourced from HSCLK */
#define SYSCTL_CLKSTATUS_HSCLKMUX_HSCLK ((uint32_t)0x00000010U) /* !< MCLK is sourced from HSCLK */
/* SYSCTL_CLKSTATUS[LFCLKMUX] Bits */
#define SYSCTL_CLKSTATUS_LFCLKMUX_OFS (6) /* !< LFCLKMUX Offset */
#define SYSCTL_CLKSTATUS_LFCLKMUX_MASK ((uint32_t)0x000000C0U) /* !< LFCLKMUX indicates if LFCLK is
sourced from the internal LFOSC, the
low frequency crystal (LFXT), or the
LFCLK_IN digital clock input. */
#define SYSCTL_CLKSTATUS_LFCLKMUX_LFOSC ((uint32_t)0x00000000U) /* !< LFCLK is sourced from the internal
LFOSC */
#define SYSCTL_CLKSTATUS_LFCLKMUX_LFXT ((uint32_t)0x00000040U) /* !< LFCLK is sourced from the LFXT
(crystal) */
#define SYSCTL_CLKSTATUS_LFCLKMUX_EXLF ((uint32_t)0x00000080U) /* !< LFCLK is sourced from LFCLK_IN
(external digital clock input) */
/* SYSCTL_CLKSTATUS[SYSOSCFREQ] Bits */
#define SYSCTL_CLKSTATUS_SYSOSCFREQ_OFS (0) /* !< SYSOSCFREQ Offset */
#define SYSCTL_CLKSTATUS_SYSOSCFREQ_MASK ((uint32_t)0x00000003U) /* !< SYSOSCFREQ indicates the current
SYSOSC operating frequency. */
#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC32M ((uint32_t)0x00000000U) /* !< SYSOSC is at base frequency (32MHz) */
#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC4M ((uint32_t)0x00000001U) /* !< SYSOSC is at low frequency (4MHz) */
#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCUSER ((uint32_t)0x00000002U) /* !< SYSOSC is at the user-trimmed
frequency (16 or 24MHz) */
#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCTURBO ((uint32_t)0x00000003U) /* !< Reserved */
/* SYSCTL_CLKSTATUS[FCLMODE] Bits */
#define SYSCTL_CLKSTATUS_FCLMODE_OFS (24) /* !< FCLMODE Offset */
#define SYSCTL_CLKSTATUS_FCLMODE_MASK ((uint32_t)0x01000000U) /* !< FCLMODE indicates if the SYSOSC
frequency correction loop (FCL) is
enabled. */
#define SYSCTL_CLKSTATUS_FCLMODE_DISABLED ((uint32_t)0x00000000U) /* !< SYSOSC FCL is disabled */
#define SYSCTL_CLKSTATUS_FCLMODE_ENABLED ((uint32_t)0x01000000U) /* !< SYSOSC FCL is enabled */
/* SYSCTL_CLKSTATUS[CURMCLKSEL] Bits */
#define SYSCTL_CLKSTATUS_CURMCLKSEL_OFS (17) /* !< CURMCLKSEL Offset */
#define SYSCTL_CLKSTATUS_CURMCLKSEL_MASK ((uint32_t)0x00020000U) /* !< CURMCLKSEL indicates if MCLK is
currently sourced from LFCLK. */
#define SYSCTL_CLKSTATUS_CURMCLKSEL_NOTLFCLK ((uint32_t)0x00000000U) /* !< MCLK is not sourced from LFCLK */
#define SYSCTL_CLKSTATUS_CURMCLKSEL_LFCLK ((uint32_t)0x00020000U) /* !< MCLK is sourced from LFCLK */
/* SYSCTL_CLKSTATUS[FCCDONE] Bits */
#define SYSCTL_CLKSTATUS_FCCDONE_OFS (25) /* !< FCCDONE Offset */
#define SYSCTL_CLKSTATUS_FCCDONE_MASK ((uint32_t)0x02000000U) /* !< FCCDONE indicates when a frequency
clock counter capture is complete. */
#define SYSCTL_CLKSTATUS_FCCDONE_NOTDONE ((uint32_t)0x00000000U) /* !< FCC capture is not done */
#define SYSCTL_CLKSTATUS_FCCDONE_DONE ((uint32_t)0x02000000U) /* !< FCC capture is done */
/* SYSCTL_SYSSTATUS Bits */
/* SYSCTL_SYSSTATUS[SHDNIOLOCK] Bits */
#define SYSCTL_SYSSTATUS_SHDNIOLOCK_OFS (14) /* !< SHDNIOLOCK Offset */
#define SYSCTL_SYSSTATUS_SHDNIOLOCK_MASK ((uint32_t)0x00004000U) /* !< SHDNIOLOCK indicates when IO is
locked due to SHUTDOWN */
#define SYSCTL_SYSSTATUS_SHDNIOLOCK_FALSE ((uint32_t)0x00000000U) /* !< IO IS NOT Locked due to SHUTDOWN */
#define SYSCTL_SYSSTATUS_SHDNIOLOCK_TRUE ((uint32_t)0x00004000U) /* !< IO IS Locked due to SHUTDOWN */
/* SYSCTL_SYSSTATUS[EXTRSTPINDIS] Bits */
#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_OFS (12) /* !< EXTRSTPINDIS Offset */
#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_MASK ((uint32_t)0x00001000U) /* !< EXTRSTPINDIS indicates when user
has disabled the use of external
reset pin */
#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_FALSE ((uint32_t)0x00000000U) /* !< External Reset Pin Enabled */
#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_TRUE ((uint32_t)0x00001000U) /* !< External Reset Pin Disabled */
/* SYSCTL_SYSSTATUS[PMUIREFGOOD] Bits */
#define SYSCTL_SYSSTATUS_PMUIREFGOOD_OFS (6) /* !< PMUIREFGOOD Offset */
#define SYSCTL_SYSSTATUS_PMUIREFGOOD_MASK ((uint32_t)0x00000040U) /* !< PMUIREFGOOD is set by hardware when
the PMU current reference is ready. */
#define SYSCTL_SYSSTATUS_PMUIREFGOOD_FALSE ((uint32_t)0x00000000U) /* !< IREF is not ready */
#define SYSCTL_SYSSTATUS_PMUIREFGOOD_TRUE ((uint32_t)0x00000040U) /* !< IREF is ready */
/* SYSCTL_SYSSTATUS[SWDCFGDIS] Bits */
#define SYSCTL_SYSSTATUS_SWDCFGDIS_OFS (13) /* !< SWDCFGDIS Offset */
#define SYSCTL_SYSSTATUS_SWDCFGDIS_MASK ((uint32_t)0x00002000U) /* !< SWDCFGDIS indicates when user has
disabled the use of SWD Port */
#define SYSCTL_SYSSTATUS_SWDCFGDIS_FALSE ((uint32_t)0x00000000U) /* !< SWD Port Enabled */
#define SYSCTL_SYSSTATUS_SWDCFGDIS_TRUE ((uint32_t)0x00002000U) /* !< SWD Port Disabled */
/* SYSCTL_SYSSTATUS[ANACPUMPGOOD] Bits */
#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_OFS (5) /* !< ANACPUMPGOOD Offset */
#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_MASK ((uint32_t)0x00000020U) /* !< ANACPUMPGOOD is set by hardware
when the VBOOST analog mux charge
pump is ready. */
#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_FALSE ((uint32_t)0x00000000U) /* !< VBOOST is not ready */
#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_TRUE ((uint32_t)0x00000020U) /* !< VBOOST is ready */
/* SYSCTL_SYSSTATUS[REBOOTATTEMPTS] Bits */
#define SYSCTL_SYSSTATUS_REBOOTATTEMPTS_OFS (30) /* !< REBOOTATTEMPTS Offset */
#define SYSCTL_SYSSTATUS_REBOOTATTEMPTS_MASK ((uint32_t)0xC0000000U) /* !< REBOOTATTEMPTS indicates the number
of boot attempts taken before the
user application starts. */
/* SYSCTL_SYSSTATUS[BORLVL] Bits */
#define SYSCTL_SYSSTATUS_BORLVL_OFS (4) /* !< BORLVL Offset */
#define SYSCTL_SYSSTATUS_BORLVL_MASK ((uint32_t)0x00000010U) /* !< BORLVL indicates if a BOR event
occured and the BOR threshold was
switched to BOR0 by hardware. */
#define SYSCTL_SYSSTATUS_BORLVL_FALSE ((uint32_t)0x00000000U) /* !< No BOR violation occured */
#define SYSCTL_SYSSTATUS_BORLVL_TRUE ((uint32_t)0x00000010U) /* !< A BOR violation occured and the BOR
threshold was switched to BOR0 */
/* SYSCTL_SYSSTATUS[BORCURTHRESHOLD] Bits */
#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_OFS (2) /* !< BORCURTHRESHOLD Offset */
#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_MASK ((uint32_t)0x0000000CU) /* !< BORCURTHRESHOLD indicates the
active brown-out reset supply monitor
configuration. */
#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORMIN ((uint32_t)0x00000000U) /* !< Default minimum threshold; a BOR0-
violation triggers a BOR */
#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL1 ((uint32_t)0x00000004U) /* !< A BOR1- violation generates a
BORLVL interrupt */
#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL2 ((uint32_t)0x00000008U) /* !< A BOR2- violation generates a
BORLVL interrupt */
#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL3 ((uint32_t)0x0000000CU) /* !< A BOR3- violation generates a
BORLVL interrupt */
/* SYSCTL_RSTCAUSE Bits */
/* SYSCTL_RSTCAUSE[ID] Bits */
#define SYSCTL_RSTCAUSE_ID_OFS (0) /* !< ID Offset */
#define SYSCTL_RSTCAUSE_ID_MASK ((uint32_t)0x0000001FU) /* !< ID is a read-to-clear field which
indicates the lowest level reset
cause since the last read. */
#define SYSCTL_RSTCAUSE_ID_NORST ((uint32_t)0x00000000U) /* !< No reset since last read */
#define SYSCTL_RSTCAUSE_ID_PORHWFAIL ((uint32_t)0x00000001U) /* !< POR- violation, SHUTDNSTOREx or PMU
trim parity fault */
#define SYSCTL_RSTCAUSE_ID_POREXNRST ((uint32_t)0x00000002U) /* !< NRST triggered POR (&gt;1s hold) */
#define SYSCTL_RSTCAUSE_ID_PORSW ((uint32_t)0x00000003U) /* !< Software triggered POR */
#define SYSCTL_RSTCAUSE_ID_BORSUPPLY ((uint32_t)0x00000004U) /* !< BOR0- violation */
#define SYSCTL_RSTCAUSE_ID_BORWAKESHUTDN ((uint32_t)0x00000005U) /* !< SHUTDOWN mode exit */
#define SYSCTL_RSTCAUSE_ID_BOOTNONPMUPARITY ((uint32_t)0x00000008U) /* !< Non-PMU trim parity fault */
#define SYSCTL_RSTCAUSE_ID_BOOTCLKFAIL ((uint32_t)0x00000009U) /* !< Fatal clock failure */
#define SYSCTL_RSTCAUSE_ID_BOOTEXNRST ((uint32_t)0x0000000CU) /* !< NRST triggered BOOTRST (&lt;1s
hold) */
#define SYSCTL_RSTCAUSE_ID_BOOTSW ((uint32_t)0x0000000DU) /* !< Software triggered BOOTRST */
#define SYSCTL_RSTCAUSE_ID_SYSWWDT0 ((uint32_t)0x0000000EU) /* !< WWDT0 violation */
#define SYSCTL_RSTCAUSE_ID_SYSBSLEXIT ((uint32_t)0x00000010U) /* !< BSL exit */
#define SYSCTL_RSTCAUSE_ID_SYSBSLENTRY ((uint32_t)0x00000011U) /* !< BSL entry */
#define SYSCTL_RSTCAUSE_ID_SYSWWDT1 ((uint32_t)0x00000013U) /* !< WWDT1 violation */
#define SYSCTL_RSTCAUSE_ID_SYSFLASHECC ((uint32_t)0x00000014U) /* !< Flash uncorrectable ECC error */
#define SYSCTL_RSTCAUSE_ID_SYSCPULOCK ((uint32_t)0x00000015U) /* !< CPULOCK violation */
#define SYSCTL_RSTCAUSE_ID_SYSDBG ((uint32_t)0x0000001AU) /* !< Debug triggered SYSRST */
#define SYSCTL_RSTCAUSE_ID_SYSSW ((uint32_t)0x0000001BU) /* !< Software triggered SYSRST */
#define SYSCTL_RSTCAUSE_ID_CPUDBG ((uint32_t)0x0000001CU) /* !< Debug triggered CPURST */
#define SYSCTL_RSTCAUSE_ID_CPUSW ((uint32_t)0x0000001DU) /* !< Software triggered CPURST */
/* SYSCTL_RESETLEVEL Bits */
/* SYSCTL_RESETLEVEL[LEVEL] Bits */
#define SYSCTL_RESETLEVEL_LEVEL_OFS (0) /* !< LEVEL Offset */
#define SYSCTL_RESETLEVEL_LEVEL_MASK ((uint32_t)0x00000007U) /* !< LEVEL is used to specify the type
of reset to be issued when RESETCMD
is set to generate a software
triggered reset. */
#define SYSCTL_RESETLEVEL_LEVEL_CPU ((uint32_t)0x00000000U) /* !< Issue a SYSRST (CPU plus
peripherals only) */
#define SYSCTL_RESETLEVEL_LEVEL_BOOT ((uint32_t)0x00000001U) /* !< Issue a BOOTRST (CPU, peripherals,
and boot configuration routine) */
#define SYSCTL_RESETLEVEL_LEVEL_BOOTLOADERENTRY ((uint32_t)0x00000002U) /* !< Issue a SYSRST and enter the boot
strap loader (BSL) */
#define SYSCTL_RESETLEVEL_LEVEL_POR ((uint32_t)0x00000003U) /* !< Issue a power-on reset (POR) */
#define SYSCTL_RESETLEVEL_LEVEL_BOOTLOADEREXIT ((uint32_t)0x00000004U) /* !< Issue a SYSRST and exit the boot
strap loader (BSL) */
/* SYSCTL_RESETCMD Bits */
/* SYSCTL_RESETCMD[KEY] Bits */
#define SYSCTL_RESETCMD_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_RESETCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of E4h (228) must be
written to KEY together with GO to
trigger the reset. */
#define SYSCTL_RESETCMD_KEY_VALUE ((uint32_t)0xE4000000U) /* !< Issue reset */
/* SYSCTL_RESETCMD[GO] Bits */
#define SYSCTL_RESETCMD_GO_OFS (0) /* !< GO Offset */
#define SYSCTL_RESETCMD_GO_MASK ((uint32_t)0x00000001U) /* !< Execute the reset specified in
RESETLEVEL.LEVEL. Must be written
together with the KEY. */
#define SYSCTL_RESETCMD_GO_TRUE ((uint32_t)0x00000001U) /* !< Issue reset */
/* SYSCTL_BORTHRESHOLD Bits */
/* SYSCTL_BORTHRESHOLD[LEVEL] Bits */
#define SYSCTL_BORTHRESHOLD_LEVEL_OFS (0) /* !< LEVEL Offset */
#define SYSCTL_BORTHRESHOLD_LEVEL_MASK ((uint32_t)0x00000003U) /* !< LEVEL specifies the desired BOR
threshold and BOR mode. */
#define SYSCTL_BORTHRESHOLD_LEVEL_BORMIN ((uint32_t)0x00000000U) /* !< Default minimum threshold; a BOR0-
violation triggers a BOR */
#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL1 ((uint32_t)0x00000001U) /* !< A BOR1- violation generates a
BORLVL interrupt */
#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL2 ((uint32_t)0x00000002U) /* !< A BOR2- violation generates a
BORLVL interrupt */
#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL3 ((uint32_t)0x00000003U) /* !< A BOR3- violation generates a
BORLVL interrupt */
/* SYSCTL_BORCLRCMD Bits */
/* SYSCTL_BORCLRCMD[KEY] Bits */
#define SYSCTL_BORCLRCMD_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_BORCLRCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of C7h (199) must be
written to KEY together with GO to
trigger the clear and BOR threshold
change. */
#define SYSCTL_BORCLRCMD_KEY_VALUE ((uint32_t)0xC7000000U) /* !< Issue clear */
/* SYSCTL_BORCLRCMD[GO] Bits */
#define SYSCTL_BORCLRCMD_GO_OFS (0) /* !< GO Offset */
#define SYSCTL_BORCLRCMD_GO_MASK ((uint32_t)0x00000001U) /* !< GO clears any prior BOR violation
status indications and attempts to
change the active BOR mode to that
specified in the LEVEL field of the
BORTHRESHOLD register. */
#define SYSCTL_BORCLRCMD_GO_TRUE ((uint32_t)0x00000001U) /* !< Issue clear */
/* SYSCTL_SYSOSCFCLCTL Bits */
/* SYSCTL_SYSOSCFCLCTL[KEY] Bits */
#define SYSCTL_SYSOSCFCLCTL_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_SYSOSCFCLCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 2Ah (42) must be
written to KEY together with
SETUSEFCL to enable the FCL. */
#define SYSCTL_SYSOSCFCLCTL_KEY_VALUE ((uint32_t)0x2A000000U) /* !< Issue Command */
/* SYSCTL_SYSOSCFCLCTL[SETUSEFCL] Bits */
#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_OFS (0) /* !< SETUSEFCL Offset */
#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_MASK ((uint32_t)0x00000001U) /* !< Set SETUSEFCL to enable the
frequency correction loop in SYSOSC.
Once enabled, this state is locked
until the next BOOTRST. */
#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE ((uint32_t)0x00000001U) /* !< Enable the SYSOSC FCL */
/* SYSCTL_EXLFCTL Bits */
/* SYSCTL_EXLFCTL[KEY] Bits */
#define SYSCTL_EXLFCTL_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_EXLFCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 36h (54) must be
written to KEY together with
SETUSEEXLF to set SETUSEEXLF. */
#define SYSCTL_EXLFCTL_KEY_VALUE ((uint32_t)0x36000000U) /* !< Issue command */
/* SYSCTL_EXLFCTL[SETUSEEXLF] Bits */
#define SYSCTL_EXLFCTL_SETUSEEXLF_OFS (0) /* !< SETUSEEXLF Offset */
#define SYSCTL_EXLFCTL_SETUSEEXLF_MASK ((uint32_t)0x00000001U) /* !< Set SETUSEEXLF to switch LFCLK to
the LFCLK_IN digital clock input.
Once set, SETUSEEXLF remains set
until the next BOOTRST. */
#define SYSCTL_EXLFCTL_SETUSEEXLF_TRUE ((uint32_t)0x00000001U) /* !< Use LFCLK_IN as the LFCLK source */
/* SYSCTL_SHDNIOREL Bits */
/* SYSCTL_SHDNIOREL[KEY] Bits */
#define SYSCTL_SHDNIOREL_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_SHDNIOREL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 91h must be written
to KEY together with RELEASE to set
RELEASE. */
#define SYSCTL_SHDNIOREL_KEY_VALUE ((uint32_t)0x91000000U) /* !< Issue command */
/* SYSCTL_SHDNIOREL[RELEASE] Bits */
#define SYSCTL_SHDNIOREL_RELEASE_OFS (0) /* !< RELEASE Offset */
#define SYSCTL_SHDNIOREL_RELEASE_MASK ((uint32_t)0x00000001U) /* !< Set RELEASE to release the IO after
a SHUTDOWN mode exit. */
#define SYSCTL_SHDNIOREL_RELEASE_TRUE ((uint32_t)0x00000001U) /* !< Release IO */
/* SYSCTL_EXRSTPIN Bits */
/* SYSCTL_EXRSTPIN[KEY] Bits */
#define SYSCTL_EXRSTPIN_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_EXRSTPIN_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 1Eh must be written
together with DISABLE to disable the
reset function. */
#define SYSCTL_EXRSTPIN_KEY_VALUE ((uint32_t)0x1E000000U) /* !< Issue command */
/* SYSCTL_EXRSTPIN[DISABLE] Bits */
#define SYSCTL_EXRSTPIN_DISABLE_OFS (0) /* !< DISABLE Offset */
#define SYSCTL_EXRSTPIN_DISABLE_MASK ((uint32_t)0x00000001U) /* !< Set DISABLE to disable the reset
function of the NRST pin. Once set,
this configuration is locked until
the next POR. */
#define SYSCTL_EXRSTPIN_DISABLE_FALSE ((uint32_t)0x00000000U) /* !< Reset function of NRST pin is
enabled */
#define SYSCTL_EXRSTPIN_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Reset function of NRST pin is
disabled */
/* SYSCTL_SYSSTATUSCLR Bits */
/* SYSCTL_SYSSTATUSCLR[KEY] Bits */
#define SYSCTL_SYSSTATUSCLR_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_SYSSTATUSCLR_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value CEh (206) must be
written to KEY together with ALLECC
to clear the ECC state. */
#define SYSCTL_SYSSTATUSCLR_KEY_VALUE ((uint32_t)0xCE000000U) /* !< Issue command */
/* SYSCTL_SYSSTATUSCLR[ALLECC] Bits */
#define SYSCTL_SYSSTATUSCLR_ALLECC_OFS (0) /* !< ALLECC Offset */
#define SYSCTL_SYSSTATUSCLR_ALLECC_MASK ((uint32_t)0x00000001U) /* !< Set ALLECC to clear all ECC related
SYSSTATUS indicators. */
#define SYSCTL_SYSSTATUSCLR_ALLECC_CLEAR ((uint32_t)0x00000001U) /* !< Clear ECC error state */
/* SYSCTL_SWDCFG Bits */
/* SYSCTL_SWDCFG[KEY] Bits */
#define SYSCTL_SWDCFG_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_SWDCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 62h (98) must be
written to KEY together with DISBALE
to disable the SWD functions. */
#define SYSCTL_SWDCFG_KEY_VALUE ((uint32_t)0x62000000U) /* !< Issue command */
/* SYSCTL_SWDCFG[DISABLE] Bits */
#define SYSCTL_SWDCFG_DISABLE_OFS (0) /* !< DISABLE Offset */
#define SYSCTL_SWDCFG_DISABLE_MASK ((uint32_t)0x00000001U) /* !< Set DISABLE to disable the SWD
function on SWD pins, allowing the
SWD pins to be used as GPIO. */
#define SYSCTL_SWDCFG_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Disable SWD function on SWD pins */
/* SYSCTL_FCCCMD Bits */
/* SYSCTL_FCCCMD[KEY] Bits */
#define SYSCTL_FCCCMD_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_FCCCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 0Eh (14) must be
written with GO to start a capture. */
#define SYSCTL_FCCCMD_KEY_VALUE ((uint32_t)0x0E000000U) /* !< Issue command */
/* SYSCTL_FCCCMD[GO] Bits */
#define SYSCTL_FCCCMD_GO_OFS (0) /* !< GO Offset */
#define SYSCTL_FCCCMD_GO_MASK ((uint32_t)0x00000001U) /* !< Set GO to start a capture with the
frequency clock counter (FCC). */
#define SYSCTL_FCCCMD_GO_TRUE ((uint32_t)0x00000001U)
/* SYSCTL_SHUTDNSTORE0 Bits */
/* SYSCTL_SHUTDNSTORE0[DATA] Bits */
#define SYSCTL_SHUTDNSTORE0_DATA_OFS (0) /* !< DATA Offset */
#define SYSCTL_SHUTDNSTORE0_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 0 */
/* SYSCTL_SHUTDNSTORE1 Bits */
/* SYSCTL_SHUTDNSTORE1[DATA] Bits */
#define SYSCTL_SHUTDNSTORE1_DATA_OFS (0) /* !< DATA Offset */
#define SYSCTL_SHUTDNSTORE1_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 1 */
/* SYSCTL_SHUTDNSTORE2 Bits */
/* SYSCTL_SHUTDNSTORE2[DATA] Bits */
#define SYSCTL_SHUTDNSTORE2_DATA_OFS (0) /* !< DATA Offset */
#define SYSCTL_SHUTDNSTORE2_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 2 */
/* SYSCTL_SHUTDNSTORE3 Bits */
/* SYSCTL_SHUTDNSTORE3[DATA] Bits */
#define SYSCTL_SHUTDNSTORE3_DATA_OFS (0) /* !< DATA Offset */
#define SYSCTL_SHUTDNSTORE3_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 3 */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0c110x__include */
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