SkyLi
826 lines
68 KiB
C
826 lines
68 KiB
C
/*****************************************************************************
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Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the
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distribution.
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Neither the name of Texas Instruments Incorporated nor the names of
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its contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#ifndef ti_devices_msp_peripherals_hw_comp__include
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#define ti_devices_msp_peripherals_hw_comp__include
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/* Filename: hw_comp.h */
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/* Revised: 2023-05-10 21:23:38 */
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/* Revision: 5c29864c187960f76e656cbc0f0f844cdb69a263 */
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#ifndef __CORTEX_M
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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#endif
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/* Use standard integer types with explicit width */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/******************************************************************************
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* COMP Registers
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******************************************************************************/
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#define COMP_GEN_EVENT_OFS ((uint32_t)0x00001050U)
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#define COMP_CPU_INT_OFS ((uint32_t)0x00001020U)
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#define COMP_GPRCM_OFS ((uint32_t)0x00000800U)
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/** @addtogroup COMP_GEN_EVENT
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@{
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*/
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typedef struct {
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__I uint32_t IIDX; /* !< (@ 0x00001050) Interrupt index */
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uint32_t RESERVED0;
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__IO uint32_t IMASK; /* !< (@ 0x00001058) Interrupt mask */
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uint32_t RESERVED1;
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__I uint32_t RIS; /* !< (@ 0x00001060) Raw interrupt status */
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uint32_t RESERVED2;
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__I uint32_t MIS; /* !< (@ 0x00001068) Masked interrupt status */
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uint32_t RESERVED3;
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__O uint32_t ISET; /* !< (@ 0x00001070) Interrupt set */
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uint32_t RESERVED4;
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__O uint32_t ICLR; /* !< (@ 0x00001078) Interrupt clear */
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} COMP_GEN_EVENT_Regs;
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/*@}*/ /* end of group COMP_GEN_EVENT */
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/** @addtogroup COMP_CPU_INT
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@{
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*/
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typedef struct {
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__I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */
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uint32_t RESERVED0;
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__IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */
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uint32_t RESERVED1;
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__I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */
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uint32_t RESERVED2;
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__I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */
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uint32_t RESERVED3;
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__O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */
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uint32_t RESERVED4;
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__O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */
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} COMP_CPU_INT_Regs;
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/*@}*/ /* end of group COMP_CPU_INT */
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/** @addtogroup COMP_GPRCM
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@{
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*/
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typedef struct {
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__IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */
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__O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */
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__IO uint32_t CLKCFG; /* !< (@ 0x00000808) Peripheral Clock Configuration Register */
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uint32_t RESERVED0[2];
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__I uint32_t STAT; /* !< (@ 0x00000814) Status Register */
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} COMP_GPRCM_Regs;
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/*@}*/ /* end of group COMP_GPRCM */
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/** @addtogroup COMP
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@{
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*/
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typedef struct {
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uint32_t RESERVED0[256];
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__IO uint32_t FSUB_0; /* !< (@ 0x00000400) Subscriber Port 0 */
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__IO uint32_t FSUB_1; /* !< (@ 0x00000404) Subscriber Port 1 */
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uint32_t RESERVED1[15];
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__IO uint32_t FPUB_1; /* !< (@ 0x00000444) Publisher port 1 */
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uint32_t RESERVED2[238];
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COMP_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */
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uint32_t RESERVED3[514];
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COMP_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */
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uint32_t RESERVED4;
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COMP_GEN_EVENT_Regs GEN_EVENT; /* !< (@ 0x00001050) */
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uint32_t RESERVED5[25];
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__IO uint32_t EVT_MODE; /* !< (@ 0x000010E0) Event Mode */
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uint32_t RESERVED6[6];
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__I uint32_t DESC; /* !< (@ 0x000010FC) Module Description */
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__IO uint32_t CTL0; /* !< (@ 0x00001100) Control 0 */
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__IO uint32_t CTL1; /* !< (@ 0x00001104) Control 1 */
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__IO uint32_t CTL2; /* !< (@ 0x00001108) Control 2 */
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__IO uint32_t CTL3; /* !< (@ 0x0000110C) Control 3 */
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uint32_t RESERVED7[4];
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__I uint32_t STAT; /* !< (@ 0x00001120) Status */
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} COMP_Regs;
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/*@}*/ /* end of group COMP */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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/******************************************************************************
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* COMP Register Control Bits
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******************************************************************************/
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/* COMP_GEN_EVENT_IIDX Bits */
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/* COMP_GEN_EVENT_IIDX[STAT] Bits */
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#define COMP_GEN_EVENT_IIDX_STAT_OFS (0) /* !< STAT Offset */
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#define COMP_GEN_EVENT_IIDX_STAT_MASK ((uint32_t)0x00000003U) /* !< Interrupt index status */
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#define COMP_GEN_EVENT_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No pending interrupt */
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#define COMP_GEN_EVENT_IIDX_STAT_COMPIFG ((uint32_t)0x00000002U) /* !< Comparator output interrupt */
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#define COMP_GEN_EVENT_IIDX_STAT_COMPINVIFG ((uint32_t)0x00000003U) /* !< Comparator output inverted
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interrupt */
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#define COMP_GEN_EVENT_IIDX_STAT_OUTRDYIFG ((uint32_t)0x00000004U) /* !< Comparator output ready interrupt */
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/* COMP_GEN_EVENT_IMASK Bits */
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/* COMP_GEN_EVENT_IMASK[COMPIFG] Bits */
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#define COMP_GEN_EVENT_IMASK_COMPIFG_OFS (1) /* !< COMPIFG Offset */
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#define COMP_GEN_EVENT_IMASK_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Masks COMPIFG */
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#define COMP_GEN_EVENT_IMASK_COMPIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
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#define COMP_GEN_EVENT_IMASK_COMPIFG_SET ((uint32_t)0x00000002U) /* !< Interrupt will request an interrupt
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service routine and corresponding bit
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in MIS will be set */
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/* COMP_GEN_EVENT_IMASK[COMPINVIFG] Bits */
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#define COMP_GEN_EVENT_IMASK_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
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#define COMP_GEN_EVENT_IMASK_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Masks COMPINVIFG */
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#define COMP_GEN_EVENT_IMASK_COMPINVIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
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#define COMP_GEN_EVENT_IMASK_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< Interrupt will request an interrupt
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service routine and corresponding bit
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in MIS will be set */
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/* COMP_GEN_EVENT_IMASK[OUTRDYIFG] Bits */
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#define COMP_GEN_EVENT_IMASK_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
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#define COMP_GEN_EVENT_IMASK_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Masks OUTRDYIFG */
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#define COMP_GEN_EVENT_IMASK_OUTRDYIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
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#define COMP_GEN_EVENT_IMASK_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< Interrupt will request an interrupt
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service routine and corresponding bit
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in MIS will be set */
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/* COMP_GEN_EVENT_RIS Bits */
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/* COMP_GEN_EVENT_RIS[COMPIFG] Bits */
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#define COMP_GEN_EVENT_RIS_COMPIFG_OFS (1) /* !< COMPIFG Offset */
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#define COMP_GEN_EVENT_RIS_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Raw interrupt status for comparator
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output interrupt flag. The IES bit
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defines the transition of the
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comparator output setting this bit. */
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#define COMP_GEN_EVENT_RIS_COMPIFG_CLR ((uint32_t)0x00000000U) /* !< No interrupt pending */
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#define COMP_GEN_EVENT_RIS_COMPIFG_SET ((uint32_t)0x00000002U) /* !< Interrupt pending */
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/* COMP_GEN_EVENT_RIS[COMPINVIFG] Bits */
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#define COMP_GEN_EVENT_RIS_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
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#define COMP_GEN_EVENT_RIS_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Raw interrupt status for comparator
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output inverted interrupt flag. The
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IES bit defines the transition of the
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comparator output setting this bit. */
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#define COMP_GEN_EVENT_RIS_COMPINVIFG_CLR ((uint32_t)0x00000000U) /* !< No interrupt pending */
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#define COMP_GEN_EVENT_RIS_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< Interrupt pending */
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/* COMP_GEN_EVENT_RIS[OUTRDYIFG] Bits */
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#define COMP_GEN_EVENT_RIS_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
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#define COMP_GEN_EVENT_RIS_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Raw interrupt status for comparator
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output ready interrupt flag. This bit
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is set when the comparator output is
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valid. */
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#define COMP_GEN_EVENT_RIS_OUTRDYIFG_CLR ((uint32_t)0x00000000U) /* !< No interrupt pending */
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#define COMP_GEN_EVENT_RIS_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< Interrupt pending */
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/* COMP_GEN_EVENT_MIS Bits */
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/* COMP_GEN_EVENT_MIS[COMPIFG] Bits */
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#define COMP_GEN_EVENT_MIS_COMPIFG_OFS (1) /* !< COMPIFG Offset */
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#define COMP_GEN_EVENT_MIS_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt status for COMPIFG */
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#define COMP_GEN_EVENT_MIS_COMPIFG_CLR ((uint32_t)0x00000000U) /* !< COMPIFG does not request an
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interrupt service routine */
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#define COMP_GEN_EVENT_MIS_COMPIFG_SET ((uint32_t)0x00000002U) /* !< COMPIFG requests an interrupt
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service routine */
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/* COMP_GEN_EVENT_MIS[COMPINVIFG] Bits */
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#define COMP_GEN_EVENT_MIS_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
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#define COMP_GEN_EVENT_MIS_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Masked interrupt status for
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COMPINVIFG */
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#define COMP_GEN_EVENT_MIS_COMPINVIFG_CLR ((uint32_t)0x00000000U) /* !< COMPINVIFG does not request an
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interrupt service routine */
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#define COMP_GEN_EVENT_MIS_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< COMPINVIFG requests an interrupt
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service routine */
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/* COMP_GEN_EVENT_MIS[OUTRDYIFG] Bits */
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#define COMP_GEN_EVENT_MIS_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
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#define COMP_GEN_EVENT_MIS_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Masked interrupt status for
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OUTRDYIFG */
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#define COMP_GEN_EVENT_MIS_OUTRDYIFG_CLR ((uint32_t)0x00000000U) /* !< OUTRDYIFG does not request an
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interrupt service routine */
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#define COMP_GEN_EVENT_MIS_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< OUTRDYIFG requests an interrupt
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service routine */
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/* COMP_GEN_EVENT_ISET Bits */
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/* COMP_GEN_EVENT_ISET[COMPIFG] Bits */
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#define COMP_GEN_EVENT_ISET_COMPIFG_OFS (1) /* !< COMPIFG Offset */
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#define COMP_GEN_EVENT_ISET_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Sets COMPIFG in RIS register */
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#define COMP_GEN_EVENT_ISET_COMPIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define COMP_GEN_EVENT_ISET_COMPIFG_SET ((uint32_t)0x00000002U) /* !< RIS bit corresponding to COMPIFG is
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set */
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/* COMP_GEN_EVENT_ISET[COMPINVIFG] Bits */
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#define COMP_GEN_EVENT_ISET_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
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#define COMP_GEN_EVENT_ISET_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Sets COMPINVIFG in RIS register */
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#define COMP_GEN_EVENT_ISET_COMPINVIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define COMP_GEN_EVENT_ISET_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< RIS bit corresponding to COMPINVIFG
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is set */
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/* COMP_GEN_EVENT_ISET[OUTRDYIFG] Bits */
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#define COMP_GEN_EVENT_ISET_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
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#define COMP_GEN_EVENT_ISET_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Sets OUTRDYIFG in RIS register */
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#define COMP_GEN_EVENT_ISET_OUTRDYIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define COMP_GEN_EVENT_ISET_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< RIS bit corresponding to OUTRDYIFG
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is set */
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/* COMP_GEN_EVENT_ICLR Bits */
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/* COMP_GEN_EVENT_ICLR[COMPIFG] Bits */
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#define COMP_GEN_EVENT_ICLR_COMPIFG_OFS (1) /* !< COMPIFG Offset */
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#define COMP_GEN_EVENT_ICLR_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Clears COMPIFG in RIS register */
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#define COMP_GEN_EVENT_ICLR_COMPIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define COMP_GEN_EVENT_ICLR_COMPIFG_CLR ((uint32_t)0x00000002U) /* !< RIS bit corresponding to COMPIFG is
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cleared */
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/* COMP_GEN_EVENT_ICLR[COMPINVIFG] Bits */
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#define COMP_GEN_EVENT_ICLR_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
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#define COMP_GEN_EVENT_ICLR_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Clears COMPINVIFG in RIS register */
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#define COMP_GEN_EVENT_ICLR_COMPINVIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define COMP_GEN_EVENT_ICLR_COMPINVIFG_CLR ((uint32_t)0x00000004U) /* !< RIS bit corresponding to COMPINVIFG
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is cleared */
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/* COMP_GEN_EVENT_ICLR[OUTRDYIFG] Bits */
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#define COMP_GEN_EVENT_ICLR_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
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#define COMP_GEN_EVENT_ICLR_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Clears OUTRDYIFG in RIS register */
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#define COMP_GEN_EVENT_ICLR_OUTRDYIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define COMP_GEN_EVENT_ICLR_OUTRDYIFG_CLR ((uint32_t)0x00000008U) /* !< RIS bit corresponding to OUTRDYIFG
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is cleared */
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/* COMP_CPU_INT_IIDX Bits */
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/* COMP_CPU_INT_IIDX[STAT] Bits */
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#define COMP_CPU_INT_IIDX_STAT_OFS (0) /* !< STAT Offset */
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#define COMP_CPU_INT_IIDX_STAT_MASK ((uint32_t)0x00000003U) /* !< Interrupt index status */
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#define COMP_CPU_INT_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No pending interrupt */
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#define COMP_CPU_INT_IIDX_STAT_COMPIFG ((uint32_t)0x00000002U) /* !< Comparator output interrupt */
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#define COMP_CPU_INT_IIDX_STAT_COMPINVIFG ((uint32_t)0x00000003U) /* !< Comparator output inverted
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interrupt */
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#define COMP_CPU_INT_IIDX_STAT_OUTRDYIFG ((uint32_t)0x00000004U) /* !< Comparator output ready interrupt */
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/* COMP_CPU_INT_IMASK Bits */
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/* COMP_CPU_INT_IMASK[COMPIFG] Bits */
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#define COMP_CPU_INT_IMASK_COMPIFG_OFS (1) /* !< COMPIFG Offset */
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#define COMP_CPU_INT_IMASK_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Masks COMPIFG */
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#define COMP_CPU_INT_IMASK_COMPIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
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#define COMP_CPU_INT_IMASK_COMPIFG_SET ((uint32_t)0x00000002U) /* !< Interrupt will request an interrupt
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service routine and corresponding bit
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in MIS will be set */
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/* COMP_CPU_INT_IMASK[COMPINVIFG] Bits */
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#define COMP_CPU_INT_IMASK_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
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#define COMP_CPU_INT_IMASK_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Masks COMPINVIFG */
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#define COMP_CPU_INT_IMASK_COMPINVIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
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#define COMP_CPU_INT_IMASK_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< Interrupt will request an interrupt
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service routine and corresponding bit
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in MIS will be set */
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/* COMP_CPU_INT_IMASK[OUTRDYIFG] Bits */
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#define COMP_CPU_INT_IMASK_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
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#define COMP_CPU_INT_IMASK_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Masks OUTRDYIFG */
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#define COMP_CPU_INT_IMASK_OUTRDYIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
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#define COMP_CPU_INT_IMASK_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< Interrupt will request an interrupt
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service routine and corresponding bit
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in MIS will be set */
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/* COMP_CPU_INT_RIS Bits */
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/* COMP_CPU_INT_RIS[COMPIFG] Bits */
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#define COMP_CPU_INT_RIS_COMPIFG_OFS (1) /* !< COMPIFG Offset */
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#define COMP_CPU_INT_RIS_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Raw interrupt status for comparator
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output interrupt flag. The IES bit
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defines the transition of the
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comparator output setting this bit. */
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#define COMP_CPU_INT_RIS_COMPIFG_CLR ((uint32_t)0x00000000U) /* !< No interrupt pending */
|
|
#define COMP_CPU_INT_RIS_COMPIFG_SET ((uint32_t)0x00000002U) /* !< Interrupt pending */
|
|
/* COMP_CPU_INT_RIS[COMPINVIFG] Bits */
|
|
#define COMP_CPU_INT_RIS_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
|
|
#define COMP_CPU_INT_RIS_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Raw interrupt status for comparator
|
|
output inverted interrupt flag. The
|
|
IES bit defines the transition of the
|
|
comparator output setting this bit. */
|
|
#define COMP_CPU_INT_RIS_COMPINVIFG_CLR ((uint32_t)0x00000000U) /* !< No interrupt pending */
|
|
#define COMP_CPU_INT_RIS_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< Interrupt pending */
|
|
/* COMP_CPU_INT_RIS[OUTRDYIFG] Bits */
|
|
#define COMP_CPU_INT_RIS_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
|
|
#define COMP_CPU_INT_RIS_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Raw interrupt status for comparator
|
|
output ready interrupt flag. This bit
|
|
is set when the comparator output is
|
|
valid. */
|
|
#define COMP_CPU_INT_RIS_OUTRDYIFG_CLR ((uint32_t)0x00000000U) /* !< No interrupt pending */
|
|
#define COMP_CPU_INT_RIS_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< Interrupt pending */
|
|
|
|
/* COMP_CPU_INT_MIS Bits */
|
|
/* COMP_CPU_INT_MIS[COMPIFG] Bits */
|
|
#define COMP_CPU_INT_MIS_COMPIFG_OFS (1) /* !< COMPIFG Offset */
|
|
#define COMP_CPU_INT_MIS_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt status for COMPIFG */
|
|
#define COMP_CPU_INT_MIS_COMPIFG_CLR ((uint32_t)0x00000000U) /* !< COMPIFG does not request an
|
|
interrupt service routine */
|
|
#define COMP_CPU_INT_MIS_COMPIFG_SET ((uint32_t)0x00000002U) /* !< COMPIFG requests an interrupt
|
|
service routine */
|
|
/* COMP_CPU_INT_MIS[COMPINVIFG] Bits */
|
|
#define COMP_CPU_INT_MIS_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
|
|
#define COMP_CPU_INT_MIS_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Masked interrupt status for
|
|
COMPINVIFG */
|
|
#define COMP_CPU_INT_MIS_COMPINVIFG_CLR ((uint32_t)0x00000000U) /* !< COMPINVIFG does not request an
|
|
interrupt service routine */
|
|
#define COMP_CPU_INT_MIS_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< COMPINVIFG requests an interrupt
|
|
service routine */
|
|
/* COMP_CPU_INT_MIS[OUTRDYIFG] Bits */
|
|
#define COMP_CPU_INT_MIS_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
|
|
#define COMP_CPU_INT_MIS_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Masked interrupt status for
|
|
OUTRDYIFG */
|
|
#define COMP_CPU_INT_MIS_OUTRDYIFG_CLR ((uint32_t)0x00000000U) /* !< OUTRDYIFG does not request an
|
|
interrupt service routine */
|
|
#define COMP_CPU_INT_MIS_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< OUTRDYIFG requests an interrupt
|
|
service routine */
|
|
|
|
/* COMP_CPU_INT_ISET Bits */
|
|
/* COMP_CPU_INT_ISET[COMPIFG] Bits */
|
|
#define COMP_CPU_INT_ISET_COMPIFG_OFS (1) /* !< COMPIFG Offset */
|
|
#define COMP_CPU_INT_ISET_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Sets COMPIFG in RIS register */
|
|
#define COMP_CPU_INT_ISET_COMPIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
|
|
#define COMP_CPU_INT_ISET_COMPIFG_SET ((uint32_t)0x00000002U) /* !< RIS bit corresponding to COMPIFG is
|
|
set */
|
|
/* COMP_CPU_INT_ISET[COMPINVIFG] Bits */
|
|
#define COMP_CPU_INT_ISET_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
|
|
#define COMP_CPU_INT_ISET_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Sets COMPINVIFG in RIS register */
|
|
#define COMP_CPU_INT_ISET_COMPINVIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
|
|
#define COMP_CPU_INT_ISET_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< RIS bit corresponding to COMPINVIFG
|
|
is set */
|
|
/* COMP_CPU_INT_ISET[OUTRDYIFG] Bits */
|
|
#define COMP_CPU_INT_ISET_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
|
|
#define COMP_CPU_INT_ISET_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Sets OUTRDYIFG in RIS register */
|
|
#define COMP_CPU_INT_ISET_OUTRDYIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
|
|
#define COMP_CPU_INT_ISET_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< RIS bit corresponding to OUTRDYIFG
|
|
is set */
|
|
|
|
/* COMP_CPU_INT_ICLR Bits */
|
|
/* COMP_CPU_INT_ICLR[COMPIFG] Bits */
|
|
#define COMP_CPU_INT_ICLR_COMPIFG_OFS (1) /* !< COMPIFG Offset */
|
|
#define COMP_CPU_INT_ICLR_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Clears COMPIFG in RIS register */
|
|
#define COMP_CPU_INT_ICLR_COMPIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
|
|
#define COMP_CPU_INT_ICLR_COMPIFG_CLR ((uint32_t)0x00000002U) /* !< RIS bit corresponding to COMPIFG is
|
|
cleared */
|
|
/* COMP_CPU_INT_ICLR[COMPINVIFG] Bits */
|
|
#define COMP_CPU_INT_ICLR_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
|
|
#define COMP_CPU_INT_ICLR_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Clears COMPINVIFG in RIS register */
|
|
#define COMP_CPU_INT_ICLR_COMPINVIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
|
|
#define COMP_CPU_INT_ICLR_COMPINVIFG_CLR ((uint32_t)0x00000004U) /* !< RIS bit corresponding to COMPINVIFG
|
|
is cleared */
|
|
/* COMP_CPU_INT_ICLR[OUTRDYIFG] Bits */
|
|
#define COMP_CPU_INT_ICLR_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
|
|
#define COMP_CPU_INT_ICLR_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Clears OUTRDYIFG in RIS register */
|
|
#define COMP_CPU_INT_ICLR_OUTRDYIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
|
|
#define COMP_CPU_INT_ICLR_OUTRDYIFG_CLR ((uint32_t)0x00000008U) /* !< RIS bit corresponding to OUTRDYIFG
|
|
is cleared */
|
|
|
|
/* COMP_PWREN Bits */
|
|
/* COMP_PWREN[ENABLE] Bits */
|
|
#define COMP_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */
|
|
#define COMP_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */
|
|
#define COMP_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */
|
|
#define COMP_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */
|
|
/* COMP_PWREN[KEY] Bits */
|
|
#define COMP_PWREN_KEY_OFS (24) /* !< KEY Offset */
|
|
#define COMP_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */
|
|
#define COMP_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this
|
|
register */
|
|
|
|
/* COMP_RSTCTL Bits */
|
|
/* COMP_RSTCTL[RESETSTKYCLR] Bits */
|
|
#define COMP_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */
|
|
#define COMP_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT
|
|
register */
|
|
#define COMP_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
|
|
#define COMP_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */
|
|
/* COMP_RSTCTL[RESETASSERT] Bits */
|
|
#define COMP_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */
|
|
#define COMP_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */
|
|
#define COMP_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
|
|
#define COMP_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */
|
|
/* COMP_RSTCTL[KEY] Bits */
|
|
#define COMP_RSTCTL_KEY_OFS (24) /* !< KEY Offset */
|
|
#define COMP_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */
|
|
#define COMP_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this
|
|
register */
|
|
|
|
/* COMP_CLKCFG Bits */
|
|
/* COMP_CLKCFG[KEY] Bits */
|
|
#define COMP_CLKCFG_KEY_OFS (24) /* !< KEY Offset */
|
|
#define COMP_CLKCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to Allow State Change -- 0xA9 */
|
|
#define COMP_CLKCFG_KEY_UNLOCK ((uint32_t)0xA9000000U) /* !< Key value to be used in writing to
|
|
this register for the write to take
|
|
effect. */
|
|
/* COMP_CLKCFG[BLOCKASYNC] Bits */
|
|
#define COMP_CLKCFG_BLOCKASYNC_OFS (8) /* !< BLOCKASYNC Offset */
|
|
#define COMP_CLKCFG_BLOCKASYNC_MASK ((uint32_t)0x00000100U) /* !< Async Clock Request is blocked from
|
|
starting SYSOSC or forcing bus clock
|
|
to 32MHz */
|
|
#define COMP_CLKCFG_BLOCKASYNC_DISABLE ((uint32_t)0x00000000U) /* !< disable COMP to request SYSOSC */
|
|
#define COMP_CLKCFG_BLOCKASYNC_ENABLE ((uint32_t)0x00000100U) /* !< enable COMP to request SYSOSC */
|
|
|
|
/* COMP_GPRCM_STAT Bits */
|
|
/* COMP_GPRCM_STAT[RESETSTKY] Bits */
|
|
#define COMP_GPRCM_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */
|
|
#define COMP_GPRCM_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the
|
|
peripheral was reset, since this bit
|
|
was cleared by RESETSTKYCLR in the
|
|
RSTCTL register */
|
|
#define COMP_GPRCM_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset
|
|
since this bit was last cleared by
|
|
RESETSTKYCLR in the RSTCTL register */
|
|
#define COMP_GPRCM_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the
|
|
last bit clear */
|
|
|
|
/* COMP_FSUB_0 Bits */
|
|
/* COMP_FSUB_0[CHANID] Bits */
|
|
#define COMP_FSUB_0_CHANID_OFS (0) /* !< CHANID Offset */
|
|
#define COMP_FSUB_0_CHANID_MASK ((uint32_t)0x00007FFFU) /* !< 0 = disconnected. 1-15 = connected
|
|
to channelID = CHANID. */
|
|
#define COMP_FSUB_0_CHANID_MNIMUM ((uint32_t)0x00000000U) /* !< 0 is an allowed value, signifying
|
|
that the event is unconnected */
|
|
#define COMP_FSUB_0_CHANID_UNCONNECTED ((uint32_t)0x00000000U) /* !< A value of 0 specifies that the
|
|
event is not connected */
|
|
#define COMP_FSUB_0_CHANID_MAXIMUM ((uint32_t)0x0000000FU) /* !< Consult your device datasheet as
|
|
the actual allowed maximum may be
|
|
less than 15. */
|
|
|
|
/* COMP_FSUB_1 Bits */
|
|
/* COMP_FSUB_1[CHANID] Bits */
|
|
#define COMP_FSUB_1_CHANID_OFS (0) /* !< CHANID Offset */
|
|
#define COMP_FSUB_1_CHANID_MASK ((uint32_t)0x00007FFFU) /* !< 0 = disconnected. 1-15 = connected
|
|
to channelID = CHANID. */
|
|
#define COMP_FSUB_1_CHANID_MNIMUM ((uint32_t)0x00000000U) /* !< 0 is an allowed value, signifying
|
|
that the event is unconnected */
|
|
#define COMP_FSUB_1_CHANID_UNCONNECTED ((uint32_t)0x00000000U) /* !< A value of 0 specifies that the
|
|
event is not connected */
|
|
#define COMP_FSUB_1_CHANID_MAXIMUM ((uint32_t)0x0000000FU) /* !< Consult your device datasheet as
|
|
the actual allowed maximum may be
|
|
less than 15. */
|
|
|
|
/* COMP_FPUB_1 Bits */
|
|
/* COMP_FPUB_1[CHANID] Bits */
|
|
#define COMP_FPUB_1_CHANID_OFS (0) /* !< CHANID Offset */
|
|
#define COMP_FPUB_1_CHANID_MASK ((uint32_t)0x00007FFFU) /* !< 0 = disconnected. 1-15 = connected
|
|
to channelID = CHANID. */
|
|
#define COMP_FPUB_1_CHANID_MNIMUM ((uint32_t)0x00000000U) /* !< 0 is an allowed value, signifying
|
|
that the event is unconnected */
|
|
#define COMP_FPUB_1_CHANID_UNCONNECTED ((uint32_t)0x00000000U) /* !< A value of 0 specifies that the
|
|
event is not connected */
|
|
#define COMP_FPUB_1_CHANID_MAXIMUM ((uint32_t)0x0000000FU) /* !< Consult your device datasheet as
|
|
the actual allowed maximum may be
|
|
less than 15. */
|
|
|
|
/* COMP_EVT_MODE Bits */
|
|
/* COMP_EVT_MODE[INT0_CFG] Bits */
|
|
#define COMP_EVT_MODE_INT0_CFG_OFS (0) /* !< INT0_CFG Offset */
|
|
#define COMP_EVT_MODE_INT0_CFG_MASK ((uint32_t)0x00000003U) /* !< Event line mode select for event
|
|
corresponding to CPU_INT */
|
|
#define COMP_EVT_MODE_INT0_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
|
|
disabled. */
|
|
#define COMP_EVT_MODE_INT0_CFG_SOFTWARE ((uint32_t)0x00000001U) /* !< Event handled by software. Software
|
|
must clear the associated RIS flag. */
|
|
#define COMP_EVT_MODE_INT0_CFG_HARDWARE ((uint32_t)0x00000002U) /* !< Event handled by hardware. The
|
|
hardware (another module) clears
|
|
automatically the associated RIS
|
|
flag. */
|
|
/* COMP_EVT_MODE[EVT1_CFG] Bits */
|
|
#define COMP_EVT_MODE_EVT1_CFG_OFS (2) /* !< EVT1_CFG Offset */
|
|
#define COMP_EVT_MODE_EVT1_CFG_MASK ((uint32_t)0x0000000CU) /* !< Event line mode select for event
|
|
corresponding to GEN_EVENT */
|
|
#define COMP_EVT_MODE_EVT1_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
|
|
disabled. */
|
|
#define COMP_EVT_MODE_EVT1_CFG_SOFTWARE ((uint32_t)0x00000004U) /* !< Event handled by software. Software
|
|
must clear the associated RIS flag. */
|
|
#define COMP_EVT_MODE_EVT1_CFG_HARDWARE ((uint32_t)0x00000008U) /* !< Event handled by hardware. The
|
|
hardware (another module) clears
|
|
automatically the associated RIS
|
|
flag. */
|
|
|
|
/* COMP_DESC Bits */
|
|
/* COMP_DESC[MINREV] Bits */
|
|
#define COMP_DESC_MINREV_OFS (0) /* !< MINREV Offset */
|
|
#define COMP_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */
|
|
/* COMP_DESC[MAJREV] Bits */
|
|
#define COMP_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */
|
|
#define COMP_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */
|
|
/* COMP_DESC[FEATUREVER] Bits */
|
|
#define COMP_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */
|
|
#define COMP_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module
|
|
*instance* */
|
|
/* COMP_DESC[MODULEID] Bits */
|
|
#define COMP_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */
|
|
#define COMP_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module identification contains a
|
|
unique peripheral identification
|
|
number. The assignments are
|
|
maintained in a central database for
|
|
all of the platform modules to ensure
|
|
uniqueness. */
|
|
|
|
/* COMP_CTL0 Bits */
|
|
/* COMP_CTL0[IPSEL] Bits */
|
|
#define COMP_CTL0_IPSEL_OFS (0) /* !< IPSEL Offset */
|
|
#define COMP_CTL0_IPSEL_MASK ((uint32_t)0x00000007U) /* !< Channel input selected for the
|
|
positive terminal of the comparator
|
|
if IPEN is set to 1. */
|
|
#define COMP_CTL0_IPSEL_CH_0 ((uint32_t)0x00000000U) /* !< Channel 0 selected */
|
|
#define COMP_CTL0_IPSEL_CH_1 ((uint32_t)0x00000001U) /* !< Channel 1 selected */
|
|
#define COMP_CTL0_IPSEL_CH_2 ((uint32_t)0x00000002U) /* !< Channel 2 selected */
|
|
#define COMP_CTL0_IPSEL_CH_3 ((uint32_t)0x00000003U) /* !< Channel 3 selected */
|
|
#define COMP_CTL0_IPSEL_CH_4 ((uint32_t)0x00000004U) /* !< Channel 4 selected */
|
|
#define COMP_CTL0_IPSEL_CH_5 ((uint32_t)0x00000005U) /* !< Channel 5 selected */
|
|
#define COMP_CTL0_IPSEL_CH_6 ((uint32_t)0x00000006U) /* !< Channel 6 selected */
|
|
#define COMP_CTL0_IPSEL_CH_7 ((uint32_t)0x00000007U) /* !< Channel 7 selected */
|
|
/* COMP_CTL0[IPEN] Bits */
|
|
#define COMP_CTL0_IPEN_OFS (15) /* !< IPEN Offset */
|
|
#define COMP_CTL0_IPEN_MASK ((uint32_t)0x00008000U) /* !< Channel input enable for the
|
|
positive terminal of the comparator. */
|
|
#define COMP_CTL0_IPEN_DISABLE ((uint32_t)0x00000000U) /* !< Selected analog input channel for
|
|
positive terminal is disabled */
|
|
#define COMP_CTL0_IPEN_ENABLE ((uint32_t)0x00008000U) /* !< Selected analog input channel for
|
|
positive terminal is enabled */
|
|
/* COMP_CTL0[IMEN] Bits */
|
|
#define COMP_CTL0_IMEN_OFS (31) /* !< IMEN Offset */
|
|
#define COMP_CTL0_IMEN_MASK ((uint32_t)0x80000000U) /* !< Channel input enable for the
|
|
negative terminal of the comparator. */
|
|
#define COMP_CTL0_IMEN_DISABLE ((uint32_t)0x00000000U) /* !< Selected analog input channel for
|
|
negative terminal is disabled */
|
|
#define COMP_CTL0_IMEN_ENABLE ((uint32_t)0x80000000U) /* !< Selected analog input channel for
|
|
negative terminal is enabled */
|
|
/* COMP_CTL0[IMSEL] Bits */
|
|
#define COMP_CTL0_IMSEL_OFS (16) /* !< IMSEL Offset */
|
|
#define COMP_CTL0_IMSEL_MASK ((uint32_t)0x00070000U) /* !< Channel input selected for the
|
|
negative terminal of the comparator
|
|
if IMEN is set to 1. */
|
|
#define COMP_CTL0_IMSEL_CH_0 ((uint32_t)0x00000000U) /* !< Channel 0 selected */
|
|
#define COMP_CTL0_IMSEL_CH_1 ((uint32_t)0x00010000U) /* !< Channel 1 selected */
|
|
#define COMP_CTL0_IMSEL_CH_2 ((uint32_t)0x00020000U) /* !< Channel 2 selected */
|
|
#define COMP_CTL0_IMSEL_CH_3 ((uint32_t)0x00030000U) /* !< Channel 3 selected */
|
|
#define COMP_CTL0_IMSEL_CH_4 ((uint32_t)0x00040000U) /* !< Channel 4 selected */
|
|
#define COMP_CTL0_IMSEL_CH_5 ((uint32_t)0x00050000U) /* !< Channel 5 selected */
|
|
#define COMP_CTL0_IMSEL_CH_6 ((uint32_t)0x00060000U) /* !< Channel 6 selected */
|
|
#define COMP_CTL0_IMSEL_CH_7 ((uint32_t)0x00070000U) /* !< Channel 7 selected */
|
|
|
|
/* COMP_CTL1 Bits */
|
|
/* COMP_CTL1[ENABLE] Bits */
|
|
#define COMP_CTL1_ENABLE_OFS (0) /* !< ENABLE Offset */
|
|
#define COMP_CTL1_ENABLE_MASK ((uint32_t)0x00000001U) /* !< This bit turns on the comparator.
|
|
When the comparator is turned off it
|
|
consumes no power. */
|
|
#define COMP_CTL1_ENABLE_OFF ((uint32_t)0x00000000U) /* !< Comparator is off */
|
|
#define COMP_CTL1_ENABLE_ON ((uint32_t)0x00000001U) /* !< Comparator is on */
|
|
/* COMP_CTL1[MODE] Bits */
|
|
#define COMP_CTL1_MODE_OFS (1) /* !< MODE Offset */
|
|
#define COMP_CTL1_MODE_MASK ((uint32_t)0x00000002U) /* !< This bit selects the comparator
|
|
operating mode. */
|
|
#define COMP_CTL1_MODE_FAST ((uint32_t)0x00000000U) /* !< Comparator is in fast mode */
|
|
#define COMP_CTL1_MODE_ULP ((uint32_t)0x00000002U) /* !< Comparator is in ultra-low power
|
|
mode */
|
|
/* COMP_CTL1[EXCH] Bits */
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#define COMP_CTL1_EXCH_OFS (2) /* !< EXCH Offset */
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#define COMP_CTL1_EXCH_MASK ((uint32_t)0x00000004U) /* !< This bit exchanges the comparator
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inputs and inverts the comparator
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output. */
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#define COMP_CTL1_EXCH_NO_EXC ((uint32_t)0x00000000U) /* !< Comparator inputs not exchanged and
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output not inverted */
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#define COMP_CTL1_EXCH_EXC ((uint32_t)0x00000004U) /* !< Comparator inputs exchanged and
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output inverted */
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/* COMP_CTL1[SHORT] Bits */
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#define COMP_CTL1_SHORT_OFS (3) /* !< SHORT Offset */
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#define COMP_CTL1_SHORT_MASK ((uint32_t)0x00000008U) /* !< This bit shorts the positive and
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negative input terminals of the
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comparator. */
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#define COMP_CTL1_SHORT_NO_SHT ((uint32_t)0x00000000U) /* !< Comparator positive and negative
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input terminals are not shorted */
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#define COMP_CTL1_SHORT_SHT ((uint32_t)0x00000008U) /* !< Comparator positive and negative
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input terminals are shorted */
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/* COMP_CTL1[IES] Bits */
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#define COMP_CTL1_IES_OFS (4) /* !< IES Offset */
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#define COMP_CTL1_IES_MASK ((uint32_t)0x00000010U) /* !< This bit selected the interrupt
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edge for COMPIFG and COMPINVIFG. */
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#define COMP_CTL1_IES_RISING ((uint32_t)0x00000000U) /* !< Rising edge sets COMPIFG and
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falling edge sets COMPINVIFG */
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#define COMP_CTL1_IES_FALLING ((uint32_t)0x00000010U) /* !< Falling edge sets COMPIFG and
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rising edge sets COMPINVIFG */
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/* COMP_CTL1[HYST] Bits */
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#define COMP_CTL1_HYST_OFS (5) /* !< HYST Offset */
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#define COMP_CTL1_HYST_MASK ((uint32_t)0x00000060U) /* !< These bits select the hysteresis
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setting of the comparator. */
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#define COMP_CTL1_HYST_NO_HYS ((uint32_t)0x00000000U) /* !< No hysteresis */
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#define COMP_CTL1_HYST_LOW_HYS ((uint32_t)0x00000020U) /* !< Low hysteresis, typical 10mV */
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#define COMP_CTL1_HYST_MED_HYS ((uint32_t)0x00000040U) /* !< Medium hysteresis, typical 20mV */
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#define COMP_CTL1_HYST_HIGH_HYS ((uint32_t)0x00000060U) /* !< High hysteresis, typical 30mV */
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/* COMP_CTL1[OUTPOL] Bits */
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#define COMP_CTL1_OUTPOL_OFS (7) /* !< OUTPOL Offset */
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#define COMP_CTL1_OUTPOL_MASK ((uint32_t)0x00000080U) /* !< This bit selects the comparator
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output polarity. */
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#define COMP_CTL1_OUTPOL_NON_INV ((uint32_t)0x00000000U) /* !< Comparator output is non-inverted */
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#define COMP_CTL1_OUTPOL_INV ((uint32_t)0x00000080U) /* !< Comparator output is inverted */
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/* COMP_CTL1[FLTEN] Bits */
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#define COMP_CTL1_FLTEN_OFS (8) /* !< FLTEN Offset */
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#define COMP_CTL1_FLTEN_MASK ((uint32_t)0x00000100U) /* !< This bit enables the analog filter
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at comparator output. */
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#define COMP_CTL1_FLTEN_DISABLE ((uint32_t)0x00000000U) /* !< Comparator output filter is
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disabled */
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#define COMP_CTL1_FLTEN_ENABLE ((uint32_t)0x00000100U) /* !< Comparator output filter is enabled */
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/* COMP_CTL1[FLTDLY] Bits */
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#define COMP_CTL1_FLTDLY_OFS (9) /* !< FLTDLY Offset */
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#define COMP_CTL1_FLTDLY_MASK ((uint32_t)0x00000600U) /* !< These bits select the comparator
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output filter delay. See the
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device-specific data sheet for
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specific values on comparator
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propagation delay for different
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filter delay settings. */
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#define COMP_CTL1_FLTDLY_DLY_0 ((uint32_t)0x00000000U) /* !< Typical filter delay of 70 ns */
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#define COMP_CTL1_FLTDLY_DLY_1 ((uint32_t)0x00000200U) /* !< Typical filter delay of 500 ns */
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#define COMP_CTL1_FLTDLY_DLY_2 ((uint32_t)0x00000400U) /* !< Typical filter delay of 1200 ns */
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#define COMP_CTL1_FLTDLY_DLY_3 ((uint32_t)0x00000600U) /* !< Typical filter delay of 2700 ns */
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/* COMP_CTL1[WINCOMPEN] Bits */
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#define COMP_CTL1_WINCOMPEN_OFS (12) /* !< WINCOMPEN Offset */
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#define COMP_CTL1_WINCOMPEN_MASK ((uint32_t)0x00001000U) /* !< This bit enables window comparator
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operation of comparator. */
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#define COMP_CTL1_WINCOMPEN_OFF ((uint32_t)0x00000000U) /* !< window comparator is disable */
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#define COMP_CTL1_WINCOMPEN_ON ((uint32_t)0x00001000U) /* !< window comparator is enable */
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/* COMP_CTL2 Bits */
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/* COMP_CTL2[REFMODE] Bits */
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#define COMP_CTL2_REFMODE_OFS (0) /* !< REFMODE Offset */
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#define COMP_CTL2_REFMODE_MASK ((uint32_t)0x00000001U) /* !< This bit requests ULP_REF bandgap
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operation in fast mode(static) or low
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power mode (sampled). The local
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reference buffer and 8-bit DAC inside
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comparator module are also configured
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accordingly. Fast mode operation
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offers higher accuracy but consumes
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higher current. Low power operation
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consumes lower current but with
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relaxed reference voltage accuracy.
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Comparator requests for reference
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voltage from ULP_REF only when REFLVL
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> 0. */
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#define COMP_CTL2_REFMODE_STATIC ((uint32_t)0x00000000U) /* !< ULP_REF bandgap, local reference
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buffer and 8-bit DAC inside
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comparator operate in static mode. */
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#define COMP_CTL2_REFMODE_SAMPLED ((uint32_t)0x00000001U) /* !< ULP_REF bandgap, local reference
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buffer and 8-bit DAC inside
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comparator operate in sampled mode. */
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/* COMP_CTL2[REFSRC] Bits */
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#define COMP_CTL2_REFSRC_OFS (3) /* !< REFSRC Offset */
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#define COMP_CTL2_REFSRC_MASK ((uint32_t)0x00000038U) /* !< These bits select the reference
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source for the comparator. */
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#define COMP_CTL2_REFSRC_OFF ((uint32_t)0x00000000U) /* !< Reference voltage generator is
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disabled (local reference buffer as
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well as DAC). */
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#define COMP_CTL2_REFSRC_VDDA_DAC ((uint32_t)0x00000008U) /* !< VDDA selected as the reference
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source to DAC and DAC output applied
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as reference to comparator. */
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#define COMP_CTL2_REFSRC_VREF_DAC ((uint32_t)0x00000010U) /* !< VREF selected as reference to DAC
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and DAC output applied as reference
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to comparator. */
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#define COMP_CTL2_REFSRC_VREF ((uint32_t)0x00000018U) /* !< In devices where internal VREF is
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buffered and hookedup to extrernal
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VREF pin, VREF applied as reference
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to comparator. DAC is switched off.
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Note: In LEGO_A3, DAC is turned off
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in this selection, in other deviced
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DAC is kept on. */
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#define COMP_CTL2_REFSRC_VDDA ((uint32_t)0x00000028U) /* !< VDDA is used as comparator
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reference. Note: In LEGO_A3, DAC is
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turned off in this selection, in
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other deviced DAC is kept on. */
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#define COMP_CTL2_REFSRC_INTVREF_DAC ((uint32_t)0x00000030U) /* !< Internal reference selected as the
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reference source to DAC and DAC
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output applied as reference to
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comparator. */
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#define COMP_CTL2_REFSRC_INTVREF ((uint32_t)0x00000038U) /* !< Internal VREF is used as the source
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of comparator. Not all devices will
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have this option. */
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/* COMP_CTL2[REFSEL] Bits */
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#define COMP_CTL2_REFSEL_OFS (7) /* !< REFSEL Offset */
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#define COMP_CTL2_REFSEL_MASK ((uint32_t)0x00000080U) /* !< This bit selects if the selected
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reference voltage is applied to
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positive or negative terminal of the
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comparator. */
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#define COMP_CTL2_REFSEL_POSITIVE ((uint32_t)0x00000000U) /* !< If EXCH bit is 0, the selected
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reference is applied to positive
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terminal. If EXCH bit is 1, the
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selected reference is applied to
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negative terminal. */
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#define COMP_CTL2_REFSEL_NEGATIVE ((uint32_t)0x00000080U) /* !< If EXCH bit is 0, the selected
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reference is applied to negative
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terminal. If EXCH bit is 1, the
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selected reference is applied to
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positive terminal. */
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/* COMP_CTL2[DACCTL] Bits */
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#define COMP_CTL2_DACCTL_OFS (16) /* !< DACCTL Offset */
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#define COMP_CTL2_DACCTL_MASK ((uint32_t)0x00010000U) /* !< This bit determines if the
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comparator output or DACSW bit
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controls the selection between
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DACCODE0 and DACCODE1. */
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#define COMP_CTL2_DACCTL_COMPOUT_SEL ((uint32_t)0x00000000U) /* !< Comparator output controls
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selection between DACCODE0 and
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DACCODE1 */
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#define COMP_CTL2_DACCTL_DACSW_SEL ((uint32_t)0x00010000U) /* !< DACSW bit controls selection
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between DACCODE0 and DACCODE1 */
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/* COMP_CTL2[DACSW] Bits */
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#define COMP_CTL2_DACSW_OFS (17) /* !< DACSW Offset */
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#define COMP_CTL2_DACSW_MASK ((uint32_t)0x00020000U) /* !< This bit selects between DACCODE0
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and DACCODE1 to 8-bit DAC when DACCTL
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bit is 1. */
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#define COMP_CTL2_DACSW_DACCODE0_SEL ((uint32_t)0x00000000U) /* !< DACCODE0 selected for 8-bit DAC */
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#define COMP_CTL2_DACSW_DACCODE1_SEL ((uint32_t)0x00020000U) /* !< DACCODE1 selected for 8-bit DAC */
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/* COMP_CTL2[BLANKSRC] Bits */
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#define COMP_CTL2_BLANKSRC_OFS (8) /* !< BLANKSRC Offset */
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#define COMP_CTL2_BLANKSRC_MASK ((uint32_t)0x00000700U) /* !< These bits select the blanking
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source for the comparator. */
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#define COMP_CTL2_BLANKSRC_DISABLE ((uint32_t)0x00000000U) /* !< Blanking source disabled */
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#define COMP_CTL2_BLANKSRC_BLANKSRC1 ((uint32_t)0x00000100U) /* !< Select Blanking Source 1 */
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#define COMP_CTL2_BLANKSRC_BLANKSRC2 ((uint32_t)0x00000200U) /* !< Select Blanking Source 2 */
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#define COMP_CTL2_BLANKSRC_BLANKSRC3 ((uint32_t)0x00000300U) /* !< Select Blanking Source 3 */
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#define COMP_CTL2_BLANKSRC_BLANKSRC4 ((uint32_t)0x00000400U) /* !< Select Blanking Source 4 */
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#define COMP_CTL2_BLANKSRC_BLANKSRC5 ((uint32_t)0x00000500U) /* !< Select Blanking Source 5 */
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#define COMP_CTL2_BLANKSRC_BLANKSRC6 ((uint32_t)0x00000600U) /* !< Select Blanking Source 6 */
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/* COMP_CTL2[SAMPMODE] Bits */
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#define COMP_CTL2_SAMPMODE_OFS (24) /* !< SAMPMODE Offset */
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#define COMP_CTL2_SAMPMODE_MASK ((uint32_t)0x01000000U) /* !< Enable sampled mode of comparator. */
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#define COMP_CTL2_SAMPMODE_DISABLE ((uint32_t)0x00000000U) /* !< Sampled mode disabled */
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#define COMP_CTL2_SAMPMODE_ENABLE ((uint32_t)0x01000000U) /* !< Sampled mode enabled */
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/* COMP_CTL3 Bits */
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/* COMP_CTL3[DACCODE0] Bits */
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#define COMP_CTL3_DACCODE0_OFS (0) /* !< DACCODE0 Offset */
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#define COMP_CTL3_DACCODE0_MASK ((uint32_t)0x000000FFU) /* !< This is the first 8-bit DAC code.
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When the DAC code is 0x0 the DAC
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output will be 0 V. When the DAC code
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is 0xFF the DAC output will be
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selected reference voltage x 255/256. */
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#define COMP_CTL3_DACCODE0_MNIMUM ((uint32_t)0x00000000U) /* !< Minimum DAC code value */
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#define COMP_CTL3_DACCODE0_MAXIMUM ((uint32_t)0x000000FFU) /* !< Minimum DAC code value */
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/* COMP_CTL3[DACCODE1] Bits */
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#define COMP_CTL3_DACCODE1_OFS (16) /* !< DACCODE1 Offset */
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#define COMP_CTL3_DACCODE1_MASK ((uint32_t)0x00FF0000U) /* !< This is the second 8-bit DAC code.
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When the DAC code is 0x0 the DAC
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output will be 0 V. When the DAC code
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is 0xFF the DAC output will be
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selected reference voltage x 255/256. */
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#define COMP_CTL3_DACCODE1_MNIMUM ((uint32_t)0x00000000U) /* !< Minimum DAC code value */
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#define COMP_CTL3_DACCODE1_MAXIMUM ((uint32_t)0x00FF0000U) /* !< Minimum DAC code value */
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/* COMP_STAT Bits */
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/* COMP_STAT[OUT] Bits */
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#define COMP_STAT_OUT_OFS (0) /* !< OUT Offset */
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#define COMP_STAT_OUT_MASK ((uint32_t)0x00000001U) /* !< This bit reflects the value of the
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comparator output. Writing to this
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bit has no effect on the comparator
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output. */
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#define COMP_STAT_OUT_LOW ((uint32_t)0x00000000U) /* !< Comparator output is low */
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#define COMP_STAT_OUT_HIGH ((uint32_t)0x00000001U) /* !< Comparator output is high */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ti_devices_msp_peripherals_hw_comp__include */
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