SkyLi
552 lines
45 KiB
C
552 lines
45 KiB
C
/*****************************************************************************
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Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the
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distribution.
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Neither the name of Texas Instruments Incorporated nor the names of
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its contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#ifndef ti_devices_msp_peripherals_hw_trng__include
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#define ti_devices_msp_peripherals_hw_trng__include
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/* Filename: hw_trng.h */
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/* Revised: 2023-06-13 16:12:38 */
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/* Revision: f9b237fa1b82e8166ce3ead25b505b784578352a */
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#ifndef __CORTEX_M
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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#endif
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/* Use standard integer types with explicit width */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/******************************************************************************
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* TRNG Registers
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******************************************************************************/
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#define TRNG_CPU_INT_OFS ((uint32_t)0x00001020U)
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#define TRNG_GPRCM_OFS ((uint32_t)0x00000800U)
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/** @addtogroup TRNG_CPU_INT
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@{
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*/
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typedef struct {
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__I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */
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uint32_t RESERVED0;
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__IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */
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uint32_t RESERVED1;
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__I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */
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uint32_t RESERVED2;
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__I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */
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uint32_t RESERVED3;
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__O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */
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uint32_t RESERVED4;
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__O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */
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} TRNG_CPU_INT_Regs;
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/*@}*/ /* end of group TRNG_CPU_INT */
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/** @addtogroup TRNG_GPRCM
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@{
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*/
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typedef struct {
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__IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */
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__O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */
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uint32_t RESERVED0[3];
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__I uint32_t STAT; /* !< (@ 0x00000814) Status Register */
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} TRNG_GPRCM_Regs;
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/*@}*/ /* end of group TRNG_GPRCM */
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/** @addtogroup TRNG
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@{
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*/
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typedef struct {
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uint32_t RESERVED0[512];
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TRNG_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */
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uint32_t RESERVED1[514];
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TRNG_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */
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uint32_t RESERVED2[44];
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__I uint32_t DESC; /* !< (@ 0x000010FC) Module descriptions */
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__IO uint32_t CTL; /* !< (@ 0x00001100) Controls the command and decimation rate */
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__I uint32_t STAT; /* !< (@ 0x00001104) Status register that informs health test results
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and last issued command */
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__I uint32_t DATA_CAPTURE; /* !< (@ 0x00001108) Captured word buffer of RNG data */
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__I uint32_t TEST_RESULTS; /* !< (@ 0x0000110C) Test results from TEST_ANA and TEST_DIG */
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__IO uint32_t CLKDIVIDE; /* !< (@ 0x00001110) Clock Divider */
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} TRNG_Regs;
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/*@}*/ /* end of group TRNG */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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/******************************************************************************
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* TRNG Register Control Bits
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******************************************************************************/
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/* TRNG_IIDX Bits */
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/* TRNG_IIDX[STAT] Bits */
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#define TRNG_IIDX_STAT_OFS (0) /* !< STAT Offset */
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#define TRNG_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */
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#define TRNG_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No bit is set means there is no
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pending interrupt request */
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#define TRNG_IIDX_STAT_IRQ_HEALTH_FAIL ((uint32_t)0x00000001U) /* !< Indicates that a health test has
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failed. The TRNG is in an error state
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until the interrupt is cleared. */
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#define TRNG_IIDX_STAT_IRQ_CMD_FAIL ((uint32_t)0x00000002U) /* !< Indicates that the just issued
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command was rejected and is not being
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performed. */
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#define TRNG_IIDX_STAT_IRQ_CMD_DONE ((uint32_t)0x00000003U) /* !< Indicates that the current
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command/mode is done. This may have
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different meanings based on the mode:
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OFF --> Power has been turned off
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PWRUP_DIG --> Digital powerup tests
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are done PWRUP_ANA --> Analog powerup
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tests are done NORM_FUNC --> No IRQ,
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since mode runs indefinitely until a
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new command is issued */
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#define TRNG_IIDX_STAT_IRQ_CAPTURED_RDY ((uint32_t)0x00000004U) /* !< Indicates that the captured word
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buffer is ready to be copied to
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memory */
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/* TRNG_IMASK Bits */
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/* TRNG_IMASK[IRQ_HEALTH_FAIL] Bits */
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#define TRNG_IMASK_IRQ_HEALTH_FAIL_OFS (0) /* !< IRQ_HEALTH_FAIL Offset */
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#define TRNG_IMASK_IRQ_HEALTH_FAIL_MASK ((uint32_t)0x00000001U) /* !< Mask for IRQ_HEALTH_FAIL. Indicates
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that a health test has failed. */
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#define TRNG_IMASK_IRQ_HEALTH_FAIL_DISABLED ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
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#define TRNG_IMASK_IRQ_HEALTH_FAIL_ENABLED ((uint32_t)0x00000001U) /* !< Interrupt will request an interrupt
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service routine and corresponding bit
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in MIS will be set */
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/* TRNG_IMASK[IRQ_CAPTURED_RDY] Bits */
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#define TRNG_IMASK_IRQ_CAPTURED_RDY_OFS (3) /* !< IRQ_CAPTURED_RDY Offset */
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#define TRNG_IMASK_IRQ_CAPTURED_RDY_MASK ((uint32_t)0x00000008U) /* !< Mask for IRQ_CAPTURED_RDY.
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Indicates to the CPU that the
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Captured Word is ready to be read. */
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#define TRNG_IMASK_IRQ_CAPTURED_RDY_DISABLED ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
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#define TRNG_IMASK_IRQ_CAPTURED_RDY_ENABLED ((uint32_t)0x00000008U) /* !< Interrupt will request an interrupt
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service routine and corresponding bit
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in MIS will be set */
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/* TRNG_IMASK[IRQ_CMD_DONE] Bits */
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#define TRNG_IMASK_IRQ_CMD_DONE_OFS (2) /* !< IRQ_CMD_DONE Offset */
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#define TRNG_IMASK_IRQ_CMD_DONE_MASK ((uint32_t)0x00000004U) /* !< Mask for IRQ_CMD_DONE. Indicates
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that a command has finished */
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#define TRNG_IMASK_IRQ_CMD_DONE_DISABLED ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
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#define TRNG_IMASK_IRQ_CMD_DONE_ENABLED ((uint32_t)0x00000004U) /* !< Interrupt will request an interrupt
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service routine and corresponding bit
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in MIS will be set */
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/* TRNG_IMASK[IRQ_CMD_FAIL] Bits */
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#define TRNG_IMASK_IRQ_CMD_FAIL_OFS (1) /* !< IRQ_CMD_FAIL Offset */
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#define TRNG_IMASK_IRQ_CMD_FAIL_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt source for
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IRQ_CMD_FAIL. Indicates that the just
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issued command/mode has been
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rejected. */
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#define TRNG_IMASK_IRQ_CMD_FAIL_DISABLED ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
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#define TRNG_IMASK_IRQ_CMD_FAIL_ENABLED ((uint32_t)0x00000002U) /* !< Interrupt will request an interrupt
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service routine and corresponding bit
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in MIS will be set */
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/* TRNG_RIS Bits */
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/* TRNG_RIS[IRQ_CAPTURED_RDY] Bits */
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#define TRNG_RIS_IRQ_CAPTURED_RDY_OFS (3) /* !< IRQ_CAPTURED_RDY Offset */
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#define TRNG_RIS_IRQ_CAPTURED_RDY_MASK ((uint32_t)0x00000008U) /* !< Indicates to the CPU that the
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Captured Word is ready to be read.
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Reading the IIDX will clear this
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interrupt. */
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#define TRNG_RIS_IRQ_CAPTURED_RDY_CLR ((uint32_t)0x00000000U) /* !< IRQ_CAPTURED_READY did not occur */
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#define TRNG_RIS_IRQ_CAPTURED_RDY_SET ((uint32_t)0x00000008U) /* !< IRQ_CAPTURED_READY occurred */
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/* TRNG_RIS[IRQ_HEALTH_FAIL] Bits */
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#define TRNG_RIS_IRQ_HEALTH_FAIL_OFS (0) /* !< IRQ_HEALTH_FAIL Offset */
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#define TRNG_RIS_IRQ_HEALTH_FAIL_MASK ((uint32_t)0x00000001U) /* !< Indicates to the CPU that any of
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the health tests have failed. Reading
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the IIDX will clear this interrupt. */
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#define TRNG_RIS_IRQ_HEALTH_FAIL_CLR ((uint32_t)0x00000000U) /* !< IRQ_CAPTURED_READY did not occur */
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#define TRNG_RIS_IRQ_HEALTH_FAIL_SET ((uint32_t)0x00000001U) /* !< IRQ_CAPTURED_READY occurred */
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/* TRNG_RIS[IRQ_CMD_DONE] Bits */
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#define TRNG_RIS_IRQ_CMD_DONE_OFS (2) /* !< IRQ_CMD_DONE Offset */
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#define TRNG_RIS_IRQ_CMD_DONE_MASK ((uint32_t)0x00000004U) /* !< Raw interrupt source for
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IRQ_CMD_DONE. Indicates that the
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issued command/mode has completed. */
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#define TRNG_RIS_IRQ_CMD_DONE_CLR ((uint32_t)0x00000000U) /* !< IRQ_CMD_DONE did not occur */
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#define TRNG_RIS_IRQ_CMD_DONE_SET ((uint32_t)0x00000004U) /* !< IRQ_CMD_DONE occurred */
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/* TRNG_RIS[IRQ_CMD_FAIL] Bits */
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#define TRNG_RIS_IRQ_CMD_FAIL_OFS (1) /* !< IRQ_CMD_FAIL Offset */
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#define TRNG_RIS_IRQ_CMD_FAIL_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt source for
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IRQ_CMD_FAIL. Indicates that the just
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issued command/mode has been
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rejected. */
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#define TRNG_RIS_IRQ_CMD_FAIL_CLR ((uint32_t)0x00000000U) /* !< IRQ_CMD_FAIL did not occur */
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#define TRNG_RIS_IRQ_CMD_FAIL_SET ((uint32_t)0x00000002U) /* !< IRQ_CMD_FAIL occurred */
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/* TRNG_MIS Bits */
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/* TRNG_MIS[IRQ_CAPTURED_RDY] Bits */
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#define TRNG_MIS_IRQ_CAPTURED_RDY_OFS (3) /* !< IRQ_CAPTURED_RDY Offset */
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#define TRNG_MIS_IRQ_CAPTURED_RDY_MASK ((uint32_t)0x00000008U) /* !< Masked interrupt result for
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CAPTURED_READY. Indicates to the CPU
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that the Captured Word is ready to be
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read. Reading the IIDX will clear
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this interrupt. */
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#define TRNG_MIS_IRQ_CAPTURED_RDY_CLR ((uint32_t)0x00000000U) /* !< IRQ_CAPTURED_READY did not request
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an interrupt service routine */
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#define TRNG_MIS_IRQ_CAPTURED_RDY_SET ((uint32_t)0x00000008U) /* !< IRQ_CAPTURED_READY requests an
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interrupt service routine */
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/* TRNG_MIS[IRQ_HEALTH_FAIL] Bits */
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#define TRNG_MIS_IRQ_HEALTH_FAIL_OFS (0) /* !< IRQ_HEALTH_FAIL Offset */
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#define TRNG_MIS_IRQ_HEALTH_FAIL_MASK ((uint32_t)0x00000001U) /* !< Masked interrupt result for
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HEALTH_FAIL. Indicates to the CPU
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that any of the health tests have
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failed for the latest 1024-bit
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window. */
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#define TRNG_MIS_IRQ_HEALTH_FAIL_CLR ((uint32_t)0x00000000U) /* !< IRQ_CAPTURED_READY did not request
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an interrupt service routine */
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#define TRNG_MIS_IRQ_HEALTH_FAIL_SET ((uint32_t)0x00000001U) /* !< IRQ_CAPTURED_READY requests an
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interrupt service routine */
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/* TRNG_MIS[IRQ_CMD_DONE] Bits */
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#define TRNG_MIS_IRQ_CMD_DONE_OFS (2) /* !< IRQ_CMD_DONE Offset */
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#define TRNG_MIS_IRQ_CMD_DONE_MASK ((uint32_t)0x00000004U) /* !< Masked interrupt source for
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IRQ_CMD_DONE. Indicates that the
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issued command/mode has completed. */
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#define TRNG_MIS_IRQ_CMD_DONE_CLR ((uint32_t)0x00000000U) /* !< IRQ_CAPTURED_READY did not request
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an interrupt service routine */
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#define TRNG_MIS_IRQ_CMD_DONE_SET ((uint32_t)0x00000004U) /* !< IRQ_CMD_DONE requests an interrupt
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service routine */
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/* TRNG_MIS[IRQ_CMD_FAIL] Bits */
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#define TRNG_MIS_IRQ_CMD_FAIL_OFS (1) /* !< IRQ_CMD_FAIL Offset */
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#define TRNG_MIS_IRQ_CMD_FAIL_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt source for
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IRQ_CMD_FAIL. Indicates that the just
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issued command/mode has been
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rejected. */
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#define TRNG_MIS_IRQ_CMD_FAIL_CLR ((uint32_t)0x00000000U) /* !< IRQ_CMD_FAIL did not request an
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interrupt service routine */
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#define TRNG_MIS_IRQ_CMD_FAIL_SET ((uint32_t)0x00000002U) /* !< IRQ_CMD_FAIL requests an interrupt
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service routine */
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/* TRNG_ISET Bits */
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/* TRNG_ISET[IRQ_CAPTURED_RDY] Bits */
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#define TRNG_ISET_IRQ_CAPTURED_RDY_OFS (3) /* !< IRQ_CAPTURED_RDY Offset */
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#define TRNG_ISET_IRQ_CAPTURED_RDY_MASK ((uint32_t)0x00000008U) /* !< Indicates to the CPU that the
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Captured Word is ready to be read.
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Reading the IIDX or DATA_CAPTURE
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registers will clear this interrupt. */
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#define TRNG_ISET_IRQ_CAPTURED_RDY_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define TRNG_ISET_IRQ_CAPTURED_RDY_SET ((uint32_t)0x00000008U) /* !< RIS bit corresponding to
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CAPTURED_READY is set */
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/* TRNG_ISET[IRQ_HEALTH_FAIL] Bits */
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#define TRNG_ISET_IRQ_HEALTH_FAIL_OFS (0) /* !< IRQ_HEALTH_FAIL Offset */
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#define TRNG_ISET_IRQ_HEALTH_FAIL_MASK ((uint32_t)0x00000001U) /* !< Indicates to the CPU that any of
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the health tests have failed. Reading
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the IIDX or DATA_CAPTURE registers
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will clear this interrupt. */
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#define TRNG_ISET_IRQ_HEALTH_FAIL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define TRNG_ISET_IRQ_HEALTH_FAIL_SET ((uint32_t)0x00000001U) /* !< RIS bit corresponding to
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HEALTH_FAIL is set */
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/* TRNG_ISET[IRQ_CMD_DONE] Bits */
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#define TRNG_ISET_IRQ_CMD_DONE_OFS (2) /* !< IRQ_CMD_DONE Offset */
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#define TRNG_ISET_IRQ_CMD_DONE_MASK ((uint32_t)0x00000004U) /* !< Write to turn on CMD_DONE IRQ.
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Indicates that the last issued TRNG
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command has finished. */
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#define TRNG_ISET_IRQ_CMD_DONE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect. */
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#define TRNG_ISET_IRQ_CMD_DONE_SET ((uint32_t)0x00000004U) /* !< RIS bit corresponding to CMD_DONE
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is set */
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/* TRNG_ISET[IRQ_CMD_FAIL] Bits */
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#define TRNG_ISET_IRQ_CMD_FAIL_OFS (1) /* !< IRQ_CMD_FAIL Offset */
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#define TRNG_ISET_IRQ_CMD_FAIL_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt source for
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IRQ_CMD_FAIL. Indicates that the just
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issued command/mode has been
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rejected. */
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#define TRNG_ISET_IRQ_CMD_FAIL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect. */
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#define TRNG_ISET_IRQ_CMD_FAIL_SET ((uint32_t)0x00000002U) /* !< RIS bit corresponding to CMD_FAIL
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is set */
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/* TRNG_ICLR Bits */
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/* TRNG_ICLR[IRQ_CAPTURED_RDY] Bits */
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#define TRNG_ICLR_IRQ_CAPTURED_RDY_OFS (3) /* !< IRQ_CAPTURED_RDY Offset */
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#define TRNG_ICLR_IRQ_CAPTURED_RDY_MASK ((uint32_t)0x00000008U) /* !< Indicates to the CPU that the
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Captured Word is ready to be read.
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Reading the IIDX or DATA_CAPTURE
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registers will clear this interrupt. */
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#define TRNG_ICLR_IRQ_CAPTURED_RDY_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define TRNG_ICLR_IRQ_CAPTURED_RDY_CLR ((uint32_t)0x00000008U) /* !< RIS bit corresponding to
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CAPTURED_READY is cleared */
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/* TRNG_ICLR[IRQ_HEALTH_FAIL] Bits */
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#define TRNG_ICLR_IRQ_HEALTH_FAIL_OFS (0) /* !< IRQ_HEALTH_FAIL Offset */
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#define TRNG_ICLR_IRQ_HEALTH_FAIL_MASK ((uint32_t)0x00000001U) /* !< Indicates to the CPU that any of
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the health tests have failed. Reading
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the IIDX or DATA_CAPTURE registers
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will clear this interrupt. */
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#define TRNG_ICLR_IRQ_HEALTH_FAIL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define TRNG_ICLR_IRQ_HEALTH_FAIL_CLR ((uint32_t)0x00000001U) /* !< RIS bit corresponding to
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CAPTURED_READY is cleared */
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/* TRNG_ICLR[IRQ_CMD_DONE] Bits */
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#define TRNG_ICLR_IRQ_CMD_DONE_OFS (2) /* !< IRQ_CMD_DONE Offset */
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#define TRNG_ICLR_IRQ_CMD_DONE_MASK ((uint32_t)0x00000004U) /* !< Write to turn off CMD_DONE IRQ.
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Indicates that the last issued TRNG
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command has finished. */
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#define TRNG_ICLR_IRQ_CMD_DONE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect. */
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#define TRNG_ICLR_IRQ_CMD_DONE_CLR ((uint32_t)0x00000004U) /* !< RIS bit corresponding to CMD_DONE
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is cleared */
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/* TRNG_ICLR[IRQ_CMD_FAIL] Bits */
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#define TRNG_ICLR_IRQ_CMD_FAIL_OFS (1) /* !< IRQ_CMD_FAIL Offset */
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#define TRNG_ICLR_IRQ_CMD_FAIL_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt source for
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IRQ_CMD_FAIL. Indicates that the just
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issued command/mode has been
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rejected. */
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#define TRNG_ICLR_IRQ_CMD_FAIL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect. */
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#define TRNG_ICLR_IRQ_CMD_FAIL_CLR ((uint32_t)0x00000002U) /* !< RIS bit corresponding to CMD_FAIL
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is cleared */
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/* TRNG_PWREN Bits */
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/* TRNG_PWREN[ENABLE] Bits */
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#define TRNG_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */
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#define TRNG_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */
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#define TRNG_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */
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#define TRNG_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */
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/* TRNG_PWREN[KEY] Bits */
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#define TRNG_PWREN_KEY_OFS (24) /* !< KEY Offset */
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#define TRNG_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */
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#define TRNG_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this
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register */
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/* TRNG_RSTCTL Bits */
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/* TRNG_RSTCTL[RESETSTKYCLR] Bits */
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#define TRNG_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */
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#define TRNG_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT
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register */
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#define TRNG_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
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#define TRNG_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */
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/* TRNG_RSTCTL[RESETASSERT] Bits */
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#define TRNG_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */
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#define TRNG_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */
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#define TRNG_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
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#define TRNG_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */
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/* TRNG_RSTCTL[KEY] Bits */
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#define TRNG_RSTCTL_KEY_OFS (24) /* !< KEY Offset */
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#define TRNG_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */
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#define TRNG_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this
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register */
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/* TRNG_GPRCM_STAT Bits */
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/* TRNG_GPRCM_STAT[RESETSTKY] Bits */
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#define TRNG_GPRCM_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */
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#define TRNG_GPRCM_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the
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peripheral was reset, since this bit
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was cleared by RESETSTKYCLR in the
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RSTCTL register */
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#define TRNG_GPRCM_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset
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since this bit was last cleared by
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RESETSTKYCLR in the RSTCTL register */
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#define TRNG_GPRCM_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the
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last bit clear */
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/* TRNG_DESC Bits */
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/* TRNG_DESC[MINREV] Bits */
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#define TRNG_DESC_MINREV_OFS (0) /* !< MINREV Offset */
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#define TRNG_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */
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/* TRNG_DESC[MAJREV] Bits */
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#define TRNG_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */
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#define TRNG_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */
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/* TRNG_DESC[INSTNUM] Bits */
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#define TRNG_DESC_INSTNUM_OFS (8) /* !< INSTNUM Offset */
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#define TRNG_DESC_INSTNUM_MASK ((uint32_t)0x00000F00U) /* !< Instance Number within the device.
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This will be a parameter to the RTL
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for modules that can have multiple
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instances */
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/* TRNG_DESC[FEATUREVER] Bits */
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#define TRNG_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */
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#define TRNG_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module
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*instance* */
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/* TRNG_DESC[MODULEID] Bits */
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#define TRNG_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */
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#define TRNG_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module Identifier - An internal TI
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page has been created to request
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unique module IDs */
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/* TRNG_CTL Bits */
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/* TRNG_CTL[DECIM_RATE] Bits */
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#define TRNG_CTL_DECIM_RATE_OFS (8) /* !< DECIM_RATE Offset */
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#define TRNG_CTL_DECIM_RATE_MASK ((uint32_t)0x00000700U) /* !< Set decimation rate. Decimate by n
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0x0 = Decimation by 1 (no decimation)
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0x1 = Decimation by 2 (Skip every
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other sample) 0x7 = Decimation by 8
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(Take every 8th sample) */
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/* TRNG_CTL[PWRUP_CLKDIV] Bits */
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#define TRNG_CTL_PWRUP_CLKDIV_OFS (16) /* !< PWRUP_CLKDIV Offset */
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#define TRNG_CTL_PWRUP_CLKDIV_MASK ((uint32_t)0x00010000U) /* !< When '1', the powerup sequence will
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take twice as long (i.e., clock
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frequency halved) */
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/* TRNG_CTL[PWRUP_PCHRG_CFG] Bits */
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#define TRNG_CTL_PWRUP_PCHRG_CFG_OFS (17) /* !< PWRUP_PCHRG_CFG Offset */
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#define TRNG_CTL_PWRUP_PCHRG_CFG_MASK ((uint32_t)0x00060000U) /* !< Configure PCHARGE sequence length
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b00 = Disabled b01 = 20 us PCHARGE
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b10 = 30 us PCHARGE (default) b11 =
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40 us PCHARGE */
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/* TRNG_CTL[PWRUP_PSTART_CFG] Bits */
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#define TRNG_CTL_PWRUP_PSTART_CFG_OFS (19) /* !< PWRUP_PSTART_CFG Offset */
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#define TRNG_CTL_PWRUP_PSTART_CFG_MASK ((uint32_t)0x00180000U) /* !< Configure pusle startup sequence
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length b00 = Disabled b01 = rise at
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10us, fall at 50us b10 = rise at
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10us, fall at 70us (default) b11 =
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rise at 10us, fall at 90us */
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/* TRNG_CTL[CMD] Bits */
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#define TRNG_CTL_CMD_OFS (0) /* !< CMD Offset */
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#define TRNG_CTL_CMD_MASK ((uint32_t)0x00000003U) /* !< Sets the TRNG mode through a
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command. The mode will not be updated
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until the previous command is done,
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as indicated by IRQ_CMD_DONE. 00 -->
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OFF 01 --> PWRUP_DIG 10 --> PWRUP_ANA
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11 --> NORM_FUNC */
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#define TRNG_CTL_CMD_PWR_OFF ((uint32_t)0x00000000U) /* !< Turns the power off of the analog
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source and clocks the digital
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interface */
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#define TRNG_CTL_CMD_PWRUP_DIG ((uint32_t)0x00000001U) /* !< Initiates the powerup test sequence
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for the digital components. This
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verifies that the digital components
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are properly working. IRQ_CMD_DONE
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indicates that the test is done. The
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results of this test are in bits 0:6
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in TEST_RESULTS register */
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#define TRNG_CTL_CMD_PWRUP_ANA ((uint32_t)0x00000002U) /* !< Initiates the powerup test sequence
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for the analog TRNG. This verifies
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that the analog component is
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generating sequences with enough
|
|
entropy. IRQ_CMD_DONE indicates that
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|
the test is done. The results of this
|
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test are in bit 7 in TEST_RESULTS
|
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register */
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#define TRNG_CTL_CMD_NORM_FUNC ((uint32_t)0x00000003U) /* !< Normal operating mode for TRNG. All
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components are turned on. */
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/* TRNG_STAT Bits */
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/* TRNG_STAT[ADAP_FAIL] Bits */
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#define TRNG_STAT_ADAP_FAIL_OFS (0) /* !< ADAP_FAIL Offset */
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#define TRNG_STAT_ADAP_FAIL_MASK ((uint32_t)0x00000001U) /* !< Indicates that the Adaptive
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|
Proportion Test (1,2,3, or 4-bit
|
|
counters) failed by having too many
|
|
or too few counted samples in the
|
|
last 1024 bit window. */
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/* TRNG_STAT[ISSUED_CMD] Bits */
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#define TRNG_STAT_ISSUED_CMD_OFS (8) /* !< ISSUED_CMD Offset */
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#define TRNG_STAT_ISSUED_CMD_MASK ((uint32_t)0x00000300U) /* !< Indicates the last accepted command
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|
that is issued to the TRNG interface.
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|
Upon writing a valid command, this
|
|
register will update and the command
|
|
will be in progress until
|
|
CMD_DONE_IRQ is set. CMD_DONE_IRQ
|
|
indicates that the state is in
|
|
PWROFF, NORM_FUNC, or ERROR. These
|
|
states will accept new commands. 00
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|
--> OFF 01 --> PWRUP_DIG 10 -->
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|
PWRUP_ANA 11 --> NORM_FUNC */
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/* TRNG_STAT[FSM_STATE] Bits */
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#define TRNG_STAT_FSM_STATE_OFS (16) /* !< FSM_STATE Offset */
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|
#define TRNG_STAT_FSM_STATE_MASK ((uint32_t)0x000F0000U) /* !< Current state of the front end FSM
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|
(behind a clock domain crossing). 2
|
|
reads are REQUIRED as there is a
|
|
chance of metastability when reading
|
|
this States: 0000: OFF 0001: PWRUP_ES
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|
0011: NORM_FUNC 0111: TEST_DIG 1011:
|
|
TEST_ANA 1010: ERROR 0010: PWRDOWN_ES */
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/* TRNG_STAT[REP_FAIL] Bits */
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|
#define TRNG_STAT_REP_FAIL_OFS (1) /* !< REP_FAIL Offset */
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|
#define TRNG_STAT_REP_FAIL_MASK ((uint32_t)0x00000002U) /* !< Indicates that the repetition
|
|
counter test caused the most recent
|
|
failure. Thus, the health count
|
|
numbers are most likely not for a
|
|
complete 1024-bit window. */
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|
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/* TRNG_DATA_CAPTURE Bits */
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|
/* TRNG_DATA_CAPTURE[BUFFER] Bits */
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|
#define TRNG_DATA_CAPTURE_BUFFER_OFS (0) /* !< BUFFER Offset */
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|
#define TRNG_DATA_CAPTURE_BUFFER_MASK ((uint32_t)0xFFFFFFFFU) /* !< Captured Data from the Decimation
|
|
Block */
|
|
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/* TRNG_TEST_RESULTS Bits */
|
|
/* TRNG_TEST_RESULTS[DIG_TEST] Bits */
|
|
#define TRNG_TEST_RESULTS_DIG_TEST_OFS (0) /* !< DIG_TEST Offset */
|
|
#define TRNG_TEST_RESULTS_DIG_TEST_MASK ((uint32_t)0x000000FFU) /* !< Bit 0 indicates if the first
|
|
decimation rate test and health
|
|
test(verifies conditioning,
|
|
decimation, and captured buffer)
|
|
fails and Bit 1 indicates if the
|
|
second decimation test and health
|
|
test fails Bit 0 - decim_test0 (decim
|
|
= 0x0) Bit 1 - decim_test1 (decim =
|
|
0x1) ... */
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|
/* TRNG_TEST_RESULTS[ANA_TEST] Bits */
|
|
#define TRNG_TEST_RESULTS_ANA_TEST_OFS (8) /* !< ANA_TEST Offset */
|
|
#define TRNG_TEST_RESULTS_ANA_TEST_MASK ((uint32_t)0x00000100U) /* !< Runs through 4096 samples from an
|
|
enabled entropy source and verifies
|
|
that none of the health tests failed,
|
|
indicating sufficient entropy was
|
|
produced by the analog components */
|
|
|
|
/* TRNG_CLKDIVIDE Bits */
|
|
/* TRNG_CLKDIVIDE[RATIO] Bits */
|
|
#define TRNG_CLKDIVIDE_RATIO_OFS (0) /* !< RATIO Offset */
|
|
#define TRNG_CLKDIVIDE_RATIO_MASK ((uint32_t)0x00000007U) /* !< Selects divide ratio of module
|
|
clock */
|
|
#define TRNG_CLKDIVIDE_RATIO_DIV_BY_1 ((uint32_t)0x00000000U) /* !< Do not divide clock source */
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|
#define TRNG_CLKDIVIDE_RATIO_DIV_BY_2 ((uint32_t)0x00000001U) /* !< Divide clock source by 2 */
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|
#define TRNG_CLKDIVIDE_RATIO_DIV_BY_4 ((uint32_t)0x00000003U) /* !< Divide clock source by 4 */
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|
#define TRNG_CLKDIVIDE_RATIO_DIV_BY_6 ((uint32_t)0x00000005U) /* !< Divide clock source by 6 */
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|
#define TRNG_CLKDIVIDE_RATIO_DIV_BY_8 ((uint32_t)0x00000007U) /* !< Divide clock source by 8 */
|
|
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* ti_devices_msp_peripherals_hw_trng__include */
|