SkyLi
461 lines
35 KiB
C
461 lines
35 KiB
C
/*****************************************************************************
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Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the
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distribution.
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Neither the name of Texas Instruments Incorporated nor the names of
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its contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#ifndef ti_devices_msp_peripherals_m0p_hw_debugss__include
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#define ti_devices_msp_peripherals_m0p_hw_debugss__include
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/* Filename: hw_debugss.h */
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/* Revised: 2023-05-10 21:16:53 */
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/* Revision: 2f29710894b537f621c6ebedd563efb234664827 */
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#ifndef __CORTEX_M
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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#endif
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/* Use standard integer types with explicit width */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/******************************************************************************
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* DEBUGSS Registers
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******************************************************************************/
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#define DEBUGSS_CPU_INT_OFS ((uint32_t)0x00001020U)
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/** @addtogroup DEBUGSS_CPU_INT
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@{
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*/
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typedef struct {
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__I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */
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uint32_t RESERVED0;
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__IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */
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uint32_t RESERVED1;
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__I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */
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uint32_t RESERVED2;
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__I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */
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uint32_t RESERVED3;
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__O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */
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uint32_t RESERVED4;
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__O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */
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} DEBUGSS_CPU_INT_Regs;
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/*@}*/ /* end of group DEBUGSS_CPU_INT */
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/** @addtogroup DEBUGSS
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@{
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*/
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typedef struct {
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uint32_t RESERVED0[1032];
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DEBUGSS_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */
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uint32_t RESERVED1[37];
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__I uint32_t EVT_MODE; /* !< (@ 0x000010E0) Event Mode */
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uint32_t RESERVED2[6];
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__I uint32_t DESC; /* !< (@ 0x000010FC) Module Description */
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__I uint32_t TXD; /* !< (@ 0x00001100) Transmit data register */
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__I uint32_t TXCTL; /* !< (@ 0x00001104) Transmit control register */
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__IO uint32_t RXD; /* !< (@ 0x00001108) Receive data register */
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__IO uint32_t RXCTL; /* !< (@ 0x0000110C) Receive control register */
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uint32_t RESERVED3[60];
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__I uint32_t SPECIAL_AUTH; /* !< (@ 0x00001200) Special enable authorization register */
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uint32_t RESERVED4[3];
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__I uint32_t APP_AUTH; /* !< (@ 0x00001210) Application CPU0 authorization register */
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} DEBUGSS_Regs;
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/*@}*/ /* end of group DEBUGSS */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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/******************************************************************************
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* DEBUGSS Register Control Bits
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******************************************************************************/
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/* DEBUGSS_IIDX Bits */
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/* DEBUGSS_IIDX[STAT] Bits */
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#define DEBUGSS_IIDX_STAT_OFS (0) /* !< STAT Offset */
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#define DEBUGSS_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */
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#define DEBUGSS_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No pending interrupt request */
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#define DEBUGSS_IIDX_STAT_TXIFG ((uint32_t)0x00000001U) /* !< TX interrupt */
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#define DEBUGSS_IIDX_STAT_RXIFG ((uint32_t)0x00000002U) /* !< RX interrupt */
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#define DEBUGSS_IIDX_STAT_PWRUP ((uint32_t)0x00000003U) /* !< Power-up interrupt. A debug session
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has started. */
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#define DEBUGSS_IIDX_STAT_PWRDWN ((uint32_t)0x00000004U) /* !< Power-up interrupt. A debug session
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has started. */
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/* DEBUGSS_IMASK Bits */
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/* DEBUGSS_IMASK[TXIFG] Bits */
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#define DEBUGSS_IMASK_TXIFG_OFS (0) /* !< TXIFG Offset */
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#define DEBUGSS_IMASK_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Masks TXIFG in MIS register */
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#define DEBUGSS_IMASK_TXIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
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#define DEBUGSS_IMASK_TXIFG_SET ((uint32_t)0x00000001U) /* !< Interrupt will request an interrupt
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service routine and corresponding bit
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in MIS will be set */
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/* DEBUGSS_IMASK[RXIFG] Bits */
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#define DEBUGSS_IMASK_RXIFG_OFS (1) /* !< RXIFG Offset */
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#define DEBUGSS_IMASK_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Masks RXIFG in MIS register */
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#define DEBUGSS_IMASK_RXIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
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#define DEBUGSS_IMASK_RXIFG_SET ((uint32_t)0x00000002U) /* !< Interrupt will request an interrupt
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service routine and corresponding bit
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in MIS will be set */
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/* DEBUGSS_IMASK[PWRUPIFG] Bits */
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#define DEBUGSS_IMASK_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
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#define DEBUGSS_IMASK_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Masks PWRUPIFG in MIS register */
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#define DEBUGSS_IMASK_PWRUPIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
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#define DEBUGSS_IMASK_PWRUPIFG_SET ((uint32_t)0x00000004U) /* !< Interrupt will request an interrupt
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service routine and corresponding bit
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in MIS will be set */
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/* DEBUGSS_IMASK[PWRDWNIFG] Bits */
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#define DEBUGSS_IMASK_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
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#define DEBUGSS_IMASK_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Masks PWRDWNIFG in MIS register */
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#define DEBUGSS_IMASK_PWRDWNIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
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#define DEBUGSS_IMASK_PWRDWNIFG_SET ((uint32_t)0x00000008U) /* !< Interrupt will request an interrupt
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service routine and corresponding bit
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in MIS will be set */
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/* DEBUGSS_RIS Bits */
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/* DEBUGSS_RIS[TXIFG] Bits */
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#define DEBUGSS_RIS_TXIFG_OFS (0) /* !< TXIFG Offset */
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#define DEBUGSS_RIS_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Raw interrupt status for TXIFG */
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#define DEBUGSS_RIS_TXIFG_CLR ((uint32_t)0x00000000U) /* !< TXIFG did not occur */
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#define DEBUGSS_RIS_TXIFG_SET ((uint32_t)0x00000001U) /* !< TXIFG occurred */
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/* DEBUGSS_RIS[RXIFG] Bits */
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#define DEBUGSS_RIS_RXIFG_OFS (1) /* !< RXIFG Offset */
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#define DEBUGSS_RIS_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Raw interrupt status for RXIFG */
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#define DEBUGSS_RIS_RXIFG_CLR ((uint32_t)0x00000000U) /* !< RXIFG did not occur */
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#define DEBUGSS_RIS_RXIFG_SET ((uint32_t)0x00000002U) /* !< RXIFG occurred */
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/* DEBUGSS_RIS[PWRUPIFG] Bits */
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#define DEBUGSS_RIS_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
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#define DEBUGSS_RIS_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Raw interrupt status for PWRUPIFG */
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#define DEBUGSS_RIS_PWRUPIFG_CLR ((uint32_t)0x00000000U) /* !< PWRUPIFG did not occur */
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#define DEBUGSS_RIS_PWRUPIFG_SET ((uint32_t)0x00000004U) /* !< PWRUPIFG occurred */
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/* DEBUGSS_RIS[PWRDWNIFG] Bits */
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#define DEBUGSS_RIS_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
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#define DEBUGSS_RIS_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Raw interrupt status for PWRDWNIFG */
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#define DEBUGSS_RIS_PWRDWNIFG_CLR ((uint32_t)0x00000000U) /* !< PWRUPIFG did not occur */
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#define DEBUGSS_RIS_PWRDWNIFG_SET ((uint32_t)0x00000008U) /* !< PWRUPIFG occurred */
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/* DEBUGSS_MIS Bits */
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/* DEBUGSS_MIS[TXIFG] Bits */
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#define DEBUGSS_MIS_TXIFG_OFS (0) /* !< TXIFG Offset */
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#define DEBUGSS_MIS_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Masked interrupt status for TXIFG */
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#define DEBUGSS_MIS_TXIFG_CLR ((uint32_t)0x00000000U) /* !< TXIFG did not request an interrupt
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service routine */
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#define DEBUGSS_MIS_TXIFG_SET ((uint32_t)0x00000001U) /* !< TXIFG requests an interrupt service
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routine */
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/* DEBUGSS_MIS[RXIFG] Bits */
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#define DEBUGSS_MIS_RXIFG_OFS (1) /* !< RXIFG Offset */
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#define DEBUGSS_MIS_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt status for RXIFG */
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#define DEBUGSS_MIS_RXIFG_CLR ((uint32_t)0x00000000U) /* !< RXIFG did not request an interrupt
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service routine */
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#define DEBUGSS_MIS_RXIFG_SET ((uint32_t)0x00000002U) /* !< RXIFG requests an interrupt service
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routine */
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/* DEBUGSS_MIS[PWRUPIFG] Bits */
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#define DEBUGSS_MIS_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
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#define DEBUGSS_MIS_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Masked interrupt status for
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PWRUPIFG */
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#define DEBUGSS_MIS_PWRUPIFG_CLR ((uint32_t)0x00000000U) /* !< PWRUPIFG did not request an
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interrupt service routine */
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#define DEBUGSS_MIS_PWRUPIFG_SET ((uint32_t)0x00000004U) /* !< PWRUPIFG requests an interrupt
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service routine */
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/* DEBUGSS_MIS[PWRDWNIFG] Bits */
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#define DEBUGSS_MIS_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
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#define DEBUGSS_MIS_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Masked interrupt status for
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PWRDWNIFG */
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#define DEBUGSS_MIS_PWRDWNIFG_CLR ((uint32_t)0x00000000U) /* !< PWRUPIFG did not request an
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interrupt service routine */
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#define DEBUGSS_MIS_PWRDWNIFG_SET ((uint32_t)0x00000008U) /* !< PWRUPIFG requests an interrupt
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service routine */
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/* DEBUGSS_ISET Bits */
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/* DEBUGSS_ISET[TXIFG] Bits */
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#define DEBUGSS_ISET_TXIFG_OFS (0) /* !< TXIFG Offset */
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#define DEBUGSS_ISET_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Sets TXIFG in RIS register */
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#define DEBUGSS_ISET_TXIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define DEBUGSS_ISET_TXIFG_SET ((uint32_t)0x00000001U) /* !< RIS bit corresponding to TXIFG is
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set */
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/* DEBUGSS_ISET[RXIFG] Bits */
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#define DEBUGSS_ISET_RXIFG_OFS (1) /* !< RXIFG Offset */
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#define DEBUGSS_ISET_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Sets RXIFG in RIS register */
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#define DEBUGSS_ISET_RXIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define DEBUGSS_ISET_RXIFG_SET ((uint32_t)0x00000002U) /* !< RIS bit corresponding to RXIFG is
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set */
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/* DEBUGSS_ISET[PWRUPIFG] Bits */
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#define DEBUGSS_ISET_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
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#define DEBUGSS_ISET_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Sets PWRUPIFG in RIS register */
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#define DEBUGSS_ISET_PWRUPIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define DEBUGSS_ISET_PWRUPIFG_SET ((uint32_t)0x00000004U) /* !< RIS bit corresponding to PWRUPIFG
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is set */
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/* DEBUGSS_ISET[PWRDWNIFG] Bits */
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#define DEBUGSS_ISET_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
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#define DEBUGSS_ISET_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Sets PWRDWNIFG in RIS register */
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#define DEBUGSS_ISET_PWRDWNIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define DEBUGSS_ISET_PWRDWNIFG_SET ((uint32_t)0x00000008U) /* !< RIS bit corresponding to PWRUPIFG
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is set */
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/* DEBUGSS_ICLR Bits */
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/* DEBUGSS_ICLR[TXIFG] Bits */
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#define DEBUGSS_ICLR_TXIFG_OFS (0) /* !< TXIFG Offset */
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#define DEBUGSS_ICLR_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Clears TXIFG in RIS register */
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#define DEBUGSS_ICLR_TXIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define DEBUGSS_ICLR_TXIFG_CLR ((uint32_t)0x00000001U) /* !< RIS bit corresponding to TXIFG is
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cleared */
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/* DEBUGSS_ICLR[RXIFG] Bits */
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#define DEBUGSS_ICLR_RXIFG_OFS (1) /* !< RXIFG Offset */
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#define DEBUGSS_ICLR_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Clears RXIFG in RIS register */
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#define DEBUGSS_ICLR_RXIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define DEBUGSS_ICLR_RXIFG_CLR ((uint32_t)0x00000002U) /* !< RIS bit corresponding to RXIFG is
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cleared */
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/* DEBUGSS_ICLR[PWRUPIFG] Bits */
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#define DEBUGSS_ICLR_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
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#define DEBUGSS_ICLR_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Clears PWRUPIFG in RIS register */
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#define DEBUGSS_ICLR_PWRUPIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define DEBUGSS_ICLR_PWRUPIFG_CLR ((uint32_t)0x00000004U) /* !< RIS bit corresponding to PWRUPIFG
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is cleared */
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/* DEBUGSS_ICLR[PWRDWNIFG] Bits */
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#define DEBUGSS_ICLR_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
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#define DEBUGSS_ICLR_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Clears PWRDWNIFG in RIS register */
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#define DEBUGSS_ICLR_PWRDWNIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
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#define DEBUGSS_ICLR_PWRDWNIFG_CLR ((uint32_t)0x00000008U) /* !< RIS bit corresponding to PWRUPIFG
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is cleared */
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/* DEBUGSS_EVT_MODE Bits */
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/* DEBUGSS_EVT_MODE[INT0_CFG] Bits */
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#define DEBUGSS_EVT_MODE_INT0_CFG_OFS (0) /* !< INT0_CFG Offset */
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#define DEBUGSS_EVT_MODE_INT0_CFG_MASK ((uint32_t)0x00000003U) /* !< Event line mode select for
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peripheral events */
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#define DEBUGSS_EVT_MODE_INT0_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
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disabled. */
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#define DEBUGSS_EVT_MODE_INT0_CFG_SOFTWARE ((uint32_t)0x00000001U) /* !< The interrupt or event line is in
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software mode. Software must clear
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the RIS. */
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#define DEBUGSS_EVT_MODE_INT0_CFG_HARDWARE ((uint32_t)0x00000002U) /* !< The interrupt or event line is in
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hardware mode. The hardware (another
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module) clears automatically the
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associated RIS flag. */
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/* DEBUGSS_DESC Bits */
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/* DEBUGSS_DESC[MINREV] Bits */
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#define DEBUGSS_DESC_MINREV_OFS (0) /* !< MINREV Offset */
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#define DEBUGSS_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */
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/* DEBUGSS_DESC[MAJREV] Bits */
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#define DEBUGSS_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */
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#define DEBUGSS_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */
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/* DEBUGSS_DESC[INSTNUM] Bits */
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#define DEBUGSS_DESC_INSTNUM_OFS (8) /* !< INSTNUM Offset */
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#define DEBUGSS_DESC_INSTNUM_MASK ((uint32_t)0x00000F00U) /* !< Instance Number within the device.
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This will be a parameter to the RTL
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for modules that can have multiple
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instances */
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/* DEBUGSS_DESC[FEATUREVER] Bits */
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#define DEBUGSS_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */
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#define DEBUGSS_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module
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*instance* */
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/* DEBUGSS_DESC[MODULEID] Bits */
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#define DEBUGSS_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */
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#define DEBUGSS_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module identification contains a
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unique peripheral identification
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number. The assignments are
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maintained in a central database for
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all of the platform modules to ensure
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uniqueness. */
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/* DEBUGSS_TXD Bits */
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/* DEBUGSS_TXD[TX_DATA] Bits */
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#define DEBUGSS_TXD_TX_DATA_OFS (0) /* !< TX_DATA Offset */
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#define DEBUGSS_TXD_TX_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Contains data written by an
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external debug tool to the SEC-AP
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TXDATA register */
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/* DEBUGSS_TXCTL Bits */
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/* DEBUGSS_TXCTL[TRANSMIT] Bits */
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#define DEBUGSS_TXCTL_TRANSMIT_OFS (0) /* !< TRANSMIT Offset */
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#define DEBUGSS_TXCTL_TRANSMIT_MASK ((uint32_t)0x00000001U) /* !< Indicates data request in DSSM.TXD,
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set on write via Debug AP to
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DSSM.TXD. A read of the DSSM.TXD
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register by SW will clear the TX
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field. The tool can check that TXD is
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empty by reading this field. */
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#define DEBUGSS_TXCTL_TRANSMIT_EMPTY ((uint32_t)0x00000000U) /* !< TXD is empty */
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#define DEBUGSS_TXCTL_TRANSMIT_FULL ((uint32_t)0x00000001U) /* !< TXD is full */
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/* DEBUGSS_TXCTL[TRANSMIT_FLAGS] Bits */
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#define DEBUGSS_TXCTL_TRANSMIT_FLAGS_OFS (1) /* !< TRANSMIT_FLAGS Offset */
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#define DEBUGSS_TXCTL_TRANSMIT_FLAGS_MASK ((uint32_t)0xFFFFFFFEU) /* !< Generic TX flags that can be set by
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external debug tool. Functionality is
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defined by SW. */
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/* DEBUGSS_RXD Bits */
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/* DEBUGSS_RXD[RX_DATA] Bits */
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#define DEBUGSS_RXD_RX_DATA_OFS (0) /* !< RX_DATA Offset */
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#define DEBUGSS_RXD_RX_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Contains data written by SM/OW. */
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/* DEBUGSS_RXCTL Bits */
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/* DEBUGSS_RXCTL[RECEIVE] Bits */
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#define DEBUGSS_RXCTL_RECEIVE_OFS (0) /* !< RECEIVE Offset */
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#define DEBUGSS_RXCTL_RECEIVE_MASK ((uint32_t)0x00000001U) /* !< Indicates SW write to the DSSM.RXD
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register. A read of the DSSM.RXD
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register by SWD Access Port will
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clear the RX field. */
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#define DEBUGSS_RXCTL_RECEIVE_EMPTY ((uint32_t)0x00000000U) /* !< RXD empty */
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#define DEBUGSS_RXCTL_RECEIVE_FULL ((uint32_t)0x00000001U) /* !< RXD full */
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/* DEBUGSS_RXCTL[RECEIVE_FLAGS] Bits */
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#define DEBUGSS_RXCTL_RECEIVE_FLAGS_OFS (1) /* !< RECEIVE_FLAGS Offset */
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#define DEBUGSS_RXCTL_RECEIVE_FLAGS_MASK ((uint32_t)0x000000FEU) /* !< Generic RX flags that can be set by
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SW and read by external debug tool.
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Functionality is defined by SW. */
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/* DEBUGSS_SPECIAL_AUTH Bits */
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/* DEBUGSS_SPECIAL_AUTH[SECAPEN] Bits */
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#define DEBUGSS_SPECIAL_AUTH_SECAPEN_OFS (0) /* !< SECAPEN Offset */
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#define DEBUGSS_SPECIAL_AUTH_SECAPEN_MASK ((uint32_t)0x00000001U) /* !< An active high input. When asserted
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(and SWD access is also permitted),
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the debug tools can use the
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Security-AP to communicate with
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security control logic. When
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deasserted, a DAPBUS firewall will
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isolate the AP and prevent access to
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the Security-AP. */
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#define DEBUGSS_SPECIAL_AUTH_SECAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable SEC-AP */
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#define DEBUGSS_SPECIAL_AUTH_SECAPEN_ENABLE ((uint32_t)0x00000001U) /* !< Enable SEC-AP */
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/* DEBUGSS_SPECIAL_AUTH[SWDPORTEN] Bits */
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#define DEBUGSS_SPECIAL_AUTH_SWDPORTEN_OFS (1) /* !< SWDPORTEN Offset */
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#define DEBUGSS_SPECIAL_AUTH_SWDPORTEN_MASK ((uint32_t)0x00000002U) /* !< When asserted, the SW-DP functions
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normally. When deasserted, the SW-DP
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effectively disables all external
|
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debug access. */
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#define DEBUGSS_SPECIAL_AUTH_SWDPORTEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable SWD port */
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#define DEBUGSS_SPECIAL_AUTH_SWDPORTEN_ENABLE ((uint32_t)0x00000002U) /* !< Enable SWD port */
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/* DEBUGSS_SPECIAL_AUTH[DFTAPEN] Bits */
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#define DEBUGSS_SPECIAL_AUTH_DFTAPEN_OFS (2) /* !< DFTAPEN Offset */
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#define DEBUGSS_SPECIAL_AUTH_DFTAPEN_MASK ((uint32_t)0x00000004U) /* !< An active high input. When asserted
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(and SWD access is also permitted),
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the debug tools can then access the
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DFT-AP external to the DebugSS lite.
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When deasserted, a DAPBUS firewall
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will isolate the AP and prevent
|
|
access. */
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#define DEBUGSS_SPECIAL_AUTH_DFTAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable DFT-TAP */
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#define DEBUGSS_SPECIAL_AUTH_DFTAPEN_ENABLE ((uint32_t)0x00000004U) /* !< Enable DFT-TAP */
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/* DEBUGSS_SPECIAL_AUTH[ETAPEN] Bits */
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#define DEBUGSS_SPECIAL_AUTH_ETAPEN_OFS (3) /* !< ETAPEN Offset */
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#define DEBUGSS_SPECIAL_AUTH_ETAPEN_MASK ((uint32_t)0x00000008U) /* !< An active high input. When asserted
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(and SWD access is also permitted),
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|
the debug tools can then access an
|
|
ET-AP external to the DebugSS lite.
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When deasserted, a DAPBUS firewall
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|
will isolate the AP and prevent
|
|
access. */
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#define DEBUGSS_SPECIAL_AUTH_ETAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable ET+ -AP */
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#define DEBUGSS_SPECIAL_AUTH_ETAPEN_ENABLE ((uint32_t)0x00000008U) /* !< Enable ET+ -AP */
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/* DEBUGSS_SPECIAL_AUTH[CFGAPEN] Bits */
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#define DEBUGSS_SPECIAL_AUTH_CFGAPEN_OFS (4) /* !< CFGAPEN Offset */
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|
#define DEBUGSS_SPECIAL_AUTH_CFGAPEN_MASK ((uint32_t)0x00000010U) /* !< An active high input. When asserted
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|
(and SWD access is also permitted),
|
|
the debug tools can use the Config-AP
|
|
to read device configuration
|
|
information. When deasserted, a
|
|
DAPBUS firewall will isolate the AP
|
|
and prevent access to the Config-AP. */
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#define DEBUGSS_SPECIAL_AUTH_CFGAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable CFG-AP */
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#define DEBUGSS_SPECIAL_AUTH_CFGAPEN_ENABLE ((uint32_t)0x00000010U) /* !< Enable CFG-AP */
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/* DEBUGSS_SPECIAL_AUTH[AHBAPEN] Bits */
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|
#define DEBUGSS_SPECIAL_AUTH_AHBAPEN_OFS (5) /* !< AHBAPEN Offset */
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|
#define DEBUGSS_SPECIAL_AUTH_AHBAPEN_MASK ((uint32_t)0x00000020U) /* !< Disabling / enabling debug access
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|
to the M0+ Core via the AHB-AP DAP
|
|
bus isolation. */
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#define DEBUGSS_SPECIAL_AUTH_AHBAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable AHB-AP */
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|
#define DEBUGSS_SPECIAL_AUTH_AHBAPEN_ENABLE ((uint32_t)0x00000020U) /* !< Enable AHB-AP */
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/* DEBUGSS_SPECIAL_AUTH[PWRAPEN] Bits */
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|
#define DEBUGSS_SPECIAL_AUTH_PWRAPEN_OFS (6) /* !< PWRAPEN Offset */
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|
#define DEBUGSS_SPECIAL_AUTH_PWRAPEN_MASK ((uint32_t)0x00000040U) /* !< An active high input. When asserted
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|
(and SWD access is also permitted),
|
|
the debug tools can then access the
|
|
PWR-AP to power and reset state of
|
|
the CPU. When deasserted, a DAPBUS
|
|
firewall will isolate the AP and
|
|
prevent access. */
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|
#define DEBUGSS_SPECIAL_AUTH_PWRAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable PWR-AP */
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|
#define DEBUGSS_SPECIAL_AUTH_PWRAPEN_ENABLE ((uint32_t)0x00000040U) /* !< Enable PWR-AP */
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|
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/* DEBUGSS_APP_AUTH Bits */
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|
/* DEBUGSS_APP_AUTH[DBGEN] Bits */
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|
#define DEBUGSS_APP_AUTH_DBGEN_OFS (0) /* !< DBGEN Offset */
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|
#define DEBUGSS_APP_AUTH_DBGEN_MASK ((uint32_t)0x00000001U) /* !< Controls invasive debug enable. */
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|
#define DEBUGSS_APP_AUTH_DBGEN_DISABLE ((uint32_t)0x00000000U) /* !< Invasive debug disabled */
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|
#define DEBUGSS_APP_AUTH_DBGEN_ENABLE ((uint32_t)0x00000001U) /* !< Invasive debug enabled */
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|
/* DEBUGSS_APP_AUTH[NIDEN] Bits */
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|
#define DEBUGSS_APP_AUTH_NIDEN_OFS (1) /* !< NIDEN Offset */
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|
#define DEBUGSS_APP_AUTH_NIDEN_MASK ((uint32_t)0x00000002U) /* !< Controls non-invasive debug enable. */
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|
#define DEBUGSS_APP_AUTH_NIDEN_DISABLE ((uint32_t)0x00000000U) /* !< Non-invasive debug disabled */
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|
#define DEBUGSS_APP_AUTH_NIDEN_ENABLE ((uint32_t)0x00000002U) /* !< Non-invasive debug enabled */
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|
/* DEBUGSS_APP_AUTH[SPIDEN] Bits */
|
|
#define DEBUGSS_APP_AUTH_SPIDEN_OFS (2) /* !< SPIDEN Offset */
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|
#define DEBUGSS_APP_AUTH_SPIDEN_MASK ((uint32_t)0x00000004U) /* !< Secure invasive debug enable. */
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|
#define DEBUGSS_APP_AUTH_SPIDEN_DISABLE ((uint32_t)0x00000000U) /* !< Invasive debug disabled */
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|
#define DEBUGSS_APP_AUTH_SPIDEN_ENABLE ((uint32_t)0x00000004U) /* !< Invasive debug enabled */
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|
/* DEBUGSS_APP_AUTH[SPNIDEN] Bits */
|
|
#define DEBUGSS_APP_AUTH_SPNIDEN_OFS (3) /* !< SPNIDEN Offset */
|
|
#define DEBUGSS_APP_AUTH_SPNIDEN_MASK ((uint32_t)0x00000008U) /* !< Secure non-invasive debug enable. */
|
|
#define DEBUGSS_APP_AUTH_SPNIDEN_DISABLE ((uint32_t)0x00000000U) /* !< Invasive debug disabled */
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|
#define DEBUGSS_APP_AUTH_SPNIDEN_ENABLE ((uint32_t)0x00000008U) /* !< Invasive debug enabled */
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|
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
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|
#endif /* ti_devices_msp_peripherals_m0p_hw_debugss__include */
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