SkyLi
269 lines
17 KiB
C
269 lines
17 KiB
C
/*****************************************************************************
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Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the
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distribution.
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Neither the name of Texas Instruments Incorporated nor the names of
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its contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#ifndef ti_devices_msp_peripherals_m0p_hw_cpuss__include
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#define ti_devices_msp_peripherals_m0p_hw_cpuss__include
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/* Filename: hw_cpuss.h */
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/* Revised: 2023-04-30 21:36:20 */
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/* Revision: ec4f3de051dafa6135b4867f4e796eec5f1a339b */
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#ifndef __CORTEX_M
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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#endif
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/* Use standard integer types with explicit width */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/******************************************************************************
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* CPUSS Registers
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******************************************************************************/
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#define CPUSS_INT_GROUP_OFS ((uint32_t)0x00001100U)
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/** @addtogroup CPUSS_INT_GROUP
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@{
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*/
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typedef struct {
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__I uint32_t IIDX; /* !< (@ 0x00001100) Interrupt index */
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uint32_t RESERVED0;
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__I uint32_t IMASK; /* !< (@ 0x00001108) Interrupt mask */
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uint32_t RESERVED1;
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__I uint32_t RIS; /* !< (@ 0x00001110) Raw interrupt status */
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uint32_t RESERVED2;
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__I uint32_t MIS; /* !< (@ 0x00001118) Masked interrupt status */
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uint32_t RESERVED3;
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__O uint32_t ISET; /* !< (@ 0x00001120) Interrupt set */
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uint32_t RESERVED4;
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__O uint32_t ICLR; /* !< (@ 0x00001128) Interrupt clear */
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uint32_t RESERVED5;
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} CPUSS_INT_GROUP_Regs;
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/*@}*/ /* end of group CPUSS_INT_GROUP */
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/** @addtogroup CPUSS
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@{
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*/
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typedef struct {
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uint32_t RESERVED0[1080];
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__I uint32_t EVT_MODE; /* !< (@ 0x000010E0) Event Mode */
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uint32_t RESERVED1[6];
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__I uint32_t DESC; /* !< (@ 0x000010FC) Module Description */
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CPUSS_INT_GROUP_Regs INT_GROUP[5]; /* !< (@ 0x00001100) */
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uint32_t RESERVED2[68];
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__IO uint32_t CTL; /* !< (@ 0x00001300) Prefetch/Cache control */
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} CPUSS_Regs;
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/*@}*/ /* end of group CPUSS */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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/******************************************************************************
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* CPUSS Register Control Bits
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******************************************************************************/
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/* CPUSS_INT_GROUP_IIDX Bits */
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/* CPUSS_INT_GROUP_IIDX[STAT] Bits */
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#define CPUSS_INT_GROUP_IIDX_STAT_OFS (0) /* !< STAT Offset */
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#define CPUSS_INT_GROUP_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */
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#define CPUSS_INT_GROUP_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No pending interrupt */
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#define CPUSS_INT_GROUP_IIDX_STAT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
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#define CPUSS_INT_GROUP_IIDX_STAT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
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#define CPUSS_INT_GROUP_IIDX_STAT_INT2 ((uint32_t)0x00000003U) /* !< Interrupt 2 */
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#define CPUSS_INT_GROUP_IIDX_STAT_INT3 ((uint32_t)0x00000004U) /* !< Interrupt 3 */
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#define CPUSS_INT_GROUP_IIDX_STAT_INT4 ((uint32_t)0x00000005U) /* !< Interrupt 4 */
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#define CPUSS_INT_GROUP_IIDX_STAT_INT5 ((uint32_t)0x00000006U) /* !< Interrupt 5 */
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#define CPUSS_INT_GROUP_IIDX_STAT_INT6 ((uint32_t)0x00000007U) /* !< Interrupt 6 */
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#define CPUSS_INT_GROUP_IIDX_STAT_INT7 ((uint32_t)0x00000008U) /* !< Interrupt 7 */
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/* CPUSS_INT_GROUP_IMASK Bits */
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/* CPUSS_INT_GROUP_IMASK[INT] Bits */
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#define CPUSS_INT_GROUP_IMASK_INT_OFS (0) /* !< INT Offset */
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#define CPUSS_INT_GROUP_IMASK_INT_MASK ((uint32_t)0x000000FFU) /* !< Masks the corresponding interrupt */
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#define CPUSS_INT_GROUP_IMASK_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
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#define CPUSS_INT_GROUP_IMASK_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
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#define CPUSS_INT_GROUP_IMASK_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
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#define CPUSS_INT_GROUP_IMASK_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
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#define CPUSS_INT_GROUP_IMASK_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
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#define CPUSS_INT_GROUP_IMASK_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
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#define CPUSS_INT_GROUP_IMASK_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
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#define CPUSS_INT_GROUP_IMASK_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
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/* CPUSS_INT_GROUP_RIS Bits */
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/* CPUSS_INT_GROUP_RIS[INT] Bits */
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#define CPUSS_INT_GROUP_RIS_INT_OFS (0) /* !< INT Offset */
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#define CPUSS_INT_GROUP_RIS_INT_MASK ((uint32_t)0x000000FFU) /* !< Raw interrupt status for INT */
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#define CPUSS_INT_GROUP_RIS_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
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#define CPUSS_INT_GROUP_RIS_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
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#define CPUSS_INT_GROUP_RIS_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
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#define CPUSS_INT_GROUP_RIS_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
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#define CPUSS_INT_GROUP_RIS_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
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#define CPUSS_INT_GROUP_RIS_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
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#define CPUSS_INT_GROUP_RIS_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
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#define CPUSS_INT_GROUP_RIS_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
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/* CPUSS_INT_GROUP_MIS Bits */
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/* CPUSS_INT_GROUP_MIS[INT] Bits */
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#define CPUSS_INT_GROUP_MIS_INT_OFS (0) /* !< INT Offset */
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#define CPUSS_INT_GROUP_MIS_INT_MASK ((uint32_t)0x000000FFU) /* !< Masked interrupt status for INT0 */
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#define CPUSS_INT_GROUP_MIS_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
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#define CPUSS_INT_GROUP_MIS_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
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#define CPUSS_INT_GROUP_MIS_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
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#define CPUSS_INT_GROUP_MIS_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
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#define CPUSS_INT_GROUP_MIS_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
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#define CPUSS_INT_GROUP_MIS_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
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#define CPUSS_INT_GROUP_MIS_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
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#define CPUSS_INT_GROUP_MIS_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
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/* CPUSS_INT_GROUP_ISET Bits */
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/* CPUSS_INT_GROUP_ISET[INT] Bits */
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#define CPUSS_INT_GROUP_ISET_INT_OFS (0) /* !< INT Offset */
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#define CPUSS_INT_GROUP_ISET_INT_MASK ((uint32_t)0x000000FFU) /* !< Sets INT in RIS register */
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#define CPUSS_INT_GROUP_ISET_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
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#define CPUSS_INT_GROUP_ISET_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
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#define CPUSS_INT_GROUP_ISET_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
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#define CPUSS_INT_GROUP_ISET_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
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#define CPUSS_INT_GROUP_ISET_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
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#define CPUSS_INT_GROUP_ISET_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
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#define CPUSS_INT_GROUP_ISET_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
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#define CPUSS_INT_GROUP_ISET_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
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/* CPUSS_INT_GROUP_ICLR Bits */
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/* CPUSS_INT_GROUP_ICLR[INT] Bits */
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#define CPUSS_INT_GROUP_ICLR_INT_OFS (0) /* !< INT Offset */
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#define CPUSS_INT_GROUP_ICLR_INT_MASK ((uint32_t)0x000000FFU) /* !< Clears INT in RIS register */
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#define CPUSS_INT_GROUP_ICLR_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
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#define CPUSS_INT_GROUP_ICLR_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
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#define CPUSS_INT_GROUP_ICLR_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
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#define CPUSS_INT_GROUP_ICLR_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
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#define CPUSS_INT_GROUP_ICLR_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
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#define CPUSS_INT_GROUP_ICLR_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
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#define CPUSS_INT_GROUP_ICLR_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
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#define CPUSS_INT_GROUP_ICLR_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
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/* CPUSS_EVT_MODE Bits */
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/* CPUSS_EVT_MODE[INT_CFG] Bits */
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#define CPUSS_EVT_MODE_INT_CFG_OFS (0) /* !< INT_CFG Offset */
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#define CPUSS_EVT_MODE_INT_CFG_MASK ((uint32_t)0x00000003U) /* !< Event line mode select */
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#define CPUSS_EVT_MODE_INT_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
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disabled. */
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#define CPUSS_EVT_MODE_INT_CFG_SOFTWARE ((uint32_t)0x00000001U) /* !< Event handled by software. Software
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must clear the associated RIS flag. */
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#define CPUSS_EVT_MODE_INT_CFG_HARDWARE ((uint32_t)0x00000002U) /* !< Event handled by hardware. The
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hardware (another module) clears
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automatically the associated RIS
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flag. */
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/* CPUSS_DESC Bits */
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/* CPUSS_DESC[MINREV] Bits */
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#define CPUSS_DESC_MINREV_OFS (0) /* !< MINREV Offset */
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#define CPUSS_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */
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/* CPUSS_DESC[MAJREV] Bits */
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#define CPUSS_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */
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#define CPUSS_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */
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/* CPUSS_DESC[FEATUREVER] Bits */
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#define CPUSS_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */
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#define CPUSS_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module
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*instance* */
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/* CPUSS_DESC[MODULEID] Bits */
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#define CPUSS_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */
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#define CPUSS_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module identification contains a
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unique peripheral identification
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number. The assignments are
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maintained in a central database for
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all of the platform modules to ensure
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uniqueness. */
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/* CPUSS_CTL Bits */
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/* CPUSS_CTL[PREFETCH] Bits */
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#define CPUSS_CTL_PREFETCH_OFS (0) /* !< PREFETCH Offset */
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#define CPUSS_CTL_PREFETCH_MASK ((uint32_t)0x00000001U) /* !< Used to enable/disable instruction
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prefetch to Flash. */
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#define CPUSS_CTL_PREFETCH_DISABLE ((uint32_t)0x00000000U) /* !< Disable instruction prefetch. */
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#define CPUSS_CTL_PREFETCH_ENABLE ((uint32_t)0x00000001U) /* !< Enable instruction prefetch. */
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/* CPUSS_CTL[ICACHE] Bits */
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#define CPUSS_CTL_ICACHE_OFS (1) /* !< ICACHE Offset */
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#define CPUSS_CTL_ICACHE_MASK ((uint32_t)0x00000002U) /* !< Used to enable/disable Instruction
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caching on flash access. */
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#define CPUSS_CTL_ICACHE_DISABLE ((uint32_t)0x00000000U) /* !< Disable instruction caching. */
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#define CPUSS_CTL_ICACHE_ENABLE ((uint32_t)0x00000002U) /* !< Enable instruction caching. */
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/* CPUSS_CTL[LITEN] Bits */
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#define CPUSS_CTL_LITEN_OFS (2) /* !< LITEN Offset */
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#define CPUSS_CTL_LITEN_MASK ((uint32_t)0x00000004U) /* !< Literal caching and prefetch
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enable. This bit is a subset of
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ICACHE/PREFETCH bit i.e. literal
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caching or literal prefetching will
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only happen if ICACHE or PREFETCH
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bits have been set respectively When
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enabled, the cache and prefetcher
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structures inside CPUSS will cache
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and prefetch literals When disabled,
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the cache and prefetcher structures
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inside CPUSS will not cache and
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prefetch literals */
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#define CPUSS_CTL_LITEN_DISABLE ((uint32_t)0x00000000U) /* !< Literal caching disabled */
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#define CPUSS_CTL_LITEN_ENABLE ((uint32_t)0x00000004U) /* !< Literal caching enabled */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ti_devices_msp_peripherals_m0p_hw_cpuss__include */
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