SkyLi
181 lines
10 KiB
C
181 lines
10 KiB
C
/*****************************************************************************
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Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the
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distribution.
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Neither the name of Texas Instruments Incorporated nor the names of
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its contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#ifndef ti_devices_msp_peripherals_hw_iomux__include
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#define ti_devices_msp_peripherals_hw_iomux__include
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/* Filename: hw_iomux.h */
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/* Revised: 2023-05-10 21:32:43 */
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/* Revision: ccc8d5592eceba00f0e63b10bdaec9c7cd64733b */
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#ifndef __CORTEX_M
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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#endif
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/* Use standard integer types with explicit width */
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/******************************************************************************
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* IOMUX Registers
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******************************************************************************/
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#define IOMUX_SECCFG_OFS ((uint32_t)0x00000000U)
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/** @addtogroup IOMUX_SECCFG
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@{
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*/
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typedef struct {
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uint32_t RESERVED0;
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__IO uint32_t PINCM[251]; /* !< (@ 0x00000004) Pin Control Management Register in SECCFG region */
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} IOMUX_SECCFG_Regs;
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/*@}*/ /* end of group IOMUX_SECCFG */
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/** @addtogroup IOMUX
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@{
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*/
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typedef struct {
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IOMUX_SECCFG_Regs SECCFG; /* !< (@ 0x00000000) SECCFG register region */
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} IOMUX_Regs;
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/*@}*/ /* end of group IOMUX */
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#if defined ( __CC_ARM )
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#pragma no_anon_unions
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#endif
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/******************************************************************************
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* IOMUX Register Control Bits
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******************************************************************************/
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/* IOMUX_PINCM Bits */
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/* IOMUX_PINCM[PF] Bits */
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#define IOMUX_PINCM_PF_OFS (0) /* !< PF Offset */
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#define IOMUX_PINCM_PF_MASK ((uint32_t)0x0000003FU) /* !< Peripheral Function selection bits */
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#define IOMUX_PINCM_PF_MINIMUM ((uint32_t)0x00000000U) /* !< Reserved as unconnected */
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#define IOMUX_PINCM_PF_MAXIMUM ((uint32_t)0x0000003FU) /* !< An encoding per function that can
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be connected to this pin. */
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/* IOMUX_PINCM[PC] Bits */
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#define IOMUX_PINCM_PC_OFS (7) /* !< PC Offset */
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#define IOMUX_PINCM_PC_MASK ((uint32_t)0x00000080U) /* !< Peripheral is Connected */
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#define IOMUX_PINCM_PC_UNCONNECTED ((uint32_t)0x00000000U) /* !< The output of the peripheral (and
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its output enable) will not propagate
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to the IOCELL */
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#define IOMUX_PINCM_PC_CONNECTED ((uint32_t)0x00000080U) /* !< The output latch of the dataflow
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will be transparent */
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/* IOMUX_PINCM[WAKESTAT] Bits */
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#define IOMUX_PINCM_WAKESTAT_OFS (13) /* !< WAKESTAT Offset */
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#define IOMUX_PINCM_WAKESTAT_MASK ((uint32_t)0x00002000U) /* !< This has the IOPAD WAKEUP signal as
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status bit. */
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#define IOMUX_PINCM_WAKESTAT_DISABLE ((uint32_t)0x00000000U) /* !< wakeup source is NOT from this
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IOCELL */
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#define IOMUX_PINCM_WAKESTAT_ENABLE ((uint32_t)0x00002000U) /* !< wakeup source is from this IOCELL */
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/* IOMUX_PINCM[PIPD] Bits */
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#define IOMUX_PINCM_PIPD_OFS (16) /* !< PIPD Offset */
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#define IOMUX_PINCM_PIPD_MASK ((uint32_t)0x00010000U) /* !< Pull Down control selection */
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#define IOMUX_PINCM_PIPD_DISABLE ((uint32_t)0x00000000U) /* !< Pull down is disabled. */
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#define IOMUX_PINCM_PIPD_ENABLE ((uint32_t)0x00010000U) /* !< Pull down is enabled */
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/* IOMUX_PINCM[PIPU] Bits */
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#define IOMUX_PINCM_PIPU_OFS (17) /* !< PIPU Offset */
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#define IOMUX_PINCM_PIPU_MASK ((uint32_t)0x00020000U) /* !< Pull Up control selection */
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#define IOMUX_PINCM_PIPU_DISABLE ((uint32_t)0x00000000U) /* !< Pull up is disabled. */
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#define IOMUX_PINCM_PIPU_ENABLE ((uint32_t)0x00020000U) /* !< Pull up is enabled */
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/* IOMUX_PINCM[INENA] Bits */
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#define IOMUX_PINCM_INENA_OFS (18) /* !< INENA Offset */
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#define IOMUX_PINCM_INENA_MASK ((uint32_t)0x00040000U) /* !< Input Enable Control Selection */
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#define IOMUX_PINCM_INENA_DISABLE ((uint32_t)0x00000000U) /* !< Input enable is disabled. */
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#define IOMUX_PINCM_INENA_ENABLE ((uint32_t)0x00040000U) /* !< Input enable is enabled. */
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/* IOMUX_PINCM[HYSTEN] Bits */
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#define IOMUX_PINCM_HYSTEN_OFS (19) /* !< HYSTEN Offset */
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#define IOMUX_PINCM_HYSTEN_MASK ((uint32_t)0x00080000U) /* !< Hysteresis Enable Control Selection */
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#define IOMUX_PINCM_HYSTEN_ENABLE ((uint32_t)0x00000000U) /* !< hysteresis is enabled. */
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#define IOMUX_PINCM_HYSTEN_DISABLE ((uint32_t)0x00080000U) /* !< hysteresis is disabled */
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/* IOMUX_PINCM[DRV] Bits */
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#define IOMUX_PINCM_DRV_OFS (20) /* !< DRV Offset */
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#define IOMUX_PINCM_DRV_MASK ((uint32_t)0x00100000U) /* !< Drive strength control selection,
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for HS IOCELL only */
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#define IOMUX_PINCM_DRV_DRVVAL0 ((uint32_t)0x00000000U) /* !< Drive setting of 0 selected */
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#define IOMUX_PINCM_DRV_DRVVAL1 ((uint32_t)0x00100000U) /* !< Drive setting of 1 selected */
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/* IOMUX_PINCM[HIZ1] Bits */
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#define IOMUX_PINCM_HIZ1_OFS (25) /* !< HIZ1 Offset */
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#define IOMUX_PINCM_HIZ1_MASK ((uint32_t)0x02000000U) /* !< High output value will tri-state
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the output when this bit is enabled */
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#define IOMUX_PINCM_HIZ1_DISABLE ((uint32_t)0x00000000U) /* !< open-drain is disabled. */
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#define IOMUX_PINCM_HIZ1_ENABLE ((uint32_t)0x02000000U) /* !< open-drain is enabled. */
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/* IOMUX_PINCM[WUEN] Bits */
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#define IOMUX_PINCM_WUEN_OFS (27) /* !< WUEN Offset */
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#define IOMUX_PINCM_WUEN_MASK ((uint32_t)0x08000000U) /* !< Wakeup Enable bit */
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#define IOMUX_PINCM_WUEN_DISABLE ((uint32_t)0x00000000U) /* !< wakeup is disabled. */
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#define IOMUX_PINCM_WUEN_ENABLE ((uint32_t)0x08000000U) /* !< wakeup is enabled */
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/* IOMUX_PINCM[WCOMP] Bits */
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#define IOMUX_PINCM_WCOMP_OFS (28) /* !< WCOMP Offset */
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#define IOMUX_PINCM_WCOMP_MASK ((uint32_t)0x10000000U) /* !< Wakeup Compare Value bit */
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#define IOMUX_PINCM_WCOMP_MATCH0 ((uint32_t)0x00000000U) /* !< Wakeup on a match of 0 */
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#define IOMUX_PINCM_WCOMP_MATCH1 ((uint32_t)0x10000000U) /* !< Wakeup on a match of 1 */
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/* IOMUX_PINCM[INV] Bits */
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#define IOMUX_PINCM_INV_OFS (26) /* !< INV Offset */
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#define IOMUX_PINCM_INV_MASK ((uint32_t)0x04000000U) /* !< Data inversion selection */
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#define IOMUX_PINCM_INV_DISABLE ((uint32_t)0x00000000U) /* !< Data inversion is disabled. */
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#define IOMUX_PINCM_INV_ENABLE ((uint32_t)0x04000000U) /* !< Data inversion is enabled */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ti_devices_msp_peripherals_hw_iomux__include */
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