SkyLi
354 lines
13 KiB
C
354 lines
13 KiB
C
/*
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* Copyright (c) 2020, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*!****************************************************************************
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* @file dl_interrupt.h
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* @brief Interrupt Management Driver Library
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* @defgroup INTERRUPT M0P Interrupts
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*
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* @anchor ti_dl_m0p_dl_interrupt_Overview
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* # Overview
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*
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* The Cortex-M0+ architecture is limited to 32 device interrupts. To enable
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* interrupt handling on devices that need more than 32 interrupts, the
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* interrupts are grouped together.
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*
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* For example, "Group 0" contains the interrupt flags for the WWDT0, WWDT1,
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* DEBUGSS, FLASH, and SYSCTL peripherals. Once the interrupt fires for Group 0,
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* the application must check to see which peripheral from Group 0 was the
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* source using the APIs in this module.
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*
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* This PI module is not for controlling the NVIC or the I-bit in the CPSR
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* register. It's best to use the CMSIS-Core APIs that are delivered as part
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* of CMSIS-Core in the `source/third_party/CMSIS/Core/Include/core_cm0plus.h`
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* file within the SDK.
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*
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* <hr>
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******************************************************************************
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*/
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/** @addtogroup INTERRUPT
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* @{
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*/
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#ifndef ti_dl_m0p_dl_interrupt__include
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#define ti_dl_m0p_dl_interrupt__include
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#include <stdint.h>
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#include <ti/devices/msp/msp.h>
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#include <ti/devices/msp/peripherals/m0p/hw_cpuss.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* clang-format off */
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/** @addtogroup DL_INTERRUPT_GROUP_IIDX
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* @{
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*/
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/*!
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* @brief WWDT0 Interrupt in Group 0
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*/
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#define DL_INTERRUPT_GROUP0_IIDX_WWDT0 (CPUSS_INT_GROUP_IIDX_STAT_INT0)
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/*!
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* @brief WWDT1 Interrupt in Group 0.
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* @note This is a device specific interrupt. Please consult the device TRM to
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* determine if the interrupt is enabled as part of Group 0 interrupts.
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*/
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#define DL_INTERRUPT_GROUP0_IIDX_WWDT1 (CPUSS_INT_GROUP_IIDX_STAT_INT1)
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/*!
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* @brief DEBUGSS Interrupt in Group 0
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*/
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#define DL_INTERRUPT_GROUP0_IIDX_DEBUGSS (CPUSS_INT_GROUP_IIDX_STAT_INT2)
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/*!
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* @brief FLASH Interrupt in Group 0
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*/
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#define DL_INTERRUPT_GROUP0_IIDX_FLASH (CPUSS_INT_GROUP_IIDX_STAT_INT3)
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/*!
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* @brief WUC FSUB0 Interrupt in Group 0
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*/
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#define DL_INTERRUPT_GROUP0_IIDX_WUC_FSUB0 (CPUSS_INT_GROUP_IIDX_STAT_INT4)
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/*!
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* @brief WUC FSUB0 Interrupt in Group 1
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*/
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#define DL_INTERRUPT_GROUP0_IIDX_WUC_FSUB1 (CPUSS_INT_GROUP_IIDX_STAT_INT5)
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/*!
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* @brief SYSCTL (PMCU) Interrupt in Group 0
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*/
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#define DL_INTERRUPT_GROUP0_IIDX_SYSCTL (CPUSS_INT_GROUP_IIDX_STAT_INT6)
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/*!
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* @brief GPIOA Interrupt in Group 1
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*/
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#define DL_INTERRUPT_GROUP1_IIDX_GPIOA (CPUSS_INT_GROUP_IIDX_STAT_INT0)
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/*!
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* @brief GPIOB Interrupt in Group 1
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* @note This is a device specific interrupt. Please consult the device TRM to
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* determine if the interrupt is enabled as part of Group 1 interrupts.
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*/
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#define DL_INTERRUPT_GROUP1_IIDX_GPIOB (CPUSS_INT_GROUP_IIDX_STAT_INT1)
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/*!
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* @brief COMP0 Interrupt in Group 1
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*/
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#define DL_INTERRUPT_GROUP1_IIDX_COMP0 (CPUSS_INT_GROUP_IIDX_STAT_INT2)
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/*!
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* @brief COMP1 Interrupt in Group 1
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* @note This is a device specific interrupt. Please consult the device TRM to
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* determine if the interrupt is enabled as part of Group 1 interrupts.
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*/
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#define DL_INTERRUPT_GROUP1_IIDX_COMP1 (CPUSS_INT_GROUP_IIDX_STAT_INT3)
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/*!
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* @brief COMP2 Interrupt in Group 1
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* @note This is a device specific interrupt. Please consult the device TRM to
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* determine if the interrupt is enabled as part of Group 1 interrupts.
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*/
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#define DL_INTERRUPT_GROUP1_IIDX_COMP2 (CPUSS_INT_GROUP_IIDX_STAT_INT4)
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/*!
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* @brief TRNG Interrupt in Group 1
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* @note This is a device specific interrupt. Please consult the device TRM to
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* determine if the interrupt is enabled as part of Group 1 interrupts.
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*/
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#define DL_INTERRUPT_GROUP1_IIDX_TRNG (CPUSS_INT_GROUP_IIDX_STAT_INT5)
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/*!
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* @brief GPIOC Interrupt in Group 1
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* @note This is a device specific interrupt. Please consult the device TRM to
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* determine if the interrupt is enabled as part of Group 1 interrupts.
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*/
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#define DL_INTERRUPT_GROUP1_IIDX_GPIOC (CPUSS_INT_GROUP_IIDX_STAT_INT6)
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/** @}*/
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/** @addtogroup DL_INTERRUPT_GROUP_INTERRUPTS
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* @{
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*/
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/*!
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* @brief WWDT0 Interrupt in Group 0
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*/
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#define DL_INTERRUPT_GROUP0_WWDT0 (CPUSS_INT_GROUP_IMASK_INT_INT0)
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/*!
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* @brief WWDT1 Interrupt in Group 0
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*/
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#define DL_INTERRUPT_GROUP0_WWDT1 (CPUSS_INT_GROUP_IMASK_INT_INT1)
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/*!
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* @brief DEBUGSS Interrupt in Group 0
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*/
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#define DL_INTERRUPT_GROUP0_DEBUGSS (CPUSS_INT_GROUP_IMASK_INT_INT2)
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/*!
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* @brief FLASH Interrupt in Group 0
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*/
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#define DL_INTERRUPT_GROUP0_FLASH (CPUSS_INT_GROUP_IMASK_INT_INT3)
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/*!
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* @brief Generic event subscriber 0 in Group 0
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*/
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#define DL_INTERRUPT_GROUP0_WUC_FSUB0 (CPUSS_INT_GROUP_IMASK_INT_INT4)
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/*!
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* @brief Generic event subscriber 1 in Group 0
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*/
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#define DL_INTERRUPT_GROUP0_WUC_FSUB1 (CPUSS_INT_GROUP_IMASK_INT_INT5)
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/*!
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* @brief PMCU (system controller) in Group 0
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*/
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#define DL_INTERRUPT_GROUP0_PMCU (CPUSS_INT_GROUP_IMASK_INT_INT6)
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/*!
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* @brief GPIOA Interrupt in Group 1
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*/
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#define DL_INTERRUPT_GROUP1_GPIOA (CPUSS_INT_GROUP_IMASK_INT_INT0)
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/*!
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* @brief GPIOB Interrupt in Group 1
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* @note This is a device specific interrupt. Please consult the device TRM to
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* determine if the interrupt is enabled as part of Group 1 interrupts.
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*/
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#define DL_INTERRUPT_GROUP1_GPIOB (CPUSS_INT_GROUP_IMASK_INT_INT1)
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/*!
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* @brief COMP0 Interrupt in Group 1
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* @note This is a device specific interrupt. Please consult the device TRM to
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* determine if the interrupt is enabled as part of Group 1 interrupts.
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*/
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#define DL_INTERRUPT_GROUP1_COMP0 (CPUSS_INT_GROUP_IMASK_INT_INT2)
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/*!
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* @brief COMP1 Interrupt in Group 1
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* @note This is a device specific interrupt. Please consult the device TRM to
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* determine if the interrupt is enabled as part of Group 1 interrupts.
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*/
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#define DL_INTERRUPT_GROUP1_COMP1 (CPUSS_INT_GROUP_IMASK_INT_INT3)
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/*!
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* @brief COMP2 Interrupt in Group 1
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* @note This is a device specific interrupt. Please consult the device TRM to
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* determine if the interrupt is enabled as part of Group 1 interrupts.
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*/
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#define DL_INTERRUPT_GROUP1_COMP2 (CPUSS_INT_GROUP_IMASK_INT_INT4)
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/*!
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* @brief TRNG Interrupt in Group 1
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* @note This is a device specific interrupt. Please consult the device TRM to
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* determine if the interrupt is enabled as part of Group 1 interrupts.
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*/
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#define DL_INTERRUPT_GROUP1_TRNG (CPUSS_INT_GROUP_IMASK_INT_INT5)
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/** @}*/
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/* clang-format on */
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/*! @enum DL_INTERRUPT_GROUP */
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typedef enum {
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/*! Selects interrupt group 0 */
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DL_INTERRUPT_GROUP_0 = 0,
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/*! Selects interrupt group 1 */
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DL_INTERRUPT_GROUP_1 = 1
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} DL_INTERRUPT_GROUP;
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/**
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* @brief Device default Handler
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*
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* This function is defined as part of the device startup file.
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*/
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extern void Default_Handler(void);
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/**
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* @brief Checks interrupt flag status in the selected group of interrupts
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*
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* Checks if any of the interrupts in the group are pending. When calling the
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* function, ensure that the interrupts passed in the mask are applicable to
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* the requested interrupt group.
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*
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* @param[in] group Group of interrupts to check.
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* @ref DL_INTERRUPT_GROUP
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* @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of
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* @ref DL_INTERRUPT_GROUP_INTERRUPTS.
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*
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* @return Which of the requested group interrupts are pending
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*
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* @retval Bitwise OR of @ref DL_INTERRUPT_GROUP_INTERRUPTS values
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*/
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static inline uint32_t DL_Interrupt_getStatusGroup(
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DL_INTERRUPT_GROUP group, uint32_t interruptMask)
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{
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return (CPUSS->INT_GROUP[(uint32_t) group].RIS & interruptMask);
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}
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/**
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* @brief Get highest priority interrupt pending in the selected interrupt
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* group
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*
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* @param[in] group Group of interrupts to check
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*
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* @return The highest priority pending interrupt for the group requested.
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* One of @ref DL_INTERRUPT_GROUP_IIDX
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*/
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__STATIC_INLINE uint32_t DL_Interrupt_getPendingGroup(DL_INTERRUPT_GROUP group)
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{
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return (CPUSS->INT_GROUP[group].IIDX);
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}
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/**
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* @brief Clear selected interrupt flags in the selected interrupt group
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*
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* Clears any of the desired interrupts in the group. When calling the
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* function, ensure that the interrupts passed in the mask are applicable to
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* the requested interrupt group.
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*
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* @param[in] group Group of interrupts to check.
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* @ref DL_INTERRUPT_GROUP
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* @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of
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* @ref DL_INTERRUPT_GROUP_INTERRUPTS.
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*/
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static inline void DL_Interrupt_clearGroup(
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DL_INTERRUPT_GROUP group, uint32_t interruptMask)
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{
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CPUSS->INT_GROUP[(uint32_t) group].ICLR |= interruptMask;
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}
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/**
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* @brief Register a function to be called when an interrupt occurs
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*
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* This allows you to register a function to be called during an interrupt,
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* allowing you to override the interrupt handler at run time. The function
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* moves the interrupt vector table from Flash to SRAM so that the interrupt
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* handler functions can be overwritten.
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*
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* This function should only be used if the application requires specifying
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* the interrupt handler at run time. If it does not need to be changed at
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* run time consider placing the ISR function pointer in the startup file to
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* link the function into the interrupt table.
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*
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* Example of usage:
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* @code
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* DL_Interrupt_registerInterrupt(TIMA0_INT_IRQn, redirectedInterruptHandler);
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* @endcode
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*
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* @param[in] exceptionNumber The interrupt number to register the handler.
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* Interrupt numbers are device specific, please
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* consult the device datasheet for valid
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* interrupt numbers.
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* @param[in] intHandler A pointer to a function to call for the desired
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* interrupt
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*/
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void DL_Interrupt_registerInterrupt(
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uint32_t exceptionNumber, void (*intHandler)(void));
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/**
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* @brief Unregister a function to be called when an interrupt occurs
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*
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* Overrides the registered interrupt function to jump into a simple while(1)
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* loop rather than the previously registered interrupt function. Requires
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* that @ref DL_Interrupt_registerInterrupt was previously called so that the
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* interrupt vector table has been moved to RAM.
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*
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* Example of usage:
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* @code DL_Interrupt_unregisterInterrupt(TIMA0_INT_IRQn); @endcode
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*
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* @param[in] exceptionNumber The interrupt number to unregister.
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* Interrupt numbers are device specific, please
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* consult the device datasheet for valid
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* interrupt numbers.
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*/
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void DL_Interrupt_unregisterInterrupt(uint32_t exceptionNumber);
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#ifdef __cplusplus
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}
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#endif
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#endif /* ti_dl_m0p_dl_interrupt__include */
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/** @}*/
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