第一次提交
This commit is contained in:
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/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file adc.c
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* @brief This file provides code for the configuration
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* of the ADC instances.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2024 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Includes ------------------------------------------------------------------*/
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#include "adc.h"
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/* USER CODE BEGIN 0 */
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/* USER CODE END 0 */
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ADC_HandleTypeDef hadc1;
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DMA_HandleTypeDef hdma_adc1;
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/* ADC1 init function */
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void MX_ADC1_Init(void)
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{
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/* USER CODE BEGIN ADC1_Init 0 */
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/* USER CODE END ADC1_Init 0 */
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ADC_MultiModeTypeDef multimode = {0};
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ADC_ChannelConfTypeDef sConfig = {0};
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/* USER CODE BEGIN ADC1_Init 1 */
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/* USER CODE END ADC1_Init 1 */
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/** Common config
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*/
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hadc1.Instance = ADC1;
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hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV64;
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hadc1.Init.Resolution = ADC_RESOLUTION_16B;
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hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
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hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
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hadc1.Init.LowPowerAutoWait = DISABLE;
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hadc1.Init.ContinuousConvMode = ENABLE;
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hadc1.Init.NbrOfConversion = 2;
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hadc1.Init.DiscontinuousConvMode = DISABLE;
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hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
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hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
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hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_CIRCULAR;
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hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
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hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
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hadc1.Init.OversamplingMode = DISABLE;
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hadc1.Init.Oversampling.Ratio = 1;
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if (HAL_ADC_Init(&hadc1) != HAL_OK)
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{
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Error_Handler();
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}
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/** Configure the ADC multi-mode
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*/
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multimode.Mode = ADC_MODE_INDEPENDENT;
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if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
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{
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Error_Handler();
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}
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/** Configure Regular Channel
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*/
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sConfig.Channel = ADC_CHANNEL_4;
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sConfig.Rank = ADC_REGULAR_RANK_1;
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sConfig.SamplingTime = ADC_SAMPLETIME_32CYCLES_5;
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sConfig.SingleDiff = ADC_SINGLE_ENDED;
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sConfig.OffsetNumber = ADC_OFFSET_NONE;
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sConfig.Offset = 0;
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sConfig.OffsetSignedSaturation = DISABLE;
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if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
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{
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Error_Handler();
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}
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/** Configure Regular Channel
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*/
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sConfig.Channel = ADC_CHANNEL_19;
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sConfig.Rank = ADC_REGULAR_RANK_2;
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if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
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{
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Error_Handler();
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}
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/* USER CODE BEGIN ADC1_Init 2 */
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/* USER CODE END ADC1_Init 2 */
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}
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void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
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{
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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if(adcHandle->Instance==ADC1)
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{
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/* USER CODE BEGIN ADC1_MspInit 0 */
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/* USER CODE END ADC1_MspInit 0 */
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/** Initializes the peripherals clock
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*/
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;
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PeriphClkInitStruct.PLL2.PLL2M = 2;
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PeriphClkInitStruct.PLL2.PLL2N = 16;
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PeriphClkInitStruct.PLL2.PLL2P = 2;
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PeriphClkInitStruct.PLL2.PLL2Q = 2;
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PeriphClkInitStruct.PLL2.PLL2R = 2;
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PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
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PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
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PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
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PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/* ADC1 clock enable */
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__HAL_RCC_ADC12_CLK_ENABLE();
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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/**ADC1 GPIO Configuration
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PA5 ------> ADC1_INP19
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PC4 ------> ADC1_INP4
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*/
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GPIO_InitStruct.Pin = GPIO_PIN_5;
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GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = GPIO_PIN_4;
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GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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/* ADC1 DMA Init */
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/* ADC1 Init */
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hdma_adc1.Instance = DMA1_Stream0;
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hdma_adc1.Init.Request = DMA_REQUEST_ADC1;
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hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
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hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
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hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
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hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
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hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
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hdma_adc1.Init.Mode = DMA_CIRCULAR;
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hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
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hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
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if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
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{
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Error_Handler();
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}
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__HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1);
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/* USER CODE BEGIN ADC1_MspInit 1 */
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/* USER CODE END ADC1_MspInit 1 */
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}
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}
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void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)
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{
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if(adcHandle->Instance==ADC1)
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{
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/* USER CODE BEGIN ADC1_MspDeInit 0 */
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/* USER CODE END ADC1_MspDeInit 0 */
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/* Peripheral clock disable */
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__HAL_RCC_ADC12_CLK_DISABLE();
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/**ADC1 GPIO Configuration
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PA5 ------> ADC1_INP19
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PC4 ------> ADC1_INP4
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*/
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HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5);
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HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4);
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/* ADC1 DMA DeInit */
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HAL_DMA_DeInit(adcHandle->DMA_Handle);
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/* USER CODE BEGIN ADC1_MspDeInit 1 */
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/* USER CODE END ADC1_MspDeInit 1 */
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}
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}
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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+101
@@ -0,0 +1,101 @@
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/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file dma.c
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* @brief This file provides code for the configuration
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* of all the requested memory to memory DMA transfers.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2024 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Includes ------------------------------------------------------------------*/
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#include "dma.h"
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/* USER CODE BEGIN 0 */
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/* USER CODE END 0 */
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/*----------------------------------------------------------------------------*/
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/* Configure DMA */
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/*----------------------------------------------------------------------------*/
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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/**
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* Enable DMA controller clock
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*/
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void MX_DMA_Init(void)
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{
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/* DMA controller clock enable */
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__HAL_RCC_DMA1_CLK_ENABLE();
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__HAL_RCC_DMA2_CLK_ENABLE();
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/* DMA interrupt init */
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/* DMA1_Stream0_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
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/* DMA1_Stream1_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
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/* DMA1_Stream2_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
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/* DMA1_Stream3_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn);
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/* DMA1_Stream4_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn);
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/* DMA1_Stream5_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn);
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/* DMA1_Stream6_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn);
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/* DMA1_Stream7_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn);
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/* DMA2_Stream0_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
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/* DMA2_Stream1_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);
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/* DMA2_Stream2_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
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/* DMA2_Stream3_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);
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/* DMA2_Stream4_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream4_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream4_IRQn);
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/* DMA2_Stream5_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn);
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/* DMA2_Stream6_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn);
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/* DMA2_Stream7_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
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}
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/* USER CODE BEGIN 2 */
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/* USER CODE END 2 */
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@@ -0,0 +1,391 @@
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/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file fdcan.c
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* @brief This file provides code for the configuration
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* of the FDCAN instances.
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******************************************************************************
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* @attention
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*
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||||
* Copyright (c) 2024 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
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/* USER CODE END Header */
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/* Includes ------------------------------------------------------------------*/
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#include "fdcan.h"
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/* USER CODE BEGIN 0 */
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/* USER CODE END 0 */
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FDCAN_HandleTypeDef hfdcan1;
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FDCAN_HandleTypeDef hfdcan2;
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FDCAN_HandleTypeDef hfdcan3;
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/* FDCAN1 init function */
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void MX_FDCAN1_Init(void)
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{
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/* USER CODE BEGIN FDCAN1_Init 0 */
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/* USER CODE END FDCAN1_Init 0 */
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/* USER CODE BEGIN FDCAN1_Init 1 */
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/* USER CODE END FDCAN1_Init 1 */
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hfdcan1.Instance = FDCAN1;
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hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
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hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
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hfdcan1.Init.AutoRetransmission = DISABLE;
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hfdcan1.Init.TransmitPause = DISABLE;
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hfdcan1.Init.ProtocolException = ENABLE;
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hfdcan1.Init.NominalPrescaler = 3;
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hfdcan1.Init.NominalSyncJumpWidth = 1;
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hfdcan1.Init.NominalTimeSeg1 = 29;
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hfdcan1.Init.NominalTimeSeg2 = 10;
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hfdcan1.Init.DataPrescaler = 3;
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hfdcan1.Init.DataSyncJumpWidth = 10;
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hfdcan1.Init.DataTimeSeg1 = 29;
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hfdcan1.Init.DataTimeSeg2 = 10;
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hfdcan1.Init.MessageRAMOffset = 0;
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hfdcan1.Init.StdFiltersNbr = 14;
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hfdcan1.Init.ExtFiltersNbr = 0;
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hfdcan1.Init.RxFifo0ElmtsNbr = 4;
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hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
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hfdcan1.Init.RxFifo1ElmtsNbr = 4;
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hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
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hfdcan1.Init.RxBuffersNbr = 0;
|
||||
hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
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hfdcan1.Init.TxEventsNbr = 0;
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||||
hfdcan1.Init.TxBuffersNbr = 0;
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||||
hfdcan1.Init.TxFifoQueueElmtsNbr = 4;
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||||
hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
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||||
hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
|
||||
if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN FDCAN1_Init 2 */
|
||||
|
||||
/* USER CODE END FDCAN1_Init 2 */
|
||||
|
||||
}
|
||||
/* FDCAN2 init function */
|
||||
void MX_FDCAN2_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN FDCAN2_Init 0 */
|
||||
|
||||
/* USER CODE END FDCAN2_Init 0 */
|
||||
|
||||
/* USER CODE BEGIN FDCAN2_Init 1 */
|
||||
|
||||
/* USER CODE END FDCAN2_Init 1 */
|
||||
hfdcan2.Instance = FDCAN2;
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||||
hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
|
||||
hfdcan2.Init.Mode = FDCAN_MODE_NORMAL;
|
||||
hfdcan2.Init.AutoRetransmission = DISABLE;
|
||||
hfdcan2.Init.TransmitPause = DISABLE;
|
||||
hfdcan2.Init.ProtocolException = DISABLE;
|
||||
hfdcan2.Init.NominalPrescaler = 3;
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||||
hfdcan2.Init.NominalSyncJumpWidth = 1;
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||||
hfdcan2.Init.NominalTimeSeg1 = 29;
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||||
hfdcan2.Init.NominalTimeSeg2 = 10;
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||||
hfdcan2.Init.DataPrescaler = 3;
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||||
hfdcan2.Init.DataSyncJumpWidth = 10;
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||||
hfdcan2.Init.DataTimeSeg1 = 29;
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||||
hfdcan2.Init.DataTimeSeg2 = 10;
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||||
hfdcan2.Init.MessageRAMOffset = 0x406;
|
||||
hfdcan2.Init.StdFiltersNbr = 14;
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||||
hfdcan2.Init.ExtFiltersNbr = 0;
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||||
hfdcan2.Init.RxFifo0ElmtsNbr = 4;
|
||||
hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
|
||||
hfdcan2.Init.RxFifo1ElmtsNbr = 4;
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||||
hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
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||||
hfdcan2.Init.RxBuffersNbr = 0;
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||||
hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
|
||||
hfdcan2.Init.TxEventsNbr = 0;
|
||||
hfdcan2.Init.TxBuffersNbr = 0;
|
||||
hfdcan2.Init.TxFifoQueueElmtsNbr = 4;
|
||||
hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
|
||||
hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
|
||||
if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN FDCAN2_Init 2 */
|
||||
|
||||
/* USER CODE END FDCAN2_Init 2 */
|
||||
|
||||
}
|
||||
/* FDCAN3 init function */
|
||||
void MX_FDCAN3_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN FDCAN3_Init 0 */
|
||||
|
||||
/* USER CODE END FDCAN3_Init 0 */
|
||||
|
||||
/* USER CODE BEGIN FDCAN3_Init 1 */
|
||||
|
||||
/* USER CODE END FDCAN3_Init 1 */
|
||||
hfdcan3.Instance = FDCAN3;
|
||||
hfdcan3.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
|
||||
hfdcan3.Init.Mode = FDCAN_MODE_NORMAL;
|
||||
hfdcan3.Init.AutoRetransmission = DISABLE;
|
||||
hfdcan3.Init.TransmitPause = DISABLE;
|
||||
hfdcan3.Init.ProtocolException = DISABLE;
|
||||
hfdcan3.Init.NominalPrescaler = 3;
|
||||
hfdcan3.Init.NominalSyncJumpWidth = 1;
|
||||
hfdcan3.Init.NominalTimeSeg1 = 29;
|
||||
hfdcan3.Init.NominalTimeSeg2 = 10;
|
||||
hfdcan3.Init.DataPrescaler = 3;
|
||||
hfdcan3.Init.DataSyncJumpWidth = 10;
|
||||
hfdcan3.Init.DataTimeSeg1 = 29;
|
||||
hfdcan3.Init.DataTimeSeg2 = 10;
|
||||
hfdcan3.Init.MessageRAMOffset = 0x812;
|
||||
hfdcan3.Init.StdFiltersNbr = 14;
|
||||
hfdcan3.Init.ExtFiltersNbr = 0;
|
||||
hfdcan3.Init.RxFifo0ElmtsNbr = 4;
|
||||
hfdcan3.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
|
||||
hfdcan3.Init.RxFifo1ElmtsNbr = 4;
|
||||
hfdcan3.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
|
||||
hfdcan3.Init.RxBuffersNbr = 0;
|
||||
hfdcan3.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
|
||||
hfdcan3.Init.TxEventsNbr = 0;
|
||||
hfdcan3.Init.TxBuffersNbr = 0;
|
||||
hfdcan3.Init.TxFifoQueueElmtsNbr = 4;
|
||||
hfdcan3.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
|
||||
hfdcan3.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
|
||||
if (HAL_FDCAN_Init(&hfdcan3) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN FDCAN3_Init 2 */
|
||||
|
||||
/* USER CODE END FDCAN3_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
static uint32_t HAL_RCC_FDCAN_CLK_ENABLED=0;
|
||||
|
||||
void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* fdcanHandle)
|
||||
{
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
if(fdcanHandle->Instance==FDCAN1)
|
||||
{
|
||||
/* USER CODE BEGIN FDCAN1_MspInit 0 */
|
||||
|
||||
/* USER CODE END FDCAN1_MspInit 0 */
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
|
||||
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* FDCAN1 clock enable */
|
||||
HAL_RCC_FDCAN_CLK_ENABLED++;
|
||||
if(HAL_RCC_FDCAN_CLK_ENABLED==1){
|
||||
__HAL_RCC_FDCAN_CLK_ENABLE();
|
||||
}
|
||||
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
/**FDCAN1 GPIO Configuration
|
||||
PD0 ------> FDCAN1_RX
|
||||
PD1 ------> FDCAN1_TX
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
|
||||
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
||||
|
||||
/* FDCAN1 interrupt Init */
|
||||
HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
|
||||
HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
|
||||
/* USER CODE BEGIN FDCAN1_MspInit 1 */
|
||||
|
||||
/* USER CODE END FDCAN1_MspInit 1 */
|
||||
}
|
||||
else if(fdcanHandle->Instance==FDCAN2)
|
||||
{
|
||||
/* USER CODE BEGIN FDCAN2_MspInit 0 */
|
||||
|
||||
/* USER CODE END FDCAN2_MspInit 0 */
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
|
||||
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* FDCAN2 clock enable */
|
||||
HAL_RCC_FDCAN_CLK_ENABLED++;
|
||||
if(HAL_RCC_FDCAN_CLK_ENABLED==1){
|
||||
__HAL_RCC_FDCAN_CLK_ENABLE();
|
||||
}
|
||||
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
/**FDCAN2 GPIO Configuration
|
||||
PB5 ------> FDCAN2_RX
|
||||
PB6 ------> FDCAN2_TX
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
/* FDCAN2 interrupt Init */
|
||||
HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
|
||||
HAL_NVIC_SetPriority(FDCAN2_IT1_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(FDCAN2_IT1_IRQn);
|
||||
/* USER CODE BEGIN FDCAN2_MspInit 1 */
|
||||
|
||||
/* USER CODE END FDCAN2_MspInit 1 */
|
||||
}
|
||||
else if(fdcanHandle->Instance==FDCAN3)
|
||||
{
|
||||
/* USER CODE BEGIN FDCAN3_MspInit 0 */
|
||||
|
||||
/* USER CODE END FDCAN3_MspInit 0 */
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
|
||||
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* FDCAN3 clock enable */
|
||||
HAL_RCC_FDCAN_CLK_ENABLED++;
|
||||
if(HAL_RCC_FDCAN_CLK_ENABLED==1){
|
||||
__HAL_RCC_FDCAN_CLK_ENABLE();
|
||||
}
|
||||
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
/**FDCAN3 GPIO Configuration
|
||||
PD12 ------> FDCAN3_RX
|
||||
PD13 ------> FDCAN3_TX
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF5_FDCAN3;
|
||||
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
||||
|
||||
/* FDCAN3 interrupt Init */
|
||||
HAL_NVIC_SetPriority(FDCAN3_IT0_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(FDCAN3_IT0_IRQn);
|
||||
HAL_NVIC_SetPriority(FDCAN3_IT1_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(FDCAN3_IT1_IRQn);
|
||||
/* USER CODE BEGIN FDCAN3_MspInit 1 */
|
||||
|
||||
/* USER CODE END FDCAN3_MspInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* fdcanHandle)
|
||||
{
|
||||
|
||||
if(fdcanHandle->Instance==FDCAN1)
|
||||
{
|
||||
/* USER CODE BEGIN FDCAN1_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END FDCAN1_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
HAL_RCC_FDCAN_CLK_ENABLED--;
|
||||
if(HAL_RCC_FDCAN_CLK_ENABLED==0){
|
||||
__HAL_RCC_FDCAN_CLK_DISABLE();
|
||||
}
|
||||
|
||||
/**FDCAN1 GPIO Configuration
|
||||
PD0 ------> FDCAN1_RX
|
||||
PD1 ------> FDCAN1_TX
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1);
|
||||
|
||||
/* FDCAN1 interrupt Deinit */
|
||||
HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn);
|
||||
HAL_NVIC_DisableIRQ(FDCAN1_IT1_IRQn);
|
||||
/* USER CODE BEGIN FDCAN1_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END FDCAN1_MspDeInit 1 */
|
||||
}
|
||||
else if(fdcanHandle->Instance==FDCAN2)
|
||||
{
|
||||
/* USER CODE BEGIN FDCAN2_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END FDCAN2_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
HAL_RCC_FDCAN_CLK_ENABLED--;
|
||||
if(HAL_RCC_FDCAN_CLK_ENABLED==0){
|
||||
__HAL_RCC_FDCAN_CLK_DISABLE();
|
||||
}
|
||||
|
||||
/**FDCAN2 GPIO Configuration
|
||||
PB5 ------> FDCAN2_RX
|
||||
PB6 ------> FDCAN2_TX
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5|GPIO_PIN_6);
|
||||
|
||||
/* FDCAN2 interrupt Deinit */
|
||||
HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn);
|
||||
HAL_NVIC_DisableIRQ(FDCAN2_IT1_IRQn);
|
||||
/* USER CODE BEGIN FDCAN2_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END FDCAN2_MspDeInit 1 */
|
||||
}
|
||||
else if(fdcanHandle->Instance==FDCAN3)
|
||||
{
|
||||
/* USER CODE BEGIN FDCAN3_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END FDCAN3_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
HAL_RCC_FDCAN_CLK_ENABLED--;
|
||||
if(HAL_RCC_FDCAN_CLK_ENABLED==0){
|
||||
__HAL_RCC_FDCAN_CLK_DISABLE();
|
||||
}
|
||||
|
||||
/**FDCAN3 GPIO Configuration
|
||||
PD12 ------> FDCAN3_RX
|
||||
PD13 ------> FDCAN3_TX
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_12|GPIO_PIN_13);
|
||||
|
||||
/* FDCAN3 interrupt Deinit */
|
||||
HAL_NVIC_DisableIRQ(FDCAN3_IT0_IRQn);
|
||||
HAL_NVIC_DisableIRQ(FDCAN3_IT1_IRQn);
|
||||
/* USER CODE BEGIN FDCAN3_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END FDCAN3_MspDeInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
@@ -0,0 +1,171 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* File Name : freertos.c
|
||||
* Description : Code for freertos applications
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2024 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "main.h"
|
||||
#include "cmsis_os.h"
|
||||
|
||||
/* Private includes ----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Includes */
|
||||
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PTD */
|
||||
|
||||
/* USER CODE END PTD */
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PD */
|
||||
|
||||
/* USER CODE END PD */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PM */
|
||||
|
||||
/* USER CODE END PM */
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Variables */
|
||||
|
||||
/* USER CODE END Variables */
|
||||
osThreadId defaultTaskHandle;
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* USER CODE BEGIN FunctionPrototypes */
|
||||
|
||||
/* USER CODE END FunctionPrototypes */
|
||||
|
||||
void StartDefaultTask(void const * argument);
|
||||
|
||||
extern void MX_USB_DEVICE_Init(void);
|
||||
void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */
|
||||
|
||||
/* GetIdleTaskMemory prototype (linked to static allocation support) */
|
||||
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );
|
||||
|
||||
/* GetTimerTaskMemory prototype (linked to static allocation support) */
|
||||
void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
|
||||
|
||||
/* Hook prototypes */
|
||||
void configureTimerForRunTimeStats(void);
|
||||
unsigned long getRunTimeCounterValue(void);
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
/* Functions needed when configGENERATE_RUN_TIME_STATS is on */
|
||||
__weak void configureTimerForRunTimeStats(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
__weak unsigned long getRunTimeCounterValue(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
/* USER CODE END 1 */
|
||||
|
||||
/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
|
||||
static StaticTask_t xIdleTaskTCBBuffer;
|
||||
static StackType_t xIdleStack[configMINIMAL_STACK_SIZE];
|
||||
|
||||
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
|
||||
{
|
||||
*ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer;
|
||||
*ppxIdleTaskStackBuffer = &xIdleStack[0];
|
||||
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
|
||||
/* place for user code */
|
||||
}
|
||||
/* USER CODE END GET_IDLE_TASK_MEMORY */
|
||||
|
||||
/* USER CODE BEGIN GET_TIMER_TASK_MEMORY */
|
||||
static StaticTask_t xTimerTaskTCBBuffer;
|
||||
static StackType_t xTimerStack[configTIMER_TASK_STACK_DEPTH];
|
||||
|
||||
void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
|
||||
{
|
||||
*ppxTimerTaskTCBBuffer = &xTimerTaskTCBBuffer;
|
||||
*ppxTimerTaskStackBuffer = &xTimerStack[0];
|
||||
*pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
|
||||
/* place for user code */
|
||||
}
|
||||
/* USER CODE END GET_TIMER_TASK_MEMORY */
|
||||
|
||||
/**
|
||||
* @brief FreeRTOS initialization
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void MX_FREERTOS_Init(void) {
|
||||
/* USER CODE BEGIN Init */
|
||||
|
||||
/* USER CODE END Init */
|
||||
|
||||
/* USER CODE BEGIN RTOS_MUTEX */
|
||||
/* add mutexes, ... */
|
||||
/* USER CODE END RTOS_MUTEX */
|
||||
|
||||
/* USER CODE BEGIN RTOS_SEMAPHORES */
|
||||
/* add semaphores, ... */
|
||||
/* USER CODE END RTOS_SEMAPHORES */
|
||||
|
||||
/* USER CODE BEGIN RTOS_TIMERS */
|
||||
/* start timers, add new ones, ... */
|
||||
/* USER CODE END RTOS_TIMERS */
|
||||
|
||||
/* USER CODE BEGIN RTOS_QUEUES */
|
||||
/* add queues, ... */
|
||||
/* USER CODE END RTOS_QUEUES */
|
||||
|
||||
/* Create the thread(s) */
|
||||
/* definition and creation of defaultTask */
|
||||
osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 128);
|
||||
defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
|
||||
|
||||
/* USER CODE BEGIN RTOS_THREADS */
|
||||
/* add threads, ... */
|
||||
/* USER CODE END RTOS_THREADS */
|
||||
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN Header_StartDefaultTask */
|
||||
/**
|
||||
* @brief Function implementing the defaultTask thread.
|
||||
* @param argument: Not used
|
||||
* @retval None
|
||||
*/
|
||||
/* USER CODE END Header_StartDefaultTask */
|
||||
void StartDefaultTask(void const * argument)
|
||||
{
|
||||
/* init code for USB_DEVICE */
|
||||
MX_USB_DEVICE_Init();
|
||||
/* USER CODE BEGIN StartDefaultTask */
|
||||
/* Infinite loop */
|
||||
for(;;)
|
||||
{
|
||||
osDelay(1);
|
||||
}
|
||||
/* USER CODE END StartDefaultTask */
|
||||
}
|
||||
|
||||
/* Private application code --------------------------------------------------*/
|
||||
/* USER CODE BEGIN Application */
|
||||
|
||||
/* USER CODE END Application */
|
||||
+131
@@ -0,0 +1,131 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file gpio.c
|
||||
* @brief This file provides code for the configuration
|
||||
* of all used GPIO pins.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2024 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "gpio.h"
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Configure GPIO */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
/** Configure pins as
|
||||
* Analog
|
||||
* Input
|
||||
* Output
|
||||
* EVENT_OUT
|
||||
* EXTI
|
||||
PA8 ------> RCC_MCO_1
|
||||
*/
|
||||
void MX_GPIO_Init(void)
|
||||
{
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
|
||||
/* GPIO Ports Clock Enable */
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
|
||||
/*Configure GPIO pin Output Level */
|
||||
HAL_GPIO_WritePin(GPIOC, POWER_24V_2_Pin|POWER_24V_1_Pin|POWER_5V_Pin|CS2_ACCEL_Pin
|
||||
|CS2_GYRO_Pin|DCMI_PWDN_Pin, GPIO_PIN_SET);
|
||||
|
||||
/*Configure GPIO pin Output Level */
|
||||
HAL_GPIO_WritePin(LCD_CS_GPIO_Port, LCD_CS_Pin, GPIO_PIN_RESET);
|
||||
|
||||
/*Configure GPIO pin Output Level */
|
||||
HAL_GPIO_WritePin(DCMI_REST_GPIO_Port, DCMI_REST_Pin, GPIO_PIN_SET);
|
||||
|
||||
/*Configure GPIO pin Output Level */
|
||||
HAL_GPIO_WritePin(LCD_DC_GPIO_Port, LCD_DC_Pin, GPIO_PIN_RESET);
|
||||
|
||||
/*Configure GPIO pins : POWER_24V_2_Pin POWER_24V_1_Pin POWER_5V_Pin */
|
||||
GPIO_InitStruct.Pin = POWER_24V_2_Pin|POWER_24V_1_Pin|POWER_5V_Pin;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
||||
|
||||
/*Configure GPIO pins : CS2_ACCEL_Pin CS2_GYRO_Pin DCMI_PWDN_Pin */
|
||||
GPIO_InitStruct.Pin = CS2_ACCEL_Pin|CS2_GYRO_Pin|DCMI_PWDN_Pin;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
||||
|
||||
/*Configure GPIO pins : ACC_INT_Pin GYRO_INT_Pin */
|
||||
GPIO_InitStruct.Pin = ACC_INT_Pin|GYRO_INT_Pin;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
||||
|
||||
/*Configure GPIO pin : LCD_CS_Pin */
|
||||
GPIO_InitStruct.Pin = LCD_CS_Pin;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
HAL_GPIO_Init(LCD_CS_GPIO_Port, &GPIO_InitStruct);
|
||||
|
||||
/*Configure GPIO pin : DCMI_REST_Pin */
|
||||
GPIO_InitStruct.Pin = DCMI_REST_Pin;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
HAL_GPIO_Init(DCMI_REST_GPIO_Port, &GPIO_InitStruct);
|
||||
|
||||
/*Configure GPIO pin : LCD_DC_Pin */
|
||||
GPIO_InitStruct.Pin = LCD_DC_Pin;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
HAL_GPIO_Init(LCD_DC_GPIO_Port, &GPIO_InitStruct);
|
||||
|
||||
/*Configure GPIO pin : PA8 */
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_8;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/*Configure GPIO pin : PA15 */
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_15;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/*AnalogSwitch Config */
|
||||
HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_CLOSE);
|
||||
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 2 */
|
||||
|
||||
/* USER CODE END 2 */
|
||||
+190
@@ -0,0 +1,190 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file i2c.c
|
||||
* @brief This file provides code for the configuration
|
||||
* of the I2C instances.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2024 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "i2c.h"
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
I2C_HandleTypeDef hi2c2;
|
||||
DMA_HandleTypeDef hdma_i2c2_rx;
|
||||
DMA_HandleTypeDef hdma_i2c2_tx;
|
||||
|
||||
/* I2C2 init function */
|
||||
void MX_I2C2_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN I2C2_Init 0 */
|
||||
|
||||
/* USER CODE END I2C2_Init 0 */
|
||||
|
||||
/* USER CODE BEGIN I2C2_Init 1 */
|
||||
|
||||
/* USER CODE END I2C2_Init 1 */
|
||||
hi2c2.Instance = I2C2;
|
||||
hi2c2.Init.Timing = 0x307075B1;
|
||||
hi2c2.Init.OwnAddress1 = 0;
|
||||
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
||||
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
||||
hi2c2.Init.OwnAddress2 = 0;
|
||||
hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
|
||||
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
||||
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
||||
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Configure Analogue filter
|
||||
*/
|
||||
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Configure Digital filter
|
||||
*/
|
||||
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN I2C2_Init 2 */
|
||||
|
||||
/* USER CODE END I2C2_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
|
||||
{
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
if(i2cHandle->Instance==I2C2)
|
||||
{
|
||||
/* USER CODE BEGIN I2C2_MspInit 0 */
|
||||
|
||||
/* USER CODE END I2C2_MspInit 0 */
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C2;
|
||||
PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C1235CLKSOURCE_D2PCLK1;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
/**I2C2 GPIO Configuration
|
||||
PB10 ------> I2C2_SCL
|
||||
PB11 ------> I2C2_SDA
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
/* I2C2 clock enable */
|
||||
__HAL_RCC_I2C2_CLK_ENABLE();
|
||||
|
||||
/* I2C2 DMA Init */
|
||||
/* I2C2_RX Init */
|
||||
hdma_i2c2_rx.Instance = DMA1_Stream2;
|
||||
hdma_i2c2_rx.Init.Request = DMA_REQUEST_I2C2_RX;
|
||||
hdma_i2c2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
hdma_i2c2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
hdma_i2c2_rx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
hdma_i2c2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||
hdma_i2c2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||
hdma_i2c2_rx.Init.Mode = DMA_NORMAL;
|
||||
hdma_i2c2_rx.Init.Priority = DMA_PRIORITY_LOW;
|
||||
hdma_i2c2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
if (HAL_DMA_Init(&hdma_i2c2_rx) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
__HAL_LINKDMA(i2cHandle,hdmarx,hdma_i2c2_rx);
|
||||
|
||||
/* I2C2_TX Init */
|
||||
hdma_i2c2_tx.Instance = DMA1_Stream3;
|
||||
hdma_i2c2_tx.Init.Request = DMA_REQUEST_I2C2_TX;
|
||||
hdma_i2c2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||
hdma_i2c2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
hdma_i2c2_tx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
hdma_i2c2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||
hdma_i2c2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||
hdma_i2c2_tx.Init.Mode = DMA_NORMAL;
|
||||
hdma_i2c2_tx.Init.Priority = DMA_PRIORITY_LOW;
|
||||
hdma_i2c2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
if (HAL_DMA_Init(&hdma_i2c2_tx) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
__HAL_LINKDMA(i2cHandle,hdmatx,hdma_i2c2_tx);
|
||||
|
||||
/* I2C2 interrupt Init */
|
||||
HAL_NVIC_SetPriority(I2C2_EV_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(I2C2_EV_IRQn);
|
||||
/* USER CODE BEGIN I2C2_MspInit 1 */
|
||||
|
||||
/* USER CODE END I2C2_MspInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle)
|
||||
{
|
||||
|
||||
if(i2cHandle->Instance==I2C2)
|
||||
{
|
||||
/* USER CODE BEGIN I2C2_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END I2C2_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_I2C2_CLK_DISABLE();
|
||||
|
||||
/**I2C2 GPIO Configuration
|
||||
PB10 ------> I2C2_SCL
|
||||
PB11 ------> I2C2_SDA
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11);
|
||||
|
||||
/* I2C2 DMA DeInit */
|
||||
HAL_DMA_DeInit(i2cHandle->hdmarx);
|
||||
HAL_DMA_DeInit(i2cHandle->hdmatx);
|
||||
|
||||
/* I2C2 interrupt Deinit */
|
||||
HAL_NVIC_DisableIRQ(I2C2_EV_IRQn);
|
||||
/* USER CODE BEGIN I2C2_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END I2C2_MspDeInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
+262
@@ -0,0 +1,262 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file : main.c
|
||||
* @brief : Main program body
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2024 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "main.h"
|
||||
#include "adc.h"
|
||||
#include "dma.h"
|
||||
#include "fdcan.h"
|
||||
#include "i2c.h"
|
||||
#include "octospi.h"
|
||||
#include "spi.h"
|
||||
#include "tim.h"
|
||||
#include "usart.h"
|
||||
#include "usb_device.h"
|
||||
#include "gpio.h"
|
||||
|
||||
/* Private includes ----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Includes */
|
||||
#include "robot.h"
|
||||
#include "bsp_log.h"
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PTD */
|
||||
|
||||
/* USER CODE END PTD */
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PD */
|
||||
|
||||
/* USER CODE END PD */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PM */
|
||||
|
||||
/* USER CODE END PM */
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* USER CODE BEGIN PV */
|
||||
#define W25Qxx_NumByteToTest 32*1024 // �������ݵij��ȣ�32K
|
||||
|
||||
int32_t OSPI_Status ; //����־λ
|
||||
|
||||
uint8_t W25Qxx_WriteBuffer[W25Qxx_NumByteToTest]; // �������
|
||||
uint8_t W25Qxx_ReadBuffer[W25Qxx_NumByteToTest]; // ����������
|
||||
/* USER CODE END PV */
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
void SystemClock_Config(void);
|
||||
/* USER CODE BEGIN PFP */
|
||||
|
||||
/* USER CODE END PFP */
|
||||
|
||||
/* Private user code ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
/**
|
||||
* @brief The application entry point.
|
||||
* @retval int
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
/* MCU Configuration--------------------------------------------------------*/
|
||||
|
||||
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
||||
HAL_Init();
|
||||
|
||||
/* USER CODE BEGIN Init */
|
||||
|
||||
/* USER CODE END Init */
|
||||
|
||||
/* Configure the system clock */
|
||||
SystemClock_Config();
|
||||
|
||||
/* USER CODE BEGIN SysInit */
|
||||
|
||||
/* USER CODE END SysInit */
|
||||
|
||||
/* Initialize all configured peripherals */
|
||||
MX_GPIO_Init();
|
||||
MX_DMA_Init();
|
||||
MX_ADC1_Init();
|
||||
MX_USB_DEVICE_Init();
|
||||
MX_TIM12_Init();
|
||||
MX_SPI1_Init();
|
||||
MX_SPI2_Init();
|
||||
MX_TIM3_Init();
|
||||
MX_USART1_UART_Init();
|
||||
MX_USART2_UART_Init();
|
||||
MX_USART3_UART_Init();
|
||||
MX_UART7_Init();
|
||||
MX_USART10_UART_Init();
|
||||
MX_FDCAN1_Init();
|
||||
MX_FDCAN2_Init();
|
||||
MX_FDCAN3_Init();
|
||||
MX_TIM1_Init();
|
||||
MX_TIM2_Init();
|
||||
MX_OCTOSPI2_Init();
|
||||
MX_UART5_Init();
|
||||
MX_UART8_Init();
|
||||
MX_UART9_Init();
|
||||
MX_I2C2_Init();
|
||||
/* USER CODE BEGIN 2 */
|
||||
RobotInit(); // Ψһ�ij�ʼ������
|
||||
LOGINFO("[main] SystemInit() and RobotInit() done");
|
||||
/* USER CODE END 2 */
|
||||
|
||||
/* Infinite loop */
|
||||
/* USER CODE BEGIN WHILE */
|
||||
while (1)
|
||||
{
|
||||
// vofa_start();
|
||||
|
||||
/* USER CODE END WHILE */
|
||||
|
||||
/* USER CODE BEGIN 3 */
|
||||
}
|
||||
/* USER CODE END 3 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief System Clock Configuration
|
||||
* @retval None
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
|
||||
/** Supply configuration update enable
|
||||
*/
|
||||
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
|
||||
|
||||
/** Configure the main internal regulator output voltage
|
||||
*/
|
||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
|
||||
|
||||
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
|
||||
|
||||
/** Initializes the RCC Oscillators according to the specified parameters
|
||||
* in the RCC_OscInitTypeDef structure.
|
||||
*/
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI
|
||||
|RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_DIV1;
|
||||
RCC_OscInitStruct.HSICalibrationValue = 64;
|
||||
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLM = 2;
|
||||
RCC_OscInitStruct.PLL.PLLN = 40;
|
||||
RCC_OscInitStruct.PLL.PLLP = 1;
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2;
|
||||
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
|
||||
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
|
||||
RCC_OscInitStruct.PLL.PLLFRACN = 0;
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Initializes the CPU, AHB and APB buses clocks
|
||||
*/
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
||||
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|
||||
|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
|
||||
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
|
||||
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
|
||||
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1);
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 4 */
|
||||
|
||||
/* USER CODE END 4 */
|
||||
|
||||
/**
|
||||
* @brief Period elapsed callback in non blocking mode
|
||||
* @note This function is called when TIM23 interrupt took place, inside
|
||||
* HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
|
||||
* a global variable "uwTick" used as application time base.
|
||||
* @param htim : TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
||||
{
|
||||
/* USER CODE BEGIN Callback 0 */
|
||||
|
||||
/* USER CODE END Callback 0 */
|
||||
if (htim->Instance == TIM23)
|
||||
{
|
||||
HAL_IncTick();
|
||||
}
|
||||
/* USER CODE BEGIN Callback 1 */
|
||||
|
||||
/* USER CODE END Callback 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is executed in case of error occurrence.
|
||||
* @retval None
|
||||
*/
|
||||
void Error_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN Error_Handler_Debug */
|
||||
/* User can add his own implementation to report the HAL error return state */
|
||||
__disable_irq();
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
/* USER CODE END Error_Handler_Debug */
|
||||
}
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief Reports the name of the source file and the source line number
|
||||
* where the assert_param error has occurred.
|
||||
* @param file: pointer to the source file name
|
||||
* @param line: assert_param error line source number
|
||||
* @retval None
|
||||
*/
|
||||
void assert_failed(uint8_t *file, uint32_t line)
|
||||
{
|
||||
/* USER CODE BEGIN 6 */
|
||||
/* User can add his own implementation to report the file name and line number,
|
||||
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
|
||||
/* USER CODE END 6 */
|
||||
}
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
@@ -0,0 +1,207 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file octospi.c
|
||||
* @brief This file provides code for the configuration
|
||||
* of the OCTOSPI instances.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2024 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "octospi.h"
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
OSPI_HandleTypeDef hospi2;
|
||||
|
||||
/* OCTOSPI2 init function */
|
||||
void MX_OCTOSPI2_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN OCTOSPI2_Init 0 */
|
||||
|
||||
/* USER CODE END OCTOSPI2_Init 0 */
|
||||
|
||||
OSPIM_CfgTypeDef sOspiManagerCfg = {0};
|
||||
|
||||
/* USER CODE BEGIN OCTOSPI2_Init 1 */
|
||||
/*��ijЩ���ϣ��������������㷨ʱ����Ҫ�ֶ��������Ȳ���������Ṥ��������*/
|
||||
uint32_t i;
|
||||
char *p;
|
||||
|
||||
/* �˴��ο��˰������Ĵ��룬��ҿ���ȥѧϰ�������Ľ̳̣��dz�רҵ */
|
||||
p = (char *)&hospi2;
|
||||
for (i = 0; i < sizeof(hospi2); i++)
|
||||
{
|
||||
*p++ = 0;
|
||||
}
|
||||
hospi2.Instance = OCTOSPI1;
|
||||
HAL_OSPI_DeInit(&hospi2); // ��λOSPI
|
||||
/* USER CODE END OCTOSPI2_Init 1 */
|
||||
hospi2.Instance = OCTOSPI2;
|
||||
hospi2.Init.FifoThreshold = 8;
|
||||
hospi2.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE;
|
||||
hospi2.Init.MemoryType = HAL_OSPI_MEMTYPE_MICRON;
|
||||
hospi2.Init.DeviceSize = 23;
|
||||
hospi2.Init.ChipSelectHighTime = 1;
|
||||
hospi2.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE;
|
||||
hospi2.Init.ClockMode = HAL_OSPI_CLOCK_MODE_3;
|
||||
hospi2.Init.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED;
|
||||
hospi2.Init.ClockPrescaler = 3;
|
||||
hospi2.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE;
|
||||
hospi2.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_DISABLE;
|
||||
hospi2.Init.ChipSelectBoundary = 0;
|
||||
hospi2.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_BYPASSED;
|
||||
hospi2.Init.MaxTran = 0;
|
||||
hospi2.Init.Refresh = 0;
|
||||
if (HAL_OSPI_Init(&hospi2) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
sOspiManagerCfg.ClkPort = 1;
|
||||
sOspiManagerCfg.NCSPort = 1;
|
||||
sOspiManagerCfg.IOLowPort = HAL_OSPIM_IOPORT_1_LOW;
|
||||
if (HAL_OSPIM_Config(&hospi2, &sOspiManagerCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN OCTOSPI2_Init 2 */
|
||||
|
||||
/* USER CODE END OCTOSPI2_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
void HAL_OSPI_MspInit(OSPI_HandleTypeDef* ospiHandle)
|
||||
{
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
if(ospiHandle->Instance==OCTOSPI2)
|
||||
{
|
||||
/* USER CODE BEGIN OCTOSPI2_MspInit 0 */
|
||||
|
||||
/* USER CODE END OCTOSPI2_MspInit 0 */
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_OSPI;
|
||||
PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_D1HCLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* OCTOSPI2 clock enable */
|
||||
__HAL_RCC_OCTOSPIM_CLK_ENABLE();
|
||||
__HAL_RCC_OSPI2_CLK_ENABLE();
|
||||
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
/**OCTOSPI2 GPIO Configuration
|
||||
PA1 ------> OCTOSPIM_P1_IO3
|
||||
PA3 ------> OCTOSPIM_P1_IO2
|
||||
PB0 ------> OCTOSPIM_P1_IO1
|
||||
PB2 ------> OCTOSPIM_P1_CLK
|
||||
PE11 ------> OCTOSPIM_P1_NCS
|
||||
PD11 ------> OCTOSPIM_P1_IO0
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_1;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPIM_P1;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_3;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF6_OCTOSPIM_P1;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_0;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF4_OCTOSPIM_P1;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_2;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPIM_P1;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_11;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF11_OCTOSPIM_P1;
|
||||
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_11;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPIM_P1;
|
||||
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN OCTOSPI2_MspInit 1 */
|
||||
|
||||
/* USER CODE END OCTOSPI2_MspInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef* ospiHandle)
|
||||
{
|
||||
|
||||
if(ospiHandle->Instance==OCTOSPI2)
|
||||
{
|
||||
/* USER CODE BEGIN OCTOSPI2_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END OCTOSPI2_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_OCTOSPIM_CLK_DISABLE();
|
||||
__HAL_RCC_OSPI2_CLK_DISABLE();
|
||||
|
||||
/**OCTOSPI2 GPIO Configuration
|
||||
PA1 ------> OCTOSPIM_P1_IO3
|
||||
PA3 ------> OCTOSPIM_P1_IO2
|
||||
PB0 ------> OCTOSPIM_P1_IO1
|
||||
PB2 ------> OCTOSPIM_P1_CLK
|
||||
PE11 ------> OCTOSPIM_P1_NCS
|
||||
PD11 ------> OCTOSPIM_P1_IO0
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_3);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_2);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_11);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_11);
|
||||
|
||||
/* USER CODE BEGIN OCTOSPI2_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END OCTOSPI2_MspDeInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
+256
@@ -0,0 +1,256 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file spi.c
|
||||
* @brief This file provides code for the configuration
|
||||
* of the SPI instances.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2024 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "spi.h"
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
SPI_HandleTypeDef hspi1;
|
||||
SPI_HandleTypeDef hspi2;
|
||||
|
||||
/* SPI1 init function */
|
||||
void MX_SPI1_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN SPI1_Init 0 */
|
||||
|
||||
/* USER CODE END SPI1_Init 0 */
|
||||
|
||||
/* USER CODE BEGIN SPI1_Init 1 */
|
||||
|
||||
/* USER CODE END SPI1_Init 1 */
|
||||
hspi1.Instance = SPI1;
|
||||
hspi1.Init.Mode = SPI_MODE_MASTER;
|
||||
hspi1.Init.Direction = SPI_DIRECTION_2LINES_TXONLY;
|
||||
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
|
||||
hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
|
||||
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
|
||||
hspi1.Init.NSS = SPI_NSS_SOFT;
|
||||
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
|
||||
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
||||
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
|
||||
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
||||
hspi1.Init.CRCPolynomial = 0x0;
|
||||
hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
|
||||
hspi1.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
|
||||
hspi1.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
|
||||
hspi1.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
|
||||
hspi1.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
|
||||
hspi1.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
|
||||
hspi1.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
|
||||
hspi1.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
|
||||
hspi1.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE;
|
||||
hspi1.Init.IOSwap = SPI_IO_SWAP_DISABLE;
|
||||
if (HAL_SPI_Init(&hspi1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN SPI1_Init 2 */
|
||||
|
||||
/* USER CODE END SPI1_Init 2 */
|
||||
|
||||
}
|
||||
/* SPI2 init function */
|
||||
void MX_SPI2_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN SPI2_Init 0 */
|
||||
|
||||
/* USER CODE END SPI2_Init 0 */
|
||||
|
||||
/* USER CODE BEGIN SPI2_Init 1 */
|
||||
|
||||
/* USER CODE END SPI2_Init 1 */
|
||||
hspi2.Instance = SPI2;
|
||||
hspi2.Init.Mode = SPI_MODE_MASTER;
|
||||
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
|
||||
hspi2.Init.DataSize = SPI_DATASIZE_8BIT;
|
||||
hspi2.Init.CLKPolarity = SPI_POLARITY_HIGH;
|
||||
hspi2.Init.CLKPhase = SPI_PHASE_2EDGE;
|
||||
hspi2.Init.NSS = SPI_NSS_SOFT;
|
||||
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
|
||||
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
||||
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
|
||||
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
||||
hspi2.Init.CRCPolynomial = 0x0;
|
||||
hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
|
||||
hspi2.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
|
||||
hspi2.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
|
||||
hspi2.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
|
||||
hspi2.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
|
||||
hspi2.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
|
||||
hspi2.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
|
||||
hspi2.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
|
||||
hspi2.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE;
|
||||
hspi2.Init.IOSwap = SPI_IO_SWAP_DISABLE;
|
||||
if (HAL_SPI_Init(&hspi2) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN SPI2_Init 2 */
|
||||
|
||||
/* USER CODE END SPI2_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
|
||||
{
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
if(spiHandle->Instance==SPI1)
|
||||
{
|
||||
/* USER CODE BEGIN SPI1_MspInit 0 */
|
||||
|
||||
/* USER CODE END SPI1_MspInit 0 */
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI1;
|
||||
PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* SPI1 clock enable */
|
||||
__HAL_RCC_SPI1_CLK_ENABLE();
|
||||
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
/**SPI1 GPIO Configuration
|
||||
PD7 ------> SPI1_MOSI
|
||||
PB3(JTDO/TRACESWO) ------> SPI1_SCK
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_7;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
|
||||
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_3;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN SPI1_MspInit 1 */
|
||||
|
||||
/* USER CODE END SPI1_MspInit 1 */
|
||||
}
|
||||
else if(spiHandle->Instance==SPI2)
|
||||
{
|
||||
/* USER CODE BEGIN SPI2_MspInit 0 */
|
||||
|
||||
/* USER CODE END SPI2_MspInit 0 */
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI2;
|
||||
PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* SPI2 clock enable */
|
||||
__HAL_RCC_SPI2_CLK_ENABLE();
|
||||
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
/**SPI2 GPIO Configuration
|
||||
PC1 ------> SPI2_MOSI
|
||||
PC2_C ------> SPI2_MISO
|
||||
PB13 ------> SPI2_SCK
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
|
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_13;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN SPI2_MspInit 1 */
|
||||
|
||||
/* USER CODE END SPI2_MspInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
|
||||
{
|
||||
|
||||
if(spiHandle->Instance==SPI1)
|
||||
{
|
||||
/* USER CODE BEGIN SPI1_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END SPI1_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_SPI1_CLK_DISABLE();
|
||||
|
||||
/**SPI1 GPIO Configuration
|
||||
PD7 ------> SPI1_MOSI
|
||||
PB3(JTDO/TRACESWO) ------> SPI1_SCK
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_7);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3);
|
||||
|
||||
/* USER CODE BEGIN SPI1_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END SPI1_MspDeInit 1 */
|
||||
}
|
||||
else if(spiHandle->Instance==SPI2)
|
||||
{
|
||||
/* USER CODE BEGIN SPI2_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END SPI2_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_SPI2_CLK_DISABLE();
|
||||
|
||||
/**SPI2 GPIO Configuration
|
||||
PC1 ------> SPI2_MOSI
|
||||
PC2_C ------> SPI2_MISO
|
||||
PB13 ------> SPI2_SCK
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_2);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
|
||||
|
||||
/* USER CODE BEGIN SPI2_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END SPI2_MspDeInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
@@ -0,0 +1,82 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_msp.c
|
||||
* @brief This file provides code for the MSP Initialization
|
||||
* and de-Initialization codes.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2024 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "main.h"
|
||||
/* USER CODE BEGIN Includes */
|
||||
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN TD */
|
||||
|
||||
/* USER CODE END TD */
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Define */
|
||||
|
||||
/* USER CODE END Define */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Macro */
|
||||
|
||||
/* USER CODE END Macro */
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PV */
|
||||
|
||||
/* USER CODE END PV */
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* USER CODE BEGIN PFP */
|
||||
|
||||
/* USER CODE END PFP */
|
||||
|
||||
/* External functions --------------------------------------------------------*/
|
||||
/* USER CODE BEGIN ExternalFunctions */
|
||||
|
||||
/* USER CODE END ExternalFunctions */
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
/**
|
||||
* Initializes the Global MSP.
|
||||
*/
|
||||
void HAL_MspInit(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN MspInit 0 */
|
||||
|
||||
/* USER CODE END MspInit 0 */
|
||||
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* System interrupt init*/
|
||||
/* PendSV_IRQn interrupt configuration */
|
||||
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
|
||||
|
||||
/* USER CODE BEGIN MspInit 1 */
|
||||
|
||||
/* USER CODE END MspInit 1 */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
@@ -0,0 +1,122 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_timebase_tim.c
|
||||
* @brief HAL time base based on the hardware TIM.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2024 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
#include "stm32h7xx_hal_tim.h"
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
TIM_HandleTypeDef htim23;
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the TIM23 as a time base source.
|
||||
* The time source is configured to have 1ms time base with a dedicated
|
||||
* Tick interrupt priority.
|
||||
* @note This function is called automatically at the beginning of program after
|
||||
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
|
||||
* @param TickPriority: Tick interrupt priority.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||
{
|
||||
RCC_ClkInitTypeDef clkconfig;
|
||||
uint32_t uwTimclock;
|
||||
uint32_t uwPrescalerValue;
|
||||
uint32_t pFLatency;
|
||||
|
||||
/*Configure the TIM23 IRQ priority */
|
||||
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
||||
{
|
||||
HAL_NVIC_SetPriority(TIM23_IRQn, TickPriority ,0);
|
||||
|
||||
/* Enable the TIM23 global Interrupt */
|
||||
HAL_NVIC_EnableIRQ(TIM23_IRQn);
|
||||
uwTickPrio = TickPriority;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Enable TIM23 clock */
|
||||
__HAL_RCC_TIM23_CLK_ENABLE();
|
||||
|
||||
/* Get clock configuration */
|
||||
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
|
||||
|
||||
/* Compute TIM23 clock */
|
||||
uwTimclock = 2*HAL_RCC_GetPCLK2Freq();
|
||||
|
||||
/* Compute the prescaler value to have TIM23 counter clock equal to 1MHz */
|
||||
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
|
||||
|
||||
/* Initialize TIM23 */
|
||||
htim23.Instance = TIM23;
|
||||
|
||||
/* Initialize TIMx peripheral as follow:
|
||||
* Period = [(TIM23CLK/1000) - 1]. to have a (1/1000) s time base.
|
||||
* Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
|
||||
* ClockDivision = 0
|
||||
* Counter direction = Up
|
||||
*/
|
||||
htim23.Init.Period = (1000000U / 1000U) - 1U;
|
||||
htim23.Init.Prescaler = uwPrescalerValue;
|
||||
htim23.Init.ClockDivision = 0;
|
||||
htim23.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||
|
||||
if(HAL_TIM_Base_Init(&htim23) == HAL_OK)
|
||||
{
|
||||
|
||||
/* Start the TIM time Base generation in interrupt mode */
|
||||
return HAL_TIM_Base_Start_IT(&htim23);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment.
|
||||
* @note Disable the tick increment by disabling TIM23 update interrupt.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SuspendTick(void)
|
||||
{
|
||||
/* Disable TIM23 update Interrupt */
|
||||
__HAL_TIM_DISABLE_IT(&htim23, TIM_IT_UPDATE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Tick increment.
|
||||
* @note Enable the tick increment by Enabling TIM23 update interrupt.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Enable TIM23 Update interrupt */
|
||||
__HAL_TIM_ENABLE_IT(&htim23, TIM_IT_UPDATE);
|
||||
}
|
||||
|
||||
@@ -0,0 +1,607 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_it.c
|
||||
* @brief Interrupt Service Routines.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2024 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "main.h"
|
||||
#include "stm32h7xx_it.h"
|
||||
/* Private includes ----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Includes */
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN TD */
|
||||
|
||||
/* USER CODE END TD */
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PD */
|
||||
|
||||
/* USER CODE END PD */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PM */
|
||||
|
||||
/* USER CODE END PM */
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PV */
|
||||
|
||||
/* USER CODE END PV */
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* USER CODE BEGIN PFP */
|
||||
|
||||
/* USER CODE END PFP */
|
||||
|
||||
/* Private user code ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
/* External variables --------------------------------------------------------*/
|
||||
extern PCD_HandleTypeDef hpcd_USB_OTG_HS;
|
||||
extern DMA_HandleTypeDef hdma_adc1;
|
||||
extern FDCAN_HandleTypeDef hfdcan1;
|
||||
extern FDCAN_HandleTypeDef hfdcan2;
|
||||
extern FDCAN_HandleTypeDef hfdcan3;
|
||||
extern DMA_HandleTypeDef hdma_i2c2_rx;
|
||||
extern DMA_HandleTypeDef hdma_i2c2_tx;
|
||||
extern I2C_HandleTypeDef hi2c2;
|
||||
extern DMA_HandleTypeDef hdma_uart5_rx;
|
||||
extern DMA_HandleTypeDef hdma_uart8_tx;
|
||||
extern DMA_HandleTypeDef hdma_uart8_rx;
|
||||
extern DMA_HandleTypeDef hdma_uart9_rx;
|
||||
extern DMA_HandleTypeDef hdma_uart9_tx;
|
||||
extern DMA_HandleTypeDef hdma_usart1_tx;
|
||||
extern DMA_HandleTypeDef hdma_usart1_rx;
|
||||
extern DMA_HandleTypeDef hdma_usart2_rx;
|
||||
extern DMA_HandleTypeDef hdma_usart2_tx;
|
||||
extern DMA_HandleTypeDef hdma_usart3_rx;
|
||||
extern DMA_HandleTypeDef hdma_usart3_tx;
|
||||
extern DMA_HandleTypeDef hdma_usart10_rx;
|
||||
extern DMA_HandleTypeDef hdma_usart10_tx;
|
||||
extern UART_HandleTypeDef huart5;
|
||||
extern UART_HandleTypeDef huart7;
|
||||
extern UART_HandleTypeDef huart1;
|
||||
extern UART_HandleTypeDef huart2;
|
||||
extern UART_HandleTypeDef huart3;
|
||||
extern UART_HandleTypeDef huart10;
|
||||
extern TIM_HandleTypeDef htim23;
|
||||
|
||||
/* USER CODE BEGIN EV */
|
||||
|
||||
/* USER CODE END EV */
|
||||
|
||||
/******************************************************************************/
|
||||
/* Cortex Processor Interruption and Exception Handlers */
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* @brief This function handles Non maskable interrupt.
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
||||
|
||||
/* USER CODE END NonMaskableInt_IRQn 0 */
|
||||
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
/* USER CODE END NonMaskableInt_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Hard fault interrupt.
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN HardFault_IRQn 0 */
|
||||
|
||||
/* USER CODE END HardFault_IRQn 0 */
|
||||
while (1)
|
||||
{
|
||||
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
|
||||
/* USER CODE END W1_HardFault_IRQn 0 */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Memory management fault.
|
||||
*/
|
||||
void MemManage_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
||||
|
||||
/* USER CODE END MemoryManagement_IRQn 0 */
|
||||
while (1)
|
||||
{
|
||||
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
|
||||
/* USER CODE END W1_MemoryManagement_IRQn 0 */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Pre-fetch fault, memory access fault.
|
||||
*/
|
||||
void BusFault_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN BusFault_IRQn 0 */
|
||||
|
||||
/* USER CODE END BusFault_IRQn 0 */
|
||||
while (1)
|
||||
{
|
||||
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
|
||||
/* USER CODE END W1_BusFault_IRQn 0 */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Undefined instruction or illegal state.
|
||||
*/
|
||||
void UsageFault_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
||||
|
||||
/* USER CODE END UsageFault_IRQn 0 */
|
||||
while (1)
|
||||
{
|
||||
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
|
||||
/* USER CODE END W1_UsageFault_IRQn 0 */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Debug monitor.
|
||||
*/
|
||||
void DebugMon_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
|
||||
|
||||
/* USER CODE END DebugMonitor_IRQn 0 */
|
||||
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
||||
|
||||
/* USER CODE END DebugMonitor_IRQn 1 */
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/* STM32H7xx Peripheral Interrupt Handlers */
|
||||
/* Add here the Interrupt Handlers for the used peripherals. */
|
||||
/* For the available peripheral interrupt handler names, */
|
||||
/* please refer to the startup file (startup_stm32h7xx.s). */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA1 stream0 global interrupt.
|
||||
*/
|
||||
void DMA1_Stream0_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA1_Stream0_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA1_Stream0_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA1 stream1 global interrupt.
|
||||
*/
|
||||
void DMA1_Stream1_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA1_Stream1_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA1_Stream1_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA1_Stream1_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA1_Stream1_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA1 stream2 global interrupt.
|
||||
*/
|
||||
void DMA1_Stream2_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA1_Stream2_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA1_Stream2_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA1_Stream2_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA1_Stream2_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA1 stream3 global interrupt.
|
||||
*/
|
||||
void DMA1_Stream3_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA1_Stream3_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA1_Stream3_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA1_Stream3_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA1_Stream3_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA1 stream4 global interrupt.
|
||||
*/
|
||||
void DMA1_Stream4_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA1_Stream4_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA1_Stream4_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA1_Stream4_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA1_Stream4_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA1 stream5 global interrupt.
|
||||
*/
|
||||
void DMA1_Stream5_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA1_Stream5_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA1_Stream5_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA1_Stream5_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA1_Stream5_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA1 stream6 global interrupt.
|
||||
*/
|
||||
void DMA1_Stream6_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA1_Stream6_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA1_Stream6_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA1_Stream6_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA1_Stream6_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FDCAN1 interrupt 0.
|
||||
*/
|
||||
void FDCAN1_IT0_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */
|
||||
|
||||
/* USER CODE END FDCAN1_IT0_IRQn 0 */
|
||||
HAL_FDCAN_IRQHandler(&hfdcan1);
|
||||
/* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */
|
||||
|
||||
/* USER CODE END FDCAN1_IT0_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FDCAN2 interrupt 0.
|
||||
*/
|
||||
void FDCAN2_IT0_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */
|
||||
|
||||
/* USER CODE END FDCAN2_IT0_IRQn 0 */
|
||||
HAL_FDCAN_IRQHandler(&hfdcan2);
|
||||
/* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */
|
||||
|
||||
/* USER CODE END FDCAN2_IT0_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FDCAN1 interrupt 1.
|
||||
*/
|
||||
void FDCAN1_IT1_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN FDCAN1_IT1_IRQn 0 */
|
||||
|
||||
/* USER CODE END FDCAN1_IT1_IRQn 0 */
|
||||
HAL_FDCAN_IRQHandler(&hfdcan1);
|
||||
/* USER CODE BEGIN FDCAN1_IT1_IRQn 1 */
|
||||
|
||||
/* USER CODE END FDCAN1_IT1_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FDCAN2 interrupt 1.
|
||||
*/
|
||||
void FDCAN2_IT1_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN FDCAN2_IT1_IRQn 0 */
|
||||
|
||||
/* USER CODE END FDCAN2_IT1_IRQn 0 */
|
||||
HAL_FDCAN_IRQHandler(&hfdcan2);
|
||||
/* USER CODE BEGIN FDCAN2_IT1_IRQn 1 */
|
||||
|
||||
/* USER CODE END FDCAN2_IT1_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles I2C2 event interrupt.
|
||||
*/
|
||||
void I2C2_EV_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN I2C2_EV_IRQn 0 */
|
||||
|
||||
/* USER CODE END I2C2_EV_IRQn 0 */
|
||||
HAL_I2C_EV_IRQHandler(&hi2c2);
|
||||
/* USER CODE BEGIN I2C2_EV_IRQn 1 */
|
||||
|
||||
/* USER CODE END I2C2_EV_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles USART1 global interrupt.
|
||||
*/
|
||||
void USART1_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN USART1_IRQn 0 */
|
||||
|
||||
/* USER CODE END USART1_IRQn 0 */
|
||||
HAL_UART_IRQHandler(&huart1);
|
||||
/* USER CODE BEGIN USART1_IRQn 1 */
|
||||
|
||||
/* USER CODE END USART1_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles USART2 global interrupt.
|
||||
*/
|
||||
void USART2_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN USART2_IRQn 0 */
|
||||
|
||||
/* USER CODE END USART2_IRQn 0 */
|
||||
HAL_UART_IRQHandler(&huart2);
|
||||
/* USER CODE BEGIN USART2_IRQn 1 */
|
||||
|
||||
/* USER CODE END USART2_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles USART3 global interrupt.
|
||||
*/
|
||||
void USART3_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN USART3_IRQn 0 */
|
||||
|
||||
/* USER CODE END USART3_IRQn 0 */
|
||||
HAL_UART_IRQHandler(&huart3);
|
||||
/* USER CODE BEGIN USART3_IRQn 1 */
|
||||
|
||||
/* USER CODE END USART3_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA1 stream7 global interrupt.
|
||||
*/
|
||||
void DMA1_Stream7_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA1_Stream7_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA1_Stream7_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA1_Stream7_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA1_Stream7_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles UART5 global interrupt.
|
||||
*/
|
||||
void UART5_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN UART5_IRQn 0 */
|
||||
|
||||
/* USER CODE END UART5_IRQn 0 */
|
||||
HAL_UART_IRQHandler(&huart5);
|
||||
/* USER CODE BEGIN UART5_IRQn 1 */
|
||||
|
||||
/* USER CODE END UART5_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA2 stream0 global interrupt.
|
||||
*/
|
||||
void DMA2_Stream0_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA2_Stream0_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA2_Stream0_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA2_Stream0_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA2_Stream0_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA2 stream1 global interrupt.
|
||||
*/
|
||||
void DMA2_Stream1_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA2_Stream1_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA2_Stream1_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA2_Stream1_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA2_Stream1_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA2 stream2 global interrupt.
|
||||
*/
|
||||
void DMA2_Stream2_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA2_Stream2_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA2_Stream2_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA2_Stream2_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA2_Stream2_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA2 stream3 global interrupt.
|
||||
*/
|
||||
void DMA2_Stream3_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA2_Stream3_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA2_Stream3_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA2_Stream3_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA2_Stream3_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA2 stream4 global interrupt.
|
||||
*/
|
||||
void DMA2_Stream4_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA2_Stream4_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA2_Stream4_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA2_Stream4_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA2_Stream4_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA2 stream5 global interrupt.
|
||||
*/
|
||||
void DMA2_Stream5_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA2_Stream5_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA2_Stream5_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA2_Stream5_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA2_Stream5_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA2 stream6 global interrupt.
|
||||
*/
|
||||
void DMA2_Stream6_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA2_Stream6_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA2_Stream6_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA2_Stream6_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA2_Stream6_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA2 stream7 global interrupt.
|
||||
*/
|
||||
void DMA2_Stream7_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA2_Stream7_IRQn 0 */
|
||||
|
||||
/* USER CODE END DMA2_Stream7_IRQn 0 */
|
||||
/* USER CODE BEGIN DMA2_Stream7_IRQn 1 */
|
||||
|
||||
/* USER CODE END DMA2_Stream7_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles USB OTG HS global interrupt.
|
||||
*/
|
||||
void OTG_HS_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN OTG_HS_IRQn 0 */
|
||||
|
||||
/* USER CODE END OTG_HS_IRQn 0 */
|
||||
/* USER CODE BEGIN OTG_HS_IRQn 1 */
|
||||
|
||||
/* USER CODE END OTG_HS_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles UART7 global interrupt.
|
||||
*/
|
||||
void UART7_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN UART7_IRQn 0 */
|
||||
|
||||
/* USER CODE END UART7_IRQn 0 */
|
||||
HAL_UART_IRQHandler(&huart7);
|
||||
/* USER CODE BEGIN UART7_IRQn 1 */
|
||||
|
||||
/* USER CODE END UART7_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles USART10 global interrupt.
|
||||
*/
|
||||
void USART10_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN USART10_IRQn 0 */
|
||||
|
||||
/* USER CODE END USART10_IRQn 0 */
|
||||
HAL_UART_IRQHandler(&huart10);
|
||||
/* USER CODE BEGIN USART10_IRQn 1 */
|
||||
|
||||
/* USER CODE END USART10_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FDCAN3 interrupt 0.
|
||||
*/
|
||||
void FDCAN3_IT0_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN FDCAN3_IT0_IRQn 0 */
|
||||
|
||||
/* USER CODE END FDCAN3_IT0_IRQn 0 */
|
||||
HAL_FDCAN_IRQHandler(&hfdcan3);
|
||||
/* USER CODE BEGIN FDCAN3_IT0_IRQn 1 */
|
||||
|
||||
/* USER CODE END FDCAN3_IT0_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FDCAN3 interrupt 1.
|
||||
*/
|
||||
void FDCAN3_IT1_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN FDCAN3_IT1_IRQn 0 */
|
||||
|
||||
/* USER CODE END FDCAN3_IT1_IRQn 0 */
|
||||
HAL_FDCAN_IRQHandler(&hfdcan3);
|
||||
/* USER CODE BEGIN FDCAN3_IT1_IRQn 1 */
|
||||
|
||||
/* USER CODE END FDCAN3_IT1_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles TIM23 global interrupt.
|
||||
*/
|
||||
void TIM23_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN TIM23_IRQn 0 */
|
||||
|
||||
/* USER CODE END TIM23_IRQn 0 */
|
||||
/* USER CODE BEGIN TIM23_IRQn 1 */
|
||||
|
||||
/* USER CODE END TIM23_IRQn 1 */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
@@ -0,0 +1,176 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file syscalls.c
|
||||
* @author Auto-generated by STM32CubeMX
|
||||
* @brief Minimal System calls file
|
||||
*
|
||||
* For more information about which c-functions
|
||||
* need which of these lowlevel functions
|
||||
* please consult the Newlib libc-manual
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2020-2024 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes */
|
||||
#include <sys/stat.h>
|
||||
#include <stdlib.h>
|
||||
#include <errno.h>
|
||||
#include <stdio.h>
|
||||
#include <signal.h>
|
||||
#include <time.h>
|
||||
#include <sys/time.h>
|
||||
#include <sys/times.h>
|
||||
|
||||
|
||||
/* Variables */
|
||||
extern int __io_putchar(int ch) __attribute__((weak));
|
||||
extern int __io_getchar(void) __attribute__((weak));
|
||||
|
||||
|
||||
char *__env[1] = { 0 };
|
||||
char **environ = __env;
|
||||
|
||||
|
||||
/* Functions */
|
||||
void initialise_monitor_handles()
|
||||
{
|
||||
}
|
||||
|
||||
int _getpid(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _kill(int pid, int sig)
|
||||
{
|
||||
(void)pid;
|
||||
(void)sig;
|
||||
errno = EINVAL;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _exit (int status)
|
||||
{
|
||||
_kill(status, -1);
|
||||
while (1) {} /* Make sure we hang here */
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _read(int file, char *ptr, int len)
|
||||
{
|
||||
(void)file;
|
||||
int DataIdx;
|
||||
|
||||
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
||||
{
|
||||
*ptr++ = __io_getchar();
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _write(int file, char *ptr, int len)
|
||||
{
|
||||
(void)file;
|
||||
int DataIdx;
|
||||
|
||||
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
||||
{
|
||||
__io_putchar(*ptr++);
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
int _close(int file)
|
||||
{
|
||||
(void)file;
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
int _fstat(int file, struct stat *st)
|
||||
{
|
||||
(void)file;
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _isatty(int file)
|
||||
{
|
||||
(void)file;
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _lseek(int file, int ptr, int dir)
|
||||
{
|
||||
(void)file;
|
||||
(void)ptr;
|
||||
(void)dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _open(char *path, int flags, ...)
|
||||
{
|
||||
(void)path;
|
||||
(void)flags;
|
||||
/* Pretend like we always fail */
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _wait(int *status)
|
||||
{
|
||||
(void)status;
|
||||
errno = ECHILD;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _unlink(char *name)
|
||||
{
|
||||
(void)name;
|
||||
errno = ENOENT;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _times(struct tms *buf)
|
||||
{
|
||||
(void)buf;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _stat(char *file, struct stat *st)
|
||||
{
|
||||
(void)file;
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _link(char *old, char *new)
|
||||
{
|
||||
(void)old;
|
||||
(void)new;
|
||||
errno = EMLINK;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _fork(void)
|
||||
{
|
||||
errno = EAGAIN;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _execve(char *name, char **argv, char **env)
|
||||
{
|
||||
(void)name;
|
||||
(void)argv;
|
||||
(void)env;
|
||||
errno = ENOMEM;
|
||||
return -1;
|
||||
}
|
||||
@@ -0,0 +1,79 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file sysmem.c
|
||||
* @author Generated by STM32CubeMX
|
||||
* @brief System Memory calls file
|
||||
*
|
||||
* For more information about which C functions
|
||||
* need which of these lowlevel functions
|
||||
* please consult the newlib libc manual
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2024 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes */
|
||||
#include <errno.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
* Pointer to the current high watermark of the heap usage
|
||||
*/
|
||||
static uint8_t *__sbrk_heap_end = NULL;
|
||||
|
||||
/**
|
||||
* @brief _sbrk() allocates memory to the newlib heap and is used by malloc
|
||||
* and others from the C library
|
||||
*
|
||||
* @verbatim
|
||||
* ############################################################################
|
||||
* # .data # .bss # newlib heap # MSP stack #
|
||||
* # # # # Reserved by _Min_Stack_Size #
|
||||
* ############################################################################
|
||||
* ^-- RAM start ^-- _end _estack, RAM end --^
|
||||
* @endverbatim
|
||||
*
|
||||
* This implementation starts allocating at the '_end' linker symbol
|
||||
* The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
|
||||
* The implementation considers '_estack' linker symbol to be RAM end
|
||||
* NOTE: If the MSP stack, at any point during execution, grows larger than the
|
||||
* reserved size, please increase the '_Min_Stack_Size'.
|
||||
*
|
||||
* @param incr Memory size
|
||||
* @return Pointer to allocated memory
|
||||
*/
|
||||
void *_sbrk(ptrdiff_t incr)
|
||||
{
|
||||
extern uint8_t _end; /* Symbol defined in the linker script */
|
||||
extern uint8_t _estack; /* Symbol defined in the linker script */
|
||||
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
||||
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
||||
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
||||
uint8_t *prev_heap_end;
|
||||
|
||||
/* Initialize heap end at first call */
|
||||
if (NULL == __sbrk_heap_end)
|
||||
{
|
||||
__sbrk_heap_end = &_end;
|
||||
}
|
||||
|
||||
/* Protect heap from growing into the reserved MSP stack */
|
||||
if (__sbrk_heap_end + incr > max_heap)
|
||||
{
|
||||
errno = ENOMEM;
|
||||
return (void *)-1;
|
||||
}
|
||||
|
||||
prev_heap_end = __sbrk_heap_end;
|
||||
__sbrk_heap_end += incr;
|
||||
|
||||
return (void *)prev_heap_end;
|
||||
}
|
||||
@@ -0,0 +1,469 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32h7xx.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32h7xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock, it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32h7xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32h7xx.h"
|
||||
#include <math.h>
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (CSI_VALUE)
|
||||
#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* CSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
|
||||
/* #define DATA_IN_D2_SRAM */
|
||||
|
||||
/* Note: Following vector table addresses must be defined in line with linker
|
||||
configuration. */
|
||||
/*!< Uncomment the following line if you need to relocate the vector table
|
||||
anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
|
||||
remap of boot address selected */
|
||||
/* #define USER_VECT_TAB_ADDRESS */
|
||||
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
#if defined(DUAL_CORE) && defined(CORE_CM4)
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table
|
||||
in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#else
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table
|
||||
in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x400. */
|
||||
#endif /* VECT_TAB_SRAM */
|
||||
#endif /* DUAL_CORE && CORE_CM4 */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 64000000;
|
||||
uint32_t SystemD2Clock = 64000000;
|
||||
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32H7xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Exit Run* mode by configuring the power supply (LDO).
|
||||
* Called from startup before SystemInit.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void ExitRun0Mode(void)
|
||||
{
|
||||
#if defined(USE_PWR_LDO_SUPPLY)
|
||||
/* Enable LDO and wait for voltage regulator ready */
|
||||
MODIFY_REG(PWR->CR3, PWR_CR3_LDOEN, PWR_CR3_LDOEN);
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) {}
|
||||
#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY)
|
||||
/* Enable SMPS and wait for voltage regulator ready */
|
||||
MODIFY_REG(PWR->CR3, PWR_CR3_SMPSEN, PWR_CR3_SMPSEN);
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) {}
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the FPU setting and vector table location
|
||||
* configuration.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if defined (DATA_IN_D2_SRAM)
|
||||
__IO uint32_t tmpreg;
|
||||
#endif /* DATA_IN_D2_SRAM */
|
||||
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
|
||||
/* Increasing the CPU frequency */
|
||||
if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
|
||||
{
|
||||
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
||||
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
|
||||
}
|
||||
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= RCC_CR_HSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
|
||||
RCC->CR &= 0xEAF6ED7FU;
|
||||
|
||||
/* Decreasing the number of wait states because of lower CPU frequency */
|
||||
if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
|
||||
{
|
||||
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
||||
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
|
||||
}
|
||||
|
||||
#if defined(D3_SRAM_BASE)
|
||||
/* Reset D1CFGR register */
|
||||
RCC->D1CFGR = 0x00000000;
|
||||
|
||||
/* Reset D2CFGR register */
|
||||
RCC->D2CFGR = 0x00000000;
|
||||
|
||||
/* Reset D3CFGR register */
|
||||
RCC->D3CFGR = 0x00000000;
|
||||
#else
|
||||
/* Reset CDCFGR1 register */
|
||||
RCC->CDCFGR1 = 0x00000000;
|
||||
|
||||
/* Reset CDCFGR2 register */
|
||||
RCC->CDCFGR2 = 0x00000000;
|
||||
|
||||
/* Reset SRDCFGR register */
|
||||
RCC->SRDCFGR = 0x00000000;
|
||||
#endif
|
||||
/* Reset PLLCKSELR register */
|
||||
RCC->PLLCKSELR = 0x02020200;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x01FF0000;
|
||||
/* Reset PLL1DIVR register */
|
||||
RCC->PLL1DIVR = 0x01010280;
|
||||
/* Reset PLL1FRACR register */
|
||||
RCC->PLL1FRACR = 0x00000000;
|
||||
|
||||
/* Reset PLL2DIVR register */
|
||||
RCC->PLL2DIVR = 0x01010280;
|
||||
|
||||
/* Reset PLL2FRACR register */
|
||||
|
||||
RCC->PLL2FRACR = 0x00000000;
|
||||
/* Reset PLL3DIVR register */
|
||||
RCC->PLL3DIVR = 0x01010280;
|
||||
|
||||
/* Reset PLL3FRACR register */
|
||||
RCC->PLL3FRACR = 0x00000000;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= 0xFFFBFFFFU;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0x00000000;
|
||||
|
||||
#if (STM32H7_DEV_ID == 0x450UL)
|
||||
/* dual core CM7 or single core line */
|
||||
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
|
||||
{
|
||||
/* if stm32h7 revY*/
|
||||
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
|
||||
*((__IO uint32_t*)0x51008108) = 0x000000001U;
|
||||
}
|
||||
#endif /* STM32H7_DEV_ID */
|
||||
|
||||
#if defined(DATA_IN_D2_SRAM)
|
||||
/* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
|
||||
#if defined(RCC_AHB2ENR_D2SRAM3EN)
|
||||
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
|
||||
#elif defined(RCC_AHB2ENR_D2SRAM2EN)
|
||||
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
|
||||
#else
|
||||
RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
|
||||
#endif /* RCC_AHB2ENR_D2SRAM3EN */
|
||||
|
||||
tmpreg = RCC->AHB2ENR;
|
||||
(void) tmpreg;
|
||||
#endif /* DATA_IN_D2_SRAM */
|
||||
|
||||
#if defined(DUAL_CORE) && defined(CORE_CM4)
|
||||
/* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
|
||||
#else
|
||||
/*
|
||||
* Disable the FMC bank1 (enabled after reset).
|
||||
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
|
||||
* 24us. During this time the others FMC master (such as LTDC) cannot use it!
|
||||
*/
|
||||
FMC_Bank1_R->BTCR[0] = 0x000030D2;
|
||||
|
||||
/* Configure the Vector Table location -------------------------------------*/
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
|
||||
#endif /* USER_VECT_TAB_ADDRESS */
|
||||
|
||||
#endif /*DUAL_CORE && CORE_CM4*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock , it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
|
||||
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
* (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
|
||||
* 64 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
|
||||
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
|
||||
uint32_t common_system_clock;
|
||||
float_t fracn1, pllvco;
|
||||
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
|
||||
switch (RCC->CFGR & RCC_CFGR_SWS)
|
||||
{
|
||||
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
||||
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
|
||||
break;
|
||||
|
||||
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
|
||||
common_system_clock = CSI_VALUE;
|
||||
break;
|
||||
|
||||
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
||||
common_system_clock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
|
||||
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
|
||||
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
|
||||
pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
|
||||
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
|
||||
|
||||
if (pllm != 0U)
|
||||
{
|
||||
switch (pllsource)
|
||||
{
|
||||
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
|
||||
|
||||
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
|
||||
pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
|
||||
break;
|
||||
|
||||
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
|
||||
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
|
||||
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
|
||||
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
|
||||
default:
|
||||
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
|
||||
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
}
|
||||
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
|
||||
common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
|
||||
}
|
||||
else
|
||||
{
|
||||
common_system_clock = 0U;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
|
||||
break;
|
||||
}
|
||||
|
||||
/* Compute SystemClock frequency --------------------------------------------------*/
|
||||
#if defined (RCC_D1CFGR_D1CPRE)
|
||||
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
|
||||
|
||||
/* common_system_clock frequency : CM7 CPU frequency */
|
||||
common_system_clock >>= tmp;
|
||||
|
||||
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
|
||||
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
|
||||
|
||||
#else
|
||||
tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
|
||||
|
||||
/* common_system_clock frequency : CM7 CPU frequency */
|
||||
common_system_clock >>= tmp;
|
||||
|
||||
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */
|
||||
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(DUAL_CORE) && defined(CORE_CM4)
|
||||
SystemCoreClock = SystemD2Clock;
|
||||
#else
|
||||
SystemCoreClock = common_system_clock;
|
||||
#endif /* DUAL_CORE && CORE_CM4 */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
+430
@@ -0,0 +1,430 @@
|
||||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file tim.c
|
||||
* @brief This file provides code for the configuration
|
||||
* of the TIM instances.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2024 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tim.h"
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
TIM_HandleTypeDef htim1;
|
||||
TIM_HandleTypeDef htim2;
|
||||
TIM_HandleTypeDef htim3;
|
||||
TIM_HandleTypeDef htim12;
|
||||
|
||||
/* TIM1 init function */
|
||||
void MX_TIM1_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN TIM1_Init 0 */
|
||||
|
||||
/* USER CODE END TIM1_Init 0 */
|
||||
|
||||
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
||||
TIM_OC_InitTypeDef sConfigOC = {0};
|
||||
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
|
||||
|
||||
/* USER CODE BEGIN TIM1_Init 1 */
|
||||
|
||||
/* USER CODE END TIM1_Init 1 */
|
||||
htim1.Instance = TIM1;
|
||||
htim1.Init.Prescaler = 24;
|
||||
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||
htim1.Init.Period = 10000;
|
||||
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
||||
htim1.Init.RepetitionCounter = 0;
|
||||
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
||||
if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
||||
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
|
||||
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
||||
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
||||
sConfigOC.Pulse = 5000;
|
||||
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
||||
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
|
||||
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
||||
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
|
||||
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
|
||||
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
|
||||
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
|
||||
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
|
||||
sBreakDeadTimeConfig.DeadTime = 0;
|
||||
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
|
||||
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
|
||||
sBreakDeadTimeConfig.BreakFilter = 0;
|
||||
sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
|
||||
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
|
||||
sBreakDeadTimeConfig.Break2Filter = 0;
|
||||
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
|
||||
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN TIM1_Init 2 */
|
||||
|
||||
/* USER CODE END TIM1_Init 2 */
|
||||
HAL_TIM_MspPostInit(&htim1);
|
||||
|
||||
}
|
||||
/* TIM2 init function */
|
||||
void MX_TIM2_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN TIM2_Init 0 */
|
||||
|
||||
/* USER CODE END TIM2_Init 0 */
|
||||
|
||||
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
||||
TIM_OC_InitTypeDef sConfigOC = {0};
|
||||
|
||||
/* USER CODE BEGIN TIM2_Init 1 */
|
||||
|
||||
/* USER CODE END TIM2_Init 1 */
|
||||
htim2.Instance = TIM2;
|
||||
htim2.Init.Prescaler = 24;
|
||||
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||
htim2.Init.Period = 10000;
|
||||
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
||||
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
||||
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
||||
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
||||
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
||||
sConfigOC.Pulse = 5000;
|
||||
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
||||
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
||||
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN TIM2_Init 2 */
|
||||
|
||||
/* USER CODE END TIM2_Init 2 */
|
||||
HAL_TIM_MspPostInit(&htim2);
|
||||
|
||||
}
|
||||
/* TIM3 init function */
|
||||
void MX_TIM3_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN TIM3_Init 0 */
|
||||
|
||||
/* USER CODE END TIM3_Init 0 */
|
||||
|
||||
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
||||
TIM_OC_InitTypeDef sConfigOC = {0};
|
||||
|
||||
/* USER CODE BEGIN TIM3_Init 1 */
|
||||
|
||||
/* USER CODE END TIM3_Init 1 */
|
||||
htim3.Instance = TIM3;
|
||||
htim3.Init.Prescaler = 24-1;
|
||||
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||
htim3.Init.Period = 10000-1;
|
||||
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
||||
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
|
||||
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
||||
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
||||
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
||||
sConfigOC.Pulse = 0;
|
||||
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
||||
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
||||
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN TIM3_Init 2 */
|
||||
|
||||
/* USER CODE END TIM3_Init 2 */
|
||||
HAL_TIM_MspPostInit(&htim3);
|
||||
|
||||
}
|
||||
/* TIM12 init function */
|
||||
void MX_TIM12_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN TIM12_Init 0 */
|
||||
|
||||
/* USER CODE END TIM12_Init 0 */
|
||||
|
||||
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
||||
TIM_OC_InitTypeDef sConfigOC = {0};
|
||||
|
||||
/* USER CODE BEGIN TIM12_Init 1 */
|
||||
|
||||
/* USER CODE END TIM12_Init 1 */
|
||||
htim12.Instance = TIM12;
|
||||
htim12.Init.Prescaler = 24-1;
|
||||
htim12.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||
htim12.Init.Period = 2000-1;
|
||||
htim12.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
||||
htim12.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
||||
if (HAL_TIM_PWM_Init(&htim12) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
||||
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
||||
if (HAL_TIMEx_MasterConfigSynchronization(&htim12, &sMasterConfig) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
||||
sConfigOC.Pulse = 0;
|
||||
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
||||
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
||||
if (HAL_TIM_PWM_ConfigChannel(&htim12, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN TIM12_Init 2 */
|
||||
|
||||
/* USER CODE END TIM12_Init 2 */
|
||||
HAL_TIM_MspPostInit(&htim12);
|
||||
|
||||
}
|
||||
|
||||
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle)
|
||||
{
|
||||
|
||||
if(tim_pwmHandle->Instance==TIM1)
|
||||
{
|
||||
/* USER CODE BEGIN TIM1_MspInit 0 */
|
||||
|
||||
/* USER CODE END TIM1_MspInit 0 */
|
||||
/* TIM1 clock enable */
|
||||
__HAL_RCC_TIM1_CLK_ENABLE();
|
||||
/* USER CODE BEGIN TIM1_MspInit 1 */
|
||||
|
||||
/* USER CODE END TIM1_MspInit 1 */
|
||||
}
|
||||
else if(tim_pwmHandle->Instance==TIM2)
|
||||
{
|
||||
/* USER CODE BEGIN TIM2_MspInit 0 */
|
||||
|
||||
/* USER CODE END TIM2_MspInit 0 */
|
||||
/* TIM2 clock enable */
|
||||
__HAL_RCC_TIM2_CLK_ENABLE();
|
||||
/* USER CODE BEGIN TIM2_MspInit 1 */
|
||||
|
||||
/* USER CODE END TIM2_MspInit 1 */
|
||||
}
|
||||
else if(tim_pwmHandle->Instance==TIM3)
|
||||
{
|
||||
/* USER CODE BEGIN TIM3_MspInit 0 */
|
||||
|
||||
/* USER CODE END TIM3_MspInit 0 */
|
||||
/* TIM3 clock enable */
|
||||
__HAL_RCC_TIM3_CLK_ENABLE();
|
||||
/* USER CODE BEGIN TIM3_MspInit 1 */
|
||||
|
||||
/* USER CODE END TIM3_MspInit 1 */
|
||||
}
|
||||
else if(tim_pwmHandle->Instance==TIM12)
|
||||
{
|
||||
/* USER CODE BEGIN TIM12_MspInit 0 */
|
||||
|
||||
/* USER CODE END TIM12_MspInit 0 */
|
||||
/* TIM12 clock enable */
|
||||
__HAL_RCC_TIM12_CLK_ENABLE();
|
||||
/* USER CODE BEGIN TIM12_MspInit 1 */
|
||||
|
||||
/* USER CODE END TIM12_MspInit 1 */
|
||||
}
|
||||
}
|
||||
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
|
||||
{
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
if(timHandle->Instance==TIM1)
|
||||
{
|
||||
/* USER CODE BEGIN TIM1_MspPostInit 0 */
|
||||
|
||||
/* USER CODE END TIM1_MspPostInit 0 */
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
/**TIM1 GPIO Configuration
|
||||
PE9 ------> TIM1_CH1
|
||||
PE13 ------> TIM1_CH3
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_13;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
|
||||
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN TIM1_MspPostInit 1 */
|
||||
|
||||
/* USER CODE END TIM1_MspPostInit 1 */
|
||||
}
|
||||
else if(timHandle->Instance==TIM2)
|
||||
{
|
||||
/* USER CODE BEGIN TIM2_MspPostInit 0 */
|
||||
|
||||
/* USER CODE END TIM2_MspPostInit 0 */
|
||||
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
/**TIM2 GPIO Configuration
|
||||
PA0 ------> TIM2_CH1
|
||||
PA2 ------> TIM2_CH3
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_2;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN TIM2_MspPostInit 1 */
|
||||
|
||||
/* USER CODE END TIM2_MspPostInit 1 */
|
||||
}
|
||||
else if(timHandle->Instance==TIM3)
|
||||
{
|
||||
/* USER CODE BEGIN TIM3_MspPostInit 0 */
|
||||
|
||||
/* USER CODE END TIM3_MspPostInit 0 */
|
||||
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
/**TIM3 GPIO Configuration
|
||||
PB1 ------> TIM3_CH4
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_1;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN TIM3_MspPostInit 1 */
|
||||
|
||||
/* USER CODE END TIM3_MspPostInit 1 */
|
||||
}
|
||||
else if(timHandle->Instance==TIM12)
|
||||
{
|
||||
/* USER CODE BEGIN TIM12_MspPostInit 0 */
|
||||
|
||||
/* USER CODE END TIM12_MspPostInit 0 */
|
||||
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
/**TIM12 GPIO Configuration
|
||||
PB15 ------> TIM12_CH2
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_15;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF2_TIM12;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN TIM12_MspPostInit 1 */
|
||||
|
||||
/* USER CODE END TIM12_MspPostInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* tim_pwmHandle)
|
||||
{
|
||||
|
||||
if(tim_pwmHandle->Instance==TIM1)
|
||||
{
|
||||
/* USER CODE BEGIN TIM1_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END TIM1_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_TIM1_CLK_DISABLE();
|
||||
/* USER CODE BEGIN TIM1_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END TIM1_MspDeInit 1 */
|
||||
}
|
||||
else if(tim_pwmHandle->Instance==TIM2)
|
||||
{
|
||||
/* USER CODE BEGIN TIM2_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END TIM2_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_TIM2_CLK_DISABLE();
|
||||
/* USER CODE BEGIN TIM2_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END TIM2_MspDeInit 1 */
|
||||
}
|
||||
else if(tim_pwmHandle->Instance==TIM3)
|
||||
{
|
||||
/* USER CODE BEGIN TIM3_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END TIM3_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_TIM3_CLK_DISABLE();
|
||||
/* USER CODE BEGIN TIM3_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END TIM3_MspDeInit 1 */
|
||||
}
|
||||
else if(tim_pwmHandle->Instance==TIM12)
|
||||
{
|
||||
/* USER CODE BEGIN TIM12_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END TIM12_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_TIM12_CLK_DISABLE();
|
||||
/* USER CODE BEGIN TIM12_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END TIM12_MspDeInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
+1160
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user