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libraries/sdk/ti/devices/msp/peripherals/hw_adc12.h
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/*****************************************************************************
Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_hw_aes__include
#define ti_devices_msp_peripherals_hw_aes__include
/* Filename: hw_aes.h */
/* Revised: 2023-06-13 16:16:59 */
/* Revision: af41564566f5317723aed3e5efba7edbc3faf9e6 */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* AES Registers
******************************************************************************/
#define AES_DMA_TRIG2_OFS ((uint32_t)0x000010B0U)
#define AES_DMA_TRIG1_OFS ((uint32_t)0x00001080U)
#define AES_DMA_TRIG0_OFS ((uint32_t)0x00001050U)
#define AES_CPU_INT_OFS ((uint32_t)0x00001020U)
#define AES_GPRCM_OFS ((uint32_t)0x00000800U)
/** @addtogroup AES_DMA_TRIG2
@{
*/
typedef struct {
__I uint32_t IIDX; /* !< (@ 0x000010B0) Interrupt Index Register */
uint32_t RESERVED0;
__IO uint32_t IMASK; /* !< (@ 0x000010B8) Interrupt mask */
uint32_t RESERVED1;
__I uint32_t RIS; /* !< (@ 0x000010C0) Raw interrupt status */
uint32_t RESERVED2;
__I uint32_t MIS; /* !< (@ 0x000010C8) Masked interrupt status */
uint32_t RESERVED3;
__O uint32_t ISET; /* !< (@ 0x000010D0) Interrupt set */
uint32_t RESERVED4;
__O uint32_t ICLR; /* !< (@ 0x000010D8) Interrupt clear */
} AES_DMA_TRIG2_Regs;
/*@}*/ /* end of group AES_DMA_TRIG2 */
/** @addtogroup AES_DMA_TRIG1
@{
*/
typedef struct {
__I uint32_t IIDX; /* !< (@ 0x00001080) Interrupt Index Register */
uint32_t RESERVED0;
__IO uint32_t IMASK; /* !< (@ 0x00001088) Interrupt mask */
uint32_t RESERVED1;
__I uint32_t RIS; /* !< (@ 0x00001090) Raw interrupt status */
uint32_t RESERVED2;
__I uint32_t MIS; /* !< (@ 0x00001098) Masked interrupt status */
uint32_t RESERVED3;
__O uint32_t ISET; /* !< (@ 0x000010A0) Interrupt set */
uint32_t RESERVED4;
__O uint32_t ICLR; /* !< (@ 0x000010A8) Interrupt clear */
} AES_DMA_TRIG1_Regs;
/*@}*/ /* end of group AES_DMA_TRIG1 */
/** @addtogroup AES_DMA_TRIG0
@{
*/
typedef struct {
__I uint32_t IIDX; /* !< (@ 0x00001050) Interrupt Index Register */
uint32_t RESERVED0;
__IO uint32_t IMASK; /* !< (@ 0x00001058) Interrupt mask */
uint32_t RESERVED1;
__I uint32_t RIS; /* !< (@ 0x00001060) Raw interrupt status */
uint32_t RESERVED2;
__I uint32_t MIS; /* !< (@ 0x00001068) Masked interrupt status */
uint32_t RESERVED3;
__O uint32_t ISET; /* !< (@ 0x00001070) Interrupt set */
uint32_t RESERVED4;
__O uint32_t ICLR; /* !< (@ 0x00001078) Interrupt clear */
} AES_DMA_TRIG0_Regs;
/*@}*/ /* end of group AES_DMA_TRIG0 */
/** @addtogroup AES_CPU_INT
@{
*/
typedef struct {
__I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt Index Register */
uint32_t RESERVED0;
__IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */
uint32_t RESERVED1;
__I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */
uint32_t RESERVED2;
__I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */
uint32_t RESERVED3;
__O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */
uint32_t RESERVED4;
__O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */
} AES_CPU_INT_Regs;
/*@}*/ /* end of group AES_CPU_INT */
/** @addtogroup AES_GPRCM
@{
*/
typedef struct {
__IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */
__O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */
uint32_t RESERVED0[3];
__I uint32_t STAT; /* !< (@ 0x00000814) Status Register */
} AES_GPRCM_Regs;
/*@}*/ /* end of group AES_GPRCM */
/** @addtogroup AES
@{
*/
typedef struct {
uint32_t RESERVED0[512];
AES_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */
uint32_t RESERVED1[512];
__IO uint32_t PDBGCTL; /* !< (@ 0x00001018) Peripheral Debug Control */
uint32_t RESERVED2;
AES_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */
uint32_t RESERVED3;
AES_DMA_TRIG0_Regs DMA_TRIG0; /* !< (@ 0x00001050) */
uint32_t RESERVED4;
AES_DMA_TRIG1_Regs DMA_TRIG1; /* !< (@ 0x00001080) */
uint32_t RESERVED5;
AES_DMA_TRIG2_Regs DMA_TRIG2; /* !< (@ 0x000010B0) */
uint32_t RESERVED6;
__IO uint32_t EVT_MODE; /* !< (@ 0x000010E0) Event Mode */
uint32_t RESERVED7[7];
__IO uint32_t AESACTL0; /* !< (@ 0x00001100) AES accelerator control register 0 */
__IO uint32_t AESACTL1; /* !< (@ 0x00001104) AES accelerator control register 1 */
__IO uint32_t AESASTAT; /* !< (@ 0x00001108) aes accelerator status register */
__O uint32_t AESAKEY; /* !< (@ 0x0000110C) aes accelerator key register */
__O uint32_t AESADIN; /* !< (@ 0x00001110) aes accelerator data in register */
__I uint32_t AESADOUT; /* !< (@ 0x00001114) aes accelerator data out register */
__O uint32_t AESAXDIN; /* !< (@ 0x00001118) aes accelerator xored data in register */
__O uint32_t AESAXIN; /* !< (@ 0x0000111C) aes accelerator xored data in register (no
trigger) */
} AES_Regs;
/*@}*/ /* end of group AES */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* AES Register Control Bits
******************************************************************************/
/* AES_DMA_TRIG2_IIDX Bits */
/* AES_DMA_TRIG2_IIDX[STAT] Bits */
#define AES_DMA_TRIG2_IIDX_STAT_OFS (0) /* !< STAT Offset */
#define AES_DMA_TRIG2_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */
#define AES_DMA_TRIG2_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define AES_DMA_TRIG2_IIDX_STAT_DMA2 ((uint32_t)0x00000004U) /* !< AES trigger 2 DMA */
/* AES_DMA_TRIG2_IMASK Bits */
/* AES_DMA_TRIG2_IMASK[DMA2] Bits */
#define AES_DMA_TRIG2_IMASK_DMA2_OFS (3) /* !< DMA2 Offset */
#define AES_DMA_TRIG2_IMASK_DMA2_MASK ((uint32_t)0x00000008U) /* !< DMA2 event mask. */
#define AES_DMA_TRIG2_IMASK_DMA2_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */
#define AES_DMA_TRIG2_IMASK_DMA2_SET ((uint32_t)0x00000008U) /* !< Set Interrrupt Mask */
/* AES_DMA_TRIG2_RIS Bits */
/* AES_DMA_TRIG2_RIS[DMA2] Bits */
#define AES_DMA_TRIG2_RIS_DMA2_OFS (3) /* !< DMA2 Offset */
#define AES_DMA_TRIG2_RIS_DMA2_MASK ((uint32_t)0x00000008U) /* !< DMA2 event */
#define AES_DMA_TRIG2_RIS_DMA2_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */
#define AES_DMA_TRIG2_RIS_DMA2_SET ((uint32_t)0x00000008U) /* !< Interrupt occured */
/* AES_DMA_TRIG2_MIS Bits */
/* AES_DMA_TRIG2_MIS[DMA2] Bits */
#define AES_DMA_TRIG2_MIS_DMA2_OFS (3) /* !< DMA2 Offset */
#define AES_DMA_TRIG2_MIS_DMA2_MASK ((uint32_t)0x00000008U) /* !< DMA2 event */
#define AES_DMA_TRIG2_MIS_DMA2_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */
#define AES_DMA_TRIG2_MIS_DMA2_SET ((uint32_t)0x00000008U) /* !< Interrupt occured */
/* AES_DMA_TRIG2_ISET Bits */
/* AES_DMA_TRIG2_ISET[DMA2] Bits */
#define AES_DMA_TRIG2_ISET_DMA2_OFS (3) /* !< DMA2 Offset */
#define AES_DMA_TRIG2_ISET_DMA2_MASK ((uint32_t)0x00000008U) /* !< DMA2 event */
#define AES_DMA_TRIG2_ISET_DMA2_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define AES_DMA_TRIG2_ISET_DMA2_SET ((uint32_t)0x00000008U) /* !< Set Interrupt */
/* AES_DMA_TRIG2_ICLR Bits */
/* AES_DMA_TRIG2_ICLR[DMA2] Bits */
#define AES_DMA_TRIG2_ICLR_DMA2_OFS (3) /* !< DMA2 Offset */
#define AES_DMA_TRIG2_ICLR_DMA2_MASK ((uint32_t)0x00000008U) /* !< DMA2 event */
#define AES_DMA_TRIG2_ICLR_DMA2_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define AES_DMA_TRIG2_ICLR_DMA2_CLR ((uint32_t)0x00000008U) /* !< Clear Interrupt */
/* AES_DMA_TRIG1_IIDX Bits */
/* AES_DMA_TRIG1_IIDX[STAT] Bits */
#define AES_DMA_TRIG1_IIDX_STAT_OFS (0) /* !< STAT Offset */
#define AES_DMA_TRIG1_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */
#define AES_DMA_TRIG1_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define AES_DMA_TRIG1_IIDX_STAT_DMA1 ((uint32_t)0x00000003U) /* !< AES trigger 1 DMA */
/* AES_DMA_TRIG1_IMASK Bits */
/* AES_DMA_TRIG1_IMASK[DMA1] Bits */
#define AES_DMA_TRIG1_IMASK_DMA1_OFS (2) /* !< DMA1 Offset */
#define AES_DMA_TRIG1_IMASK_DMA1_MASK ((uint32_t)0x00000004U) /* !< DMA1 event mask. */
#define AES_DMA_TRIG1_IMASK_DMA1_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */
#define AES_DMA_TRIG1_IMASK_DMA1_SET ((uint32_t)0x00000004U) /* !< Set Interrrupt Mask */
/* AES_DMA_TRIG1_RIS Bits */
/* AES_DMA_TRIG1_RIS[DMA1] Bits */
#define AES_DMA_TRIG1_RIS_DMA1_OFS (2) /* !< DMA1 Offset */
#define AES_DMA_TRIG1_RIS_DMA1_MASK ((uint32_t)0x00000004U) /* !< DMA1 event */
#define AES_DMA_TRIG1_RIS_DMA1_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */
#define AES_DMA_TRIG1_RIS_DMA1_SET ((uint32_t)0x00000004U) /* !< Interrupt occured */
/* AES_DMA_TRIG1_MIS Bits */
/* AES_DMA_TRIG1_MIS[DMA1] Bits */
#define AES_DMA_TRIG1_MIS_DMA1_OFS (2) /* !< DMA1 Offset */
#define AES_DMA_TRIG1_MIS_DMA1_MASK ((uint32_t)0x00000004U) /* !< DMA1 event */
#define AES_DMA_TRIG1_MIS_DMA1_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */
#define AES_DMA_TRIG1_MIS_DMA1_SET ((uint32_t)0x00000004U) /* !< Interrupt occured */
/* AES_DMA_TRIG1_ISET Bits */
/* AES_DMA_TRIG1_ISET[DMA1] Bits */
#define AES_DMA_TRIG1_ISET_DMA1_OFS (2) /* !< DMA1 Offset */
#define AES_DMA_TRIG1_ISET_DMA1_MASK ((uint32_t)0x00000004U) /* !< DMA1 event */
#define AES_DMA_TRIG1_ISET_DMA1_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define AES_DMA_TRIG1_ISET_DMA1_SET ((uint32_t)0x00000004U) /* !< Set Interrupt */
/* AES_DMA_TRIG1_ICLR Bits */
/* AES_DMA_TRIG1_ICLR[DMA1] Bits */
#define AES_DMA_TRIG1_ICLR_DMA1_OFS (2) /* !< DMA1 Offset */
#define AES_DMA_TRIG1_ICLR_DMA1_MASK ((uint32_t)0x00000004U) /* !< DMA1 event */
#define AES_DMA_TRIG1_ICLR_DMA1_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define AES_DMA_TRIG1_ICLR_DMA1_CLR ((uint32_t)0x00000004U) /* !< Clear Interrupt */
/* AES_DMA_TRIG0_IIDX Bits */
/* AES_DMA_TRIG0_IIDX[STAT] Bits */
#define AES_DMA_TRIG0_IIDX_STAT_OFS (0) /* !< STAT Offset */
#define AES_DMA_TRIG0_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */
#define AES_DMA_TRIG0_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define AES_DMA_TRIG0_IIDX_STAT_DMA0 ((uint32_t)0x00000002U) /* !< AES trigger 0 DMA */
/* AES_DMA_TRIG0_IMASK Bits */
/* AES_DMA_TRIG0_IMASK[DMA0] Bits */
#define AES_DMA_TRIG0_IMASK_DMA0_OFS (1) /* !< DMA0 Offset */
#define AES_DMA_TRIG0_IMASK_DMA0_MASK ((uint32_t)0x00000002U) /* !< DMA0 event mask. */
#define AES_DMA_TRIG0_IMASK_DMA0_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */
#define AES_DMA_TRIG0_IMASK_DMA0_SET ((uint32_t)0x00000002U) /* !< Set Interrrupt Mask */
/* AES_DMA_TRIG0_RIS Bits */
/* AES_DMA_TRIG0_RIS[DMA0] Bits */
#define AES_DMA_TRIG0_RIS_DMA0_OFS (1) /* !< DMA0 Offset */
#define AES_DMA_TRIG0_RIS_DMA0_MASK ((uint32_t)0x00000002U) /* !< DMA0 event */
#define AES_DMA_TRIG0_RIS_DMA0_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */
#define AES_DMA_TRIG0_RIS_DMA0_SET ((uint32_t)0x00000002U) /* !< Interrupt occured */
/* AES_DMA_TRIG0_MIS Bits */
/* AES_DMA_TRIG0_MIS[DMA0] Bits */
#define AES_DMA_TRIG0_MIS_DMA0_OFS (1) /* !< DMA0 Offset */
#define AES_DMA_TRIG0_MIS_DMA0_MASK ((uint32_t)0x00000002U) /* !< DMA0 event */
#define AES_DMA_TRIG0_MIS_DMA0_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */
#define AES_DMA_TRIG0_MIS_DMA0_SET ((uint32_t)0x00000002U) /* !< Interrupt occured */
/* AES_DMA_TRIG0_ISET Bits */
/* AES_DMA_TRIG0_ISET[DMA0] Bits */
#define AES_DMA_TRIG0_ISET_DMA0_OFS (1) /* !< DMA0 Offset */
#define AES_DMA_TRIG0_ISET_DMA0_MASK ((uint32_t)0x00000002U) /* !< DMA0 */
#define AES_DMA_TRIG0_ISET_DMA0_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define AES_DMA_TRIG0_ISET_DMA0_SET ((uint32_t)0x00000002U) /* !< Set Interrupt */
/* AES_DMA_TRIG0_ICLR Bits */
/* AES_DMA_TRIG0_ICLR[DMA0] Bits */
#define AES_DMA_TRIG0_ICLR_DMA0_OFS (1) /* !< DMA0 Offset */
#define AES_DMA_TRIG0_ICLR_DMA0_MASK ((uint32_t)0x00000002U) /* !< DMA0 event */
#define AES_DMA_TRIG0_ICLR_DMA0_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define AES_DMA_TRIG0_ICLR_DMA0_CLR ((uint32_t)0x00000002U) /* !< Clear Interrupt */
/* AES_CPU_INT_IIDX Bits */
/* AES_CPU_INT_IIDX[STAT] Bits */
#define AES_CPU_INT_IIDX_STAT_OFS (0) /* !< STAT Offset */
#define AES_CPU_INT_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */
#define AES_CPU_INT_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define AES_CPU_INT_IIDX_STAT_AESRDY ((uint32_t)0x00000001U) /* !< AES ready interrupt, set when the
selected AES operation was completed
and the result can be read from
AESADOUT */
/* AES_CPU_INT_IMASK Bits */
/* AES_CPU_INT_IMASK[AESRDY] Bits */
#define AES_CPU_INT_IMASK_AESRDY_OFS (0) /* !< AESRDY Offset */
#define AES_CPU_INT_IMASK_AESRDY_MASK ((uint32_t)0x00000001U) /* !< AES ready interrupt, set when the
selected AES operation was completed
and the result can be read from
AESADOUT. */
#define AES_CPU_INT_IMASK_AESRDY_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */
#define AES_CPU_INT_IMASK_AESRDY_SET ((uint32_t)0x00000001U) /* !< Set Interrrupt Mask */
/* AES_CPU_INT_RIS Bits */
/* AES_CPU_INT_RIS[AESRDY] Bits */
#define AES_CPU_INT_RIS_AESRDY_OFS (0) /* !< AESRDY Offset */
#define AES_CPU_INT_RIS_AESRDY_MASK ((uint32_t)0x00000001U) /* !< AES ready interrupt, set when the
selected AES operation was completed
and the result can be read from
AESADOUT. */
#define AES_CPU_INT_RIS_AESRDY_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */
#define AES_CPU_INT_RIS_AESRDY_SET ((uint32_t)0x00000001U) /* !< Interrupt occured */
/* AES_CPU_INT_MIS Bits */
/* AES_CPU_INT_MIS[AESRDY] Bits */
#define AES_CPU_INT_MIS_AESRDY_OFS (0) /* !< AESRDY Offset */
#define AES_CPU_INT_MIS_AESRDY_MASK ((uint32_t)0x00000001U) /* !< AES ready interrupt, set when the
selected AES operation was completed
and the result can be read from
AESADOUT. */
#define AES_CPU_INT_MIS_AESRDY_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */
#define AES_CPU_INT_MIS_AESRDY_SET ((uint32_t)0x00000001U) /* !< Interrupt occured */
/* AES_CPU_INT_ISET Bits */
/* AES_CPU_INT_ISET[AESRDY] Bits */
#define AES_CPU_INT_ISET_AESRDY_OFS (0) /* !< AESRDY Offset */
#define AES_CPU_INT_ISET_AESRDY_MASK ((uint32_t)0x00000001U) /* !< AES ready interrupt, set when the
selected AES operation was completed
and the result can be read from
AESADOUT. */
#define AES_CPU_INT_ISET_AESRDY_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define AES_CPU_INT_ISET_AESRDY_SET ((uint32_t)0x00000001U) /* !< Set Interrupt */
/* AES_CPU_INT_ICLR Bits */
/* AES_CPU_INT_ICLR[AESRDY] Bits */
#define AES_CPU_INT_ICLR_AESRDY_OFS (0) /* !< AESRDY Offset */
#define AES_CPU_INT_ICLR_AESRDY_MASK ((uint32_t)0x00000001U) /* !< AES ready interrupt, set when the
selected AES operation was completed
and the result can be read from
AESADOUT. */
#define AES_CPU_INT_ICLR_AESRDY_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define AES_CPU_INT_ICLR_AESRDY_CLR ((uint32_t)0x00000001U) /* !< Clear Interrupt */
/* AES_PWREN Bits */
/* AES_PWREN[ENABLE] Bits */
#define AES_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */
#define AES_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */
#define AES_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */
#define AES_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */
/* AES_PWREN[KEY] Bits */
#define AES_PWREN_KEY_OFS (24) /* !< KEY Offset */
#define AES_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */
#define AES_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this
register */
/* AES_RSTCTL Bits */
/* AES_RSTCTL[RESETSTKYCLR] Bits */
#define AES_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */
#define AES_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT
register */
#define AES_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define AES_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */
/* AES_RSTCTL[RESETASSERT] Bits */
#define AES_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */
#define AES_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */
#define AES_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define AES_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */
/* AES_RSTCTL[KEY] Bits */
#define AES_RSTCTL_KEY_OFS (24) /* !< KEY Offset */
#define AES_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */
#define AES_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this
register */
/* AES_STAT Bits */
/* AES_STAT[RESETSTKY] Bits */
#define AES_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */
#define AES_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the
peripheral was reset, since this bit
was cleared by RESETSTKYCLR in the
RSTCTL register */
#define AES_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset
since this bit was last cleared by
RESETSTKYCLR in the RSTCTL register */
#define AES_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the
last bit clear */
/* AES_PDBGCTL Bits */
/* AES_PDBGCTL[FREE] Bits */
#define AES_PDBGCTL_FREE_OFS (0) /* !< FREE Offset */
#define AES_PDBGCTL_FREE_MASK ((uint32_t)0x00000001U) /* !< Free run control */
#define AES_PDBGCTL_FREE_STOP ((uint32_t)0x00000000U) /* !< The peripheral freezes
functionality while the Core Halted
input is asserted and resumes when it
is deasserted. */
#define AES_PDBGCTL_FREE_RUN ((uint32_t)0x00000001U) /* !< The peripheral ignores the state of
the Core Halted input */
/* AES_PDBGCTL[SOFT] Bits */
#define AES_PDBGCTL_SOFT_OFS (1) /* !< SOFT Offset */
#define AES_PDBGCTL_SOFT_MASK ((uint32_t)0x00000002U) /* !< Soft halt boundary control. This
function is only available, if [FREE]
is set to 'STOP' */
#define AES_PDBGCTL_SOFT_IMMEDIATE ((uint32_t)0x00000000U) /* !< The peripheral will halt
immediately, even if the resultant
state will result in corruption if
the system is restarted */
#define AES_PDBGCTL_SOFT_DELAYED ((uint32_t)0x00000002U) /* !< The peripheral blocks the debug
freeze until it has reached a
boundary where it can resume without
corruption */
/* AES_EVT_MODE Bits */
/* AES_EVT_MODE[INT0_CFG] Bits */
#define AES_EVT_MODE_INT0_CFG_OFS (0) /* !< INT0_CFG Offset */
#define AES_EVT_MODE_INT0_CFG_MASK ((uint32_t)0x00000003U) /* !< Event line mode select for event
corresponding to
[IPSTANDARD.INT_EVENT0] */
#define AES_EVT_MODE_INT0_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
disabled. */
#define AES_EVT_MODE_INT0_CFG_SOFTWARE ((uint32_t)0x00000001U) /* !< The interrupt or event line is in
software mode. Software must clear
the RIS. */
#define AES_EVT_MODE_INT0_CFG_HARDWARE ((uint32_t)0x00000002U) /* !< The interrupt or event line is in
hardware mode. The hardware (another
module) clears automatically the
associated RIS flag. */
/* AES_EVT_MODE[EVT1_CFG] Bits */
#define AES_EVT_MODE_EVT1_CFG_OFS (2) /* !< EVT1_CFG Offset */
#define AES_EVT_MODE_EVT1_CFG_MASK ((uint32_t)0x0000000CU) /* !< Event line mode select for event
corresponding to
[IPSTANDARD.INT_EVENT1] */
#define AES_EVT_MODE_EVT1_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
disabled. */
#define AES_EVT_MODE_EVT1_CFG_SOFTWARE ((uint32_t)0x00000004U) /* !< The interrupt or event line is in
software mode. Software must clear
the RIS. */
#define AES_EVT_MODE_EVT1_CFG_HARDWARE ((uint32_t)0x00000008U) /* !< The interrupt or event line is in
hardware mode. The hardware (another
module) clears automatically the
associated RIS flag. */
/* AES_EVT_MODE[EVT2_CFG] Bits */
#define AES_EVT_MODE_EVT2_CFG_OFS (4) /* !< EVT2_CFG Offset */
#define AES_EVT_MODE_EVT2_CFG_MASK ((uint32_t)0x00000030U) /* !< Event line mode select for event
corresponding to
[IPSTANDARD.INT_EVENT2] */
#define AES_EVT_MODE_EVT2_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
disabled. */
#define AES_EVT_MODE_EVT2_CFG_SOFTWARE ((uint32_t)0x00000010U) /* !< The interrupt or event line is in
software mode. Software must clear
the RIS. */
#define AES_EVT_MODE_EVT2_CFG_HARDWARE ((uint32_t)0x00000020U) /* !< The interrupt or event line is in
hardware mode. The hardware (another
module) clears automatically the
associated RIS flag. */
/* AES_EVT_MODE[EVT3_CFG] Bits */
#define AES_EVT_MODE_EVT3_CFG_OFS (6) /* !< EVT3_CFG Offset */
#define AES_EVT_MODE_EVT3_CFG_MASK ((uint32_t)0x000000C0U) /* !< Event line mode select for event
corresponding to
[IPSTANDARD.INT_EVENT2] */
#define AES_EVT_MODE_EVT3_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
disabled. */
#define AES_EVT_MODE_EVT3_CFG_SOFTWARE ((uint32_t)0x00000040U) /* !< The interrupt or event line is in
software mode. Software must clear
the RIS. */
#define AES_EVT_MODE_EVT3_CFG_HARDWARE ((uint32_t)0x00000080U) /* !< The interrupt or event line is in
hardware mode. The hardware (another
module) clears automatically the
associated RIS flag. */
/* AES_AESACTL0 Bits */
/* AES_AESACTL0[OPX] Bits */
#define AES_AESACTL0_OPX_OFS (0) /* !< OPX Offset */
#define AES_AESACTL0_OPX_MASK ((uint32_t)0x00000003U) /* !< AES operation. The AESOPx bits are
not reset by AESSWRST = 1. Writes are
ignored when AESCMEN = 1 and
AESBLKCNTx > 0. 00b = Encryption. 01b
= Decryption. The provided key is the
same key used for encryption. 10b =
Generate first round key required for
decryption. 11b = Decryption. The
provided key is the first round key
required for decryption. */
#define AES_AESACTL0_OPX_OP0 ((uint32_t)0x00000000U) /* !< Encryption */
#define AES_AESACTL0_OPX_OP1 ((uint32_t)0x00000001U) /* !< Decryption. The provided key is the
same key used for encryption. */
#define AES_AESACTL0_OPX_OP2 ((uint32_t)0x00000002U) /* !< Generate first round key required
for decryption. */
#define AES_AESACTL0_OPX_OP3 ((uint32_t)0x00000003U) /* !< Decryption. The provided key is the
first round key required for
decryption. */
/* AES_AESACTL0[KLX] Bits */
#define AES_AESACTL0_KLX_OFS (2) /* !< KLX Offset */
#define AES_AESACTL0_KLX_MASK ((uint32_t)0x0000000CU) /* !< AES key length. These bits define
which of the 1 AES standards is
performed. The AESKLx bits are not
reset by AESSWRST = 1. Writes are
ignored when AESCMEN = 1 and
AESBLKCNTx > 0. */
#define AES_AESACTL0_KLX_AES128 ((uint32_t)0x00000000U) /* !< The key size is 128 bit. */
#define AES_AESACTL0_KLX_AES256 ((uint32_t)0x00000008U) /* !< The key size is 256 bit. */
/* AES_AESACTL0[CMX] Bits */
#define AES_AESACTL0_CMX_OFS (5) /* !< CMX Offset */
#define AES_AESACTL0_CMX_MASK ((uint32_t)0x00000060U) /* !< AES cipher mode select. These bits
are ignored for AESCMEN = 0. Writes
are ignored when AESCMEN = 1 and
AESBLKCNTx > 0. 00b = ECB 01b = CBC
10b = OFB 11b = CFB */
#define AES_AESACTL0_CMX_ECB ((uint32_t)0x00000000U) /* !< ECB */
#define AES_AESACTL0_CMX_CBC ((uint32_t)0x00000020U) /* !< CBC */
#define AES_AESACTL0_CMX_OFB ((uint32_t)0x00000040U) /* !< OFB */
#define AES_AESACTL0_CMX_CFB ((uint32_t)0x00000060U) /* !< CFB */
/* AES_AESACTL0[SWRST] Bits */
#define AES_AESACTL0_SWRST_OFS (7) /* !< SWRST Offset */
#define AES_AESACTL0_SWRST_MASK ((uint32_t)0x00000080U) /* !< AES software reset. Immediately
resets the complete AES accelerator
module even when busy except for the
AESRDYIE, the AESKLx and the AESOPx
bits. It also clears the (internal)
state memory. The AESSWRST bit is
automatically reset and is always
read as zero. 0b = No reset 1b =
Reset AES accelerator module */
#define AES_AESACTL0_SWRST_NORST ((uint32_t)0x00000000U) /* !< No reset. */
#define AES_AESACTL0_SWRST_RST ((uint32_t)0x00000080U) /* !< Reset AES accelerator module. */
/* AES_AESACTL0[ERRFG] Bits */
#define AES_AESACTL0_ERRFG_OFS (11) /* !< ERRFG Offset */
#define AES_AESACTL0_ERRFG_MASK ((uint32_t)0x00000800U) /* !< AES error flag. AESAKEY or AESADIN
were written while an AES operation
was in progress. The bit must be
cleared by software. 0b = No error 1b
= Error occurred */
#define AES_AESACTL0_ERRFG_NOERR ((uint32_t)0x00000000U) /* !< No error */
#define AES_AESACTL0_ERRFG_ERR ((uint32_t)0x00000800U) /* !< Error occurred */
/* AES_AESACTL0[CMEN] Bits */
#define AES_AESACTL0_CMEN_OFS (15) /* !< CMEN Offset */
#define AES_AESACTL0_CMEN_MASK ((uint32_t)0x00008000U) /* !< AESCMEN enables the support of the
cipher modes ECB, CBC, OFB and CFB
together with the DMA. Writes are
ignored when AESCMEN = 1 and
AESBLKCNTx > 0. 0 = No DMA triggers
are generated. 1 = DMA cipher mode
support operation is enabled and the
corresponding DMA triggers are
generated. */
#define AES_AESACTL0_CMEN_DISABLE ((uint32_t)0x00000000U) /* !< No DMA triggers are generated. */
#define AES_AESACTL0_CMEN_ENABLE ((uint32_t)0x00008000U) /* !< DMA cipher mode support operation
is enabled and the corresponding DMA
triggers are generated. */
/* AES_AESACTL1 Bits */
/* AES_AESACTL1[BLKCNTX] Bits */
#define AES_AESACTL1_BLKCNTX_OFS (0) /* !< BLKCNTX Offset */
#define AES_AESACTL1_BLKCNTX_MASK ((uint32_t)0x000000FFU) /* !< Cipher Block Counter. Number of
blocks to be encrypted or decrypted
with block cipher modes enabled
(AESCMEN = 1). Ignored if AESCMEN =
0. The block counter decrements with
each performed encryption or
decryption. Writes are ignored when
AESCMEN = 1 and AESBLKCNTx > 0. */
#define AES_AESACTL1_BLKCNTX_MINNUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define AES_AESACTL1_BLKCNTX_ENABLE ((uint32_t)0x000000FFU) /* !< Highest possible value */
/* AES_AESASTAT Bits */
/* AES_AESASTAT[BUSY] Bits */
#define AES_AESASTAT_BUSY_OFS (0) /* !< BUSY Offset */
#define AES_AESASTAT_BUSY_MASK ((uint32_t)0x00000001U) /* !< AES accelerator module busy;
encryption, decryption, or key
generation in progress. 0 = Not busy
1 = Busy */
#define AES_AESASTAT_BUSY_IDLE ((uint32_t)0x00000000U) /* !< Not busy */
#define AES_AESASTAT_BUSY_BUSY ((uint32_t)0x00000001U) /* !< Busy */
/* AES_AESASTAT[KEYWR] Bits */
#define AES_AESASTAT_KEYWR_OFS (1) /* !< KEYWR Offset */
#define AES_AESASTAT_KEYWR_MASK ((uint32_t)0x00000002U) /* !< All bytes written to AESAKEY. This
bit can be modified by software but
it must not be reset by software (10)
if AESCMEN=1. Changing its state by
software also resets the AESKEYCNTx
bits. AESKEYWR is reset by PUC,
AESSWRST, an error condition,
changing AESOPx, changing AESKLx, and
the start to (over)write a new key.
Because it is reset when AESOPx is
changed it can be set by software
again to indicate that the loaded key
is still valid. */
#define AES_AESASTAT_KEYWR_NALL ((uint32_t)0x00000000U) /* !< Not all bytes written */
#define AES_AESASTAT_KEYWR_ALL ((uint32_t)0x00000002U) /* !< All bytes written */
/* AES_AESASTAT[DINWR] Bits */
#define AES_AESASTAT_DINWR_OFS (2) /* !< DINWR Offset */
#define AES_AESASTAT_DINWR_MASK ((uint32_t)0x00000004U) /* !< All 16 bytes written to AESADIN,
AESAXDIN or AESAXIN. Changing its
state by software also resets the
AESDINCNTx bits. AESDINWR is reset by
PUC, AESSWRST, an error condition,
changing AESOPx, changing AESKLx, the
start to (over)write the data, and
when the AES accelerator is busy.
Because it is reset when AESOPx or
AESKLx is changed it can be set by
software again to indicate that the
current data is still valid. 0 = Not
all bytes written 1 = All bytes
written */
#define AES_AESASTAT_DINWR_NALL ((uint32_t)0x00000000U) /* !< Not all bytes written */
#define AES_AESASTAT_DINWR_ALL ((uint32_t)0x00000004U) /* !< All bytes written */
/* AES_AESASTAT[DOUTRD] Bits */
#define AES_AESASTAT_DOUTRD_OFS (3) /* !< DOUTRD Offset */
#define AES_AESASTAT_DOUTRD_MASK ((uint32_t)0x00000008U) /* !< All 16 bytes read from AESADOUT.
AESDOUTRD is reset by PUC, AESSWRST,
an error condition, changing AESOPx,
changing AESKLx, when the AES
accelerator is busy, and when the
output data is read again. 0 = Not
all bytes read 1 = All bytes read */
#define AES_AESASTAT_DOUTRD_NALL ((uint32_t)0x00000000U) /* !< Not all bytes read */
#define AES_AESASTAT_DOUTRD_ALL ((uint32_t)0x00000008U) /* !< All bytes read */
/* AES_AESASTAT[KEYCNTX] Bits */
#define AES_AESASTAT_KEYCNTX_OFS (4) /* !< KEYCNTX Offset */
#define AES_AESASTAT_KEYCNTX_MASK ((uint32_t)0x000000F0U) /* !< Bytes written to AESAKEY when
AESKLx = 00, half-words written to
AESAKEY if AESKLx = b10. Reset when
AESKEYWR is reset. If AESKEYCNTx = 0
and AESKEYWR = 0, no bytes were
written. If AESKEYCNTx = 0 and
AESKEYWR = 1, all bytes were written. */
#define AES_AESASTAT_KEYCNTX_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESASTAT_KEYCNTX_MAXNUM ((uint32_t)0x000000F0U) /* !< Highest possible value */
/* AES_AESASTAT[DINCNTX] Bits */
#define AES_AESASTAT_DINCNTX_OFS (8) /* !< DINCNTX Offset */
#define AES_AESASTAT_DINCNTX_MASK ((uint32_t)0x00000F00U) /* !< Bytes written to AESADIN, AESAXDIN
or AESAXIN. Reset when AESDINWR is
reset. If AESDINCNTx = 0 and AESDINWR
= 0, no bytes were written. If
AESDINCNTx = 0 and AESDINWR = 1, all
bytes were written. */
#define AES_AESASTAT_DINCNTX_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESASTAT_DINCNTX_MAXNUM ((uint32_t)0x00000F00U) /* !< Highest possible value */
/* AES_AESASTAT[DOUTCNTX] Bits */
#define AES_AESASTAT_DOUTCNTX_OFS (12) /* !< DOUTCNTX Offset */
#define AES_AESASTAT_DOUTCNTX_MASK ((uint32_t)0x0000F000U) /* !< Bytes read from AESADOUT. Reset
when AESDOUTRD is reset. If
AESDOUTCNTx = 0 and AESDOUTRD = 0, no
bytes were read. If AESDOUTCNTx = 0
and AESDOUTRD = 1, all bytes were
read. */
#define AES_AESASTAT_DOUTCNTX_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESASTAT_DOUTCNTX_MAXNUM ((uint32_t)0x0000F000U) /* !< Highest possible value */
/* AES_AESAKEY Bits */
/* AES_AESAKEY[KEY0X] Bits */
#define AES_AESAKEY_KEY0X_OFS (0) /* !< KEY0X Offset */
#define AES_AESAKEY_KEY0X_MASK ((uint32_t)0x000000FFU) /* !< AES key byte n when AESAKEY is
written as word. AES next key byte
when AESAKEY is written as byte. Do
not mix word and byte access. Always
reads as zero. The key is reset by
PUC or by AESSWRST = 1. */
#define AES_AESAKEY_KEY0X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESAKEY_KEY0X_MAXNUM ((uint32_t)0x000000FFU) /* !< Highest possible value */
/* AES_AESAKEY[KEY1X] Bits */
#define AES_AESAKEY_KEY1X_OFS (8) /* !< KEY1X Offset */
#define AES_AESAKEY_KEY1X_MASK ((uint32_t)0x0000FF00U) /* !< AES key byte n+1 when AESAKEY is
written as word. Do not use these
bits for byte access. Do not mix word
and byte access. Always reads as
zero. The key is reset by PUC or by
AESSWRST = 1. */
#define AES_AESAKEY_KEY1X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESAKEY_KEY1X_MAXNUM ((uint32_t)0x0000FF00U) /* !< Highest possible value */
/* AES_AESAKEY[KEY2X] Bits */
#define AES_AESAKEY_KEY2X_OFS (16) /* !< KEY2X Offset */
#define AES_AESAKEY_KEY2X_MASK ((uint32_t)0x00FF0000U) /* !< AES key byte n+2 when AESAKEY is
written as word. Do not use these
bits for byte access. Do not mix word
and byte access. Always reads as
zero. The key is reset by PUC or by
AESSWRST = 1. */
#define AES_AESAKEY_KEY2X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESAKEY_KEY2X_MAXNUM ((uint32_t)0x00FF0000U) /* !< Highest possible value */
/* AES_AESAKEY[KEY3X] Bits */
#define AES_AESAKEY_KEY3X_OFS (24) /* !< KEY3X Offset */
#define AES_AESAKEY_KEY3X_MASK ((uint32_t)0xFF000000U) /* !< AES key byte n+3 when AESAKEY is
written as word. Do not use these
bits for byte access. Do not mix word
and byte access. Always reads as
zero. The key is reset by PUC or by
AESSWRST = 1. */
#define AES_AESAKEY_KEY3X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESAKEY_KEY3X_MAXNUM ((uint32_t)0xFF000000U) /* !< Highest possible value */
/* AES_AESADIN Bits */
/* AES_AESADIN[DIN0X] Bits */
#define AES_AESADIN_DIN0X_OFS (0) /* !< DIN0X Offset */
#define AES_AESADIN_DIN0X_MASK ((uint32_t)0x000000FFU) /* !< AES data in byte n when AESADIN is
written as word. AES next data in
byte when AESADIN is written as byte.
Do not mix word and byte access.
Always reads as zero. */
#define AES_AESADIN_DIN0X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESADIN_DIN0X_MAXNUM ((uint32_t)0x000000FFU) /* !< Highest possible value */
/* AES_AESADIN[DIN1X] Bits */
#define AES_AESADIN_DIN1X_OFS (8) /* !< DIN1X Offset */
#define AES_AESADIN_DIN1X_MASK ((uint32_t)0x0000FF00U) /* !< AES data in byte n+1 when AESADIN
is written as word. Do not use these
bits for byte access. Do not mix word
and byte access. Always reads as
zero. */
#define AES_AESADIN_DIN1X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESADIN_DIN1X_MAXNUM ((uint32_t)0x0000FF00U) /* !< Highest possible value */
/* AES_AESADIN[DIN2X] Bits */
#define AES_AESADIN_DIN2X_OFS (16) /* !< DIN2X Offset */
#define AES_AESADIN_DIN2X_MASK ((uint32_t)0x00FF0000U) /* !< AES data in byte n+2 when AESADIN
is written as word. Do not use these
bits for byte access. Do not mix word
and byte access. Always reads as
zero. */
#define AES_AESADIN_DIN2X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESADIN_DIN2X_MAXNUM ((uint32_t)0x00FF0000U) /* !< Highest possible value */
/* AES_AESADIN[DIN3X] Bits */
#define AES_AESADIN_DIN3X_OFS (24) /* !< DIN3X Offset */
#define AES_AESADIN_DIN3X_MASK ((uint32_t)0xFF000000U) /* !< AES data in byte n+3 when AESADIN
is written as word. Do not use these
bits for byte access. Do not mix word
and byte access. Always reads as
zero. */
#define AES_AESADIN_DIN3X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESADIN_DIN3X_MAXNUM ((uint32_t)0xFF000000U) /* !< Highest possible value */
/* AES_AESADOUT Bits */
/* AES_AESADOUT[DOUT0X] Bits */
#define AES_AESADOUT_DOUT0X_OFS (0) /* !< DOUT0X Offset */
#define AES_AESADOUT_DOUT0X_MASK ((uint32_t)0x000000FFU) /* !< AES data out byte n when AESADOUT
is read as word. AES next data out
byte when AESADOUT is read as byte.
Do not mix word and byte access. */
#define AES_AESADOUT_DOUT0X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESADOUT_DOUT0X_MAXNUM ((uint32_t)0x000000FFU) /* !< Highest possible value */
/* AES_AESADOUT[DOUT1X] Bits */
#define AES_AESADOUT_DOUT1X_OFS (8) /* !< DOUT1X Offset */
#define AES_AESADOUT_DOUT1X_MASK ((uint32_t)0x0000FF00U) /* !< AES data out byte n+1 when AESADOUT
is read as word. Do not use these
bits for byte access. Do not mix word
and byte access. */
#define AES_AESADOUT_DOUT1X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESADOUT_DOUT1X_MAXNUM ((uint32_t)0x0000FF00U) /* !< Highest possible value */
/* AES_AESADOUT[DOUT2X] Bits */
#define AES_AESADOUT_DOUT2X_OFS (16) /* !< DOUT2X Offset */
#define AES_AESADOUT_DOUT2X_MASK ((uint32_t)0x00FF0000U) /* !< AES data out byte n+2 when AESADOUT
is read as word. Do not use these
bits for byte access. Do not mix word
and byte access. */
#define AES_AESADOUT_DOUT2X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESADOUT_DOUT2X_MAXNUM ((uint32_t)0x00FF0000U) /* !< Highest possible value */
/* AES_AESADOUT[DOUT3X] Bits */
#define AES_AESADOUT_DOUT3X_OFS (24) /* !< DOUT3X Offset */
#define AES_AESADOUT_DOUT3X_MASK ((uint32_t)0xFF000000U) /* !< AES data out byte n+3 when AESADOUT
is read as word. Do not use these
bits for byte access. Do not mix word
and byte access. */
#define AES_AESADOUT_DOUT3X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESADOUT_DOUT3X_MAXNUM ((uint32_t)0xFF000000U) /* !< Highest possible value */
/* AES_AESAXDIN Bits */
/* AES_AESAXDIN[XDIN0X] Bits */
#define AES_AESAXDIN_XDIN0X_OFS (0) /* !< XDIN0X Offset */
#define AES_AESAXDIN_XDIN0X_MASK ((uint32_t)0x000000FFU) /* !< AES data in byte n when AESAXDIN is
written as word. AES next data in
byte when AESAXDIN is written as
byte. Do not mix word and byte
access. Always reads as zero. */
#define AES_AESAXDIN_XDIN0X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESAXDIN_XDIN0X_MAXNUM ((uint32_t)0x000000FFU) /* !< Highest possible value */
/* AES_AESAXDIN[XDIN1X] Bits */
#define AES_AESAXDIN_XDIN1X_OFS (8) /* !< XDIN1X Offset */
#define AES_AESAXDIN_XDIN1X_MASK ((uint32_t)0x0000FF00U) /* !< AES data in byte n+1 when AESAXDIN
is written as word. Do not use these
bits for byte access. Do not mix word
and byte access. Always reads as
zero. */
#define AES_AESAXDIN_XDIN1X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESAXDIN_XDIN1X_MAXNUM ((uint32_t)0x0000FF00U) /* !< Highest possible value */
/* AES_AESAXDIN[XDIN2X] Bits */
#define AES_AESAXDIN_XDIN2X_OFS (16) /* !< XDIN2X Offset */
#define AES_AESAXDIN_XDIN2X_MASK ((uint32_t)0x00FF0000U) /* !< AES data in byte n+2 when AESAXDIN
is written as word. Do not use these
bits for byte access. Do not mix word
and byte access. Always reads as
zero. */
#define AES_AESAXDIN_XDIN2X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESAXDIN_XDIN2X_MAXNUM ((uint32_t)0x00FF0000U) /* !< Highest possible value */
/* AES_AESAXDIN[XDIN3X] Bits */
#define AES_AESAXDIN_XDIN3X_OFS (24) /* !< XDIN3X Offset */
#define AES_AESAXDIN_XDIN3X_MASK ((uint32_t)0xFF000000U) /* !< AES data in byte n+3 when AESAXDIN
is written as word. Do not use these
bits for byte access. Do not mix word
and byte access. Always reads as
zero. */
#define AES_AESAXDIN_XDIN3X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESAXDIN_XDIN3X_MAXNUM ((uint32_t)0xFF000000U) /* !< Highest possible value */
/* AES_AESAXIN Bits */
/* AES_AESAXIN[XIN0X] Bits */
#define AES_AESAXIN_XIN0X_OFS (0) /* !< XIN0X Offset */
#define AES_AESAXIN_XIN0X_MASK ((uint32_t)0x000000FFU) /* !< AES data in byte n when AESAXIN is
written as word. AES next data in
byte when AESAXIN is written as byte.
Do not mix word and byte access.
Always reads as zero. */
#define AES_AESAXIN_XIN0X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESAXIN_XIN0X_MAXNUM ((uint32_t)0x000000FFU) /* !< Highest possible value */
/* AES_AESAXIN[XIN1X] Bits */
#define AES_AESAXIN_XIN1X_OFS (8) /* !< XIN1X Offset */
#define AES_AESAXIN_XIN1X_MASK ((uint32_t)0x0000FF00U) /* !< AES data in byte n+1 when AESAXIN
is written as word. Do not use these
bits for byte access. Do not mix word
and byte access. Always reads as
zero. */
#define AES_AESAXIN_XIN1X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESAXIN_XIN1X_MAXNUM ((uint32_t)0x0000FF00U) /* !< Highest possible value */
/* AES_AESAXIN[XIN2X] Bits */
#define AES_AESAXIN_XIN2X_OFS (16) /* !< XIN2X Offset */
#define AES_AESAXIN_XIN2X_MASK ((uint32_t)0x00FF0000U) /* !< AES data in byte n+2 when AESAXIN
is written as word. Do not use these
bits for byte access. Do not mix word
and byte access. Always reads as
zero. */
#define AES_AESAXIN_XIN2X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESAXIN_XIN2X_MAXNUM ((uint32_t)0x00FF0000U) /* !< Highest possible value */
/* AES_AESAXIN[XIN3X] Bits */
#define AES_AESAXIN_XIN3X_OFS (24) /* !< XIN3X Offset */
#define AES_AESAXIN_XIN3X_MASK ((uint32_t)0xFF000000U) /* !< AES data in byte n+3 when AESAXIN
is written as word. Do not use these
bits for byte access. Do not mix word
and byte access. Always reads as
zero. */
#define AES_AESAXIN_XIN3X_MINNUM ((uint32_t)0x00000000U) /* !< Smallest possible value */
#define AES_AESAXIN_XIN3X_MAXNUM ((uint32_t)0xFF000000U) /* !< Highest possible value */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_hw_aes__include */
libraries/sdk/ti/devices/msp/peripherals/hw_aesadv.h
+1303
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libraries/sdk/ti/devices/msp/peripherals/hw_comp.h
+825
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@@ -0,0 +1,825 @@
/*****************************************************************************
Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_hw_comp__include
#define ti_devices_msp_peripherals_hw_comp__include
/* Filename: hw_comp.h */
/* Revised: 2023-05-10 21:23:38 */
/* Revision: 5c29864c187960f76e656cbc0f0f844cdb69a263 */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* COMP Registers
******************************************************************************/
#define COMP_GEN_EVENT_OFS ((uint32_t)0x00001050U)
#define COMP_CPU_INT_OFS ((uint32_t)0x00001020U)
#define COMP_GPRCM_OFS ((uint32_t)0x00000800U)
/** @addtogroup COMP_GEN_EVENT
@{
*/
typedef struct {
__I uint32_t IIDX; /* !< (@ 0x00001050) Interrupt index */
uint32_t RESERVED0;
__IO uint32_t IMASK; /* !< (@ 0x00001058) Interrupt mask */
uint32_t RESERVED1;
__I uint32_t RIS; /* !< (@ 0x00001060) Raw interrupt status */
uint32_t RESERVED2;
__I uint32_t MIS; /* !< (@ 0x00001068) Masked interrupt status */
uint32_t RESERVED3;
__O uint32_t ISET; /* !< (@ 0x00001070) Interrupt set */
uint32_t RESERVED4;
__O uint32_t ICLR; /* !< (@ 0x00001078) Interrupt clear */
} COMP_GEN_EVENT_Regs;
/*@}*/ /* end of group COMP_GEN_EVENT */
/** @addtogroup COMP_CPU_INT
@{
*/
typedef struct {
__I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */
uint32_t RESERVED0;
__IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */
uint32_t RESERVED1;
__I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */
uint32_t RESERVED2;
__I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */
uint32_t RESERVED3;
__O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */
uint32_t RESERVED4;
__O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */
} COMP_CPU_INT_Regs;
/*@}*/ /* end of group COMP_CPU_INT */
/** @addtogroup COMP_GPRCM
@{
*/
typedef struct {
__IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */
__O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */
__IO uint32_t CLKCFG; /* !< (@ 0x00000808) Peripheral Clock Configuration Register */
uint32_t RESERVED0[2];
__I uint32_t STAT; /* !< (@ 0x00000814) Status Register */
} COMP_GPRCM_Regs;
/*@}*/ /* end of group COMP_GPRCM */
/** @addtogroup COMP
@{
*/
typedef struct {
uint32_t RESERVED0[256];
__IO uint32_t FSUB_0; /* !< (@ 0x00000400) Subscriber Port 0 */
__IO uint32_t FSUB_1; /* !< (@ 0x00000404) Subscriber Port 1 */
uint32_t RESERVED1[15];
__IO uint32_t FPUB_1; /* !< (@ 0x00000444) Publisher port 1 */
uint32_t RESERVED2[238];
COMP_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */
uint32_t RESERVED3[514];
COMP_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */
uint32_t RESERVED4;
COMP_GEN_EVENT_Regs GEN_EVENT; /* !< (@ 0x00001050) */
uint32_t RESERVED5[25];
__IO uint32_t EVT_MODE; /* !< (@ 0x000010E0) Event Mode */
uint32_t RESERVED6[6];
__I uint32_t DESC; /* !< (@ 0x000010FC) Module Description */
__IO uint32_t CTL0; /* !< (@ 0x00001100) Control 0 */
__IO uint32_t CTL1; /* !< (@ 0x00001104) Control 1 */
__IO uint32_t CTL2; /* !< (@ 0x00001108) Control 2 */
__IO uint32_t CTL3; /* !< (@ 0x0000110C) Control 3 */
uint32_t RESERVED7[4];
__I uint32_t STAT; /* !< (@ 0x00001120) Status */
} COMP_Regs;
/*@}*/ /* end of group COMP */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* COMP Register Control Bits
******************************************************************************/
/* COMP_GEN_EVENT_IIDX Bits */
/* COMP_GEN_EVENT_IIDX[STAT] Bits */
#define COMP_GEN_EVENT_IIDX_STAT_OFS (0) /* !< STAT Offset */
#define COMP_GEN_EVENT_IIDX_STAT_MASK ((uint32_t)0x00000003U) /* !< Interrupt index status */
#define COMP_GEN_EVENT_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No pending interrupt */
#define COMP_GEN_EVENT_IIDX_STAT_COMPIFG ((uint32_t)0x00000002U) /* !< Comparator output interrupt */
#define COMP_GEN_EVENT_IIDX_STAT_COMPINVIFG ((uint32_t)0x00000003U) /* !< Comparator output inverted
interrupt */
#define COMP_GEN_EVENT_IIDX_STAT_OUTRDYIFG ((uint32_t)0x00000004U) /* !< Comparator output ready interrupt */
/* COMP_GEN_EVENT_IMASK Bits */
/* COMP_GEN_EVENT_IMASK[COMPIFG] Bits */
#define COMP_GEN_EVENT_IMASK_COMPIFG_OFS (1) /* !< COMPIFG Offset */
#define COMP_GEN_EVENT_IMASK_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Masks COMPIFG */
#define COMP_GEN_EVENT_IMASK_COMPIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define COMP_GEN_EVENT_IMASK_COMPIFG_SET ((uint32_t)0x00000002U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* COMP_GEN_EVENT_IMASK[COMPINVIFG] Bits */
#define COMP_GEN_EVENT_IMASK_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
#define COMP_GEN_EVENT_IMASK_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Masks COMPINVIFG */
#define COMP_GEN_EVENT_IMASK_COMPINVIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define COMP_GEN_EVENT_IMASK_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* COMP_GEN_EVENT_IMASK[OUTRDYIFG] Bits */
#define COMP_GEN_EVENT_IMASK_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
#define COMP_GEN_EVENT_IMASK_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Masks OUTRDYIFG */
#define COMP_GEN_EVENT_IMASK_OUTRDYIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define COMP_GEN_EVENT_IMASK_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* COMP_GEN_EVENT_RIS Bits */
/* COMP_GEN_EVENT_RIS[COMPIFG] Bits */
#define COMP_GEN_EVENT_RIS_COMPIFG_OFS (1) /* !< COMPIFG Offset */
#define COMP_GEN_EVENT_RIS_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Raw interrupt status for comparator
output interrupt flag. The IES bit
defines the transition of the
comparator output setting this bit. */
#define COMP_GEN_EVENT_RIS_COMPIFG_CLR ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define COMP_GEN_EVENT_RIS_COMPIFG_SET ((uint32_t)0x00000002U) /* !< Interrupt pending */
/* COMP_GEN_EVENT_RIS[COMPINVIFG] Bits */
#define COMP_GEN_EVENT_RIS_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
#define COMP_GEN_EVENT_RIS_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Raw interrupt status for comparator
output inverted interrupt flag. The
IES bit defines the transition of the
comparator output setting this bit. */
#define COMP_GEN_EVENT_RIS_COMPINVIFG_CLR ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define COMP_GEN_EVENT_RIS_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< Interrupt pending */
/* COMP_GEN_EVENT_RIS[OUTRDYIFG] Bits */
#define COMP_GEN_EVENT_RIS_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
#define COMP_GEN_EVENT_RIS_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Raw interrupt status for comparator
output ready interrupt flag. This bit
is set when the comparator output is
valid. */
#define COMP_GEN_EVENT_RIS_OUTRDYIFG_CLR ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define COMP_GEN_EVENT_RIS_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< Interrupt pending */
/* COMP_GEN_EVENT_MIS Bits */
/* COMP_GEN_EVENT_MIS[COMPIFG] Bits */
#define COMP_GEN_EVENT_MIS_COMPIFG_OFS (1) /* !< COMPIFG Offset */
#define COMP_GEN_EVENT_MIS_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt status for COMPIFG */
#define COMP_GEN_EVENT_MIS_COMPIFG_CLR ((uint32_t)0x00000000U) /* !< COMPIFG does not request an
interrupt service routine */
#define COMP_GEN_EVENT_MIS_COMPIFG_SET ((uint32_t)0x00000002U) /* !< COMPIFG requests an interrupt
service routine */
/* COMP_GEN_EVENT_MIS[COMPINVIFG] Bits */
#define COMP_GEN_EVENT_MIS_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
#define COMP_GEN_EVENT_MIS_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Masked interrupt status for
COMPINVIFG */
#define COMP_GEN_EVENT_MIS_COMPINVIFG_CLR ((uint32_t)0x00000000U) /* !< COMPINVIFG does not request an
interrupt service routine */
#define COMP_GEN_EVENT_MIS_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< COMPINVIFG requests an interrupt
service routine */
/* COMP_GEN_EVENT_MIS[OUTRDYIFG] Bits */
#define COMP_GEN_EVENT_MIS_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
#define COMP_GEN_EVENT_MIS_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Masked interrupt status for
OUTRDYIFG */
#define COMP_GEN_EVENT_MIS_OUTRDYIFG_CLR ((uint32_t)0x00000000U) /* !< OUTRDYIFG does not request an
interrupt service routine */
#define COMP_GEN_EVENT_MIS_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< OUTRDYIFG requests an interrupt
service routine */
/* COMP_GEN_EVENT_ISET Bits */
/* COMP_GEN_EVENT_ISET[COMPIFG] Bits */
#define COMP_GEN_EVENT_ISET_COMPIFG_OFS (1) /* !< COMPIFG Offset */
#define COMP_GEN_EVENT_ISET_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Sets COMPIFG in RIS register */
#define COMP_GEN_EVENT_ISET_COMPIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define COMP_GEN_EVENT_ISET_COMPIFG_SET ((uint32_t)0x00000002U) /* !< RIS bit corresponding to COMPIFG is
set */
/* COMP_GEN_EVENT_ISET[COMPINVIFG] Bits */
#define COMP_GEN_EVENT_ISET_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
#define COMP_GEN_EVENT_ISET_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Sets COMPINVIFG in RIS register */
#define COMP_GEN_EVENT_ISET_COMPINVIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define COMP_GEN_EVENT_ISET_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< RIS bit corresponding to COMPINVIFG
is set */
/* COMP_GEN_EVENT_ISET[OUTRDYIFG] Bits */
#define COMP_GEN_EVENT_ISET_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
#define COMP_GEN_EVENT_ISET_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Sets OUTRDYIFG in RIS register */
#define COMP_GEN_EVENT_ISET_OUTRDYIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define COMP_GEN_EVENT_ISET_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< RIS bit corresponding to OUTRDYIFG
is set */
/* COMP_GEN_EVENT_ICLR Bits */
/* COMP_GEN_EVENT_ICLR[COMPIFG] Bits */
#define COMP_GEN_EVENT_ICLR_COMPIFG_OFS (1) /* !< COMPIFG Offset */
#define COMP_GEN_EVENT_ICLR_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Clears COMPIFG in RIS register */
#define COMP_GEN_EVENT_ICLR_COMPIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define COMP_GEN_EVENT_ICLR_COMPIFG_CLR ((uint32_t)0x00000002U) /* !< RIS bit corresponding to COMPIFG is
cleared */
/* COMP_GEN_EVENT_ICLR[COMPINVIFG] Bits */
#define COMP_GEN_EVENT_ICLR_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
#define COMP_GEN_EVENT_ICLR_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Clears COMPINVIFG in RIS register */
#define COMP_GEN_EVENT_ICLR_COMPINVIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define COMP_GEN_EVENT_ICLR_COMPINVIFG_CLR ((uint32_t)0x00000004U) /* !< RIS bit corresponding to COMPINVIFG
is cleared */
/* COMP_GEN_EVENT_ICLR[OUTRDYIFG] Bits */
#define COMP_GEN_EVENT_ICLR_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
#define COMP_GEN_EVENT_ICLR_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Clears OUTRDYIFG in RIS register */
#define COMP_GEN_EVENT_ICLR_OUTRDYIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define COMP_GEN_EVENT_ICLR_OUTRDYIFG_CLR ((uint32_t)0x00000008U) /* !< RIS bit corresponding to OUTRDYIFG
is cleared */
/* COMP_CPU_INT_IIDX Bits */
/* COMP_CPU_INT_IIDX[STAT] Bits */
#define COMP_CPU_INT_IIDX_STAT_OFS (0) /* !< STAT Offset */
#define COMP_CPU_INT_IIDX_STAT_MASK ((uint32_t)0x00000003U) /* !< Interrupt index status */
#define COMP_CPU_INT_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No pending interrupt */
#define COMP_CPU_INT_IIDX_STAT_COMPIFG ((uint32_t)0x00000002U) /* !< Comparator output interrupt */
#define COMP_CPU_INT_IIDX_STAT_COMPINVIFG ((uint32_t)0x00000003U) /* !< Comparator output inverted
interrupt */
#define COMP_CPU_INT_IIDX_STAT_OUTRDYIFG ((uint32_t)0x00000004U) /* !< Comparator output ready interrupt */
/* COMP_CPU_INT_IMASK Bits */
/* COMP_CPU_INT_IMASK[COMPIFG] Bits */
#define COMP_CPU_INT_IMASK_COMPIFG_OFS (1) /* !< COMPIFG Offset */
#define COMP_CPU_INT_IMASK_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Masks COMPIFG */
#define COMP_CPU_INT_IMASK_COMPIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define COMP_CPU_INT_IMASK_COMPIFG_SET ((uint32_t)0x00000002U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* COMP_CPU_INT_IMASK[COMPINVIFG] Bits */
#define COMP_CPU_INT_IMASK_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
#define COMP_CPU_INT_IMASK_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Masks COMPINVIFG */
#define COMP_CPU_INT_IMASK_COMPINVIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define COMP_CPU_INT_IMASK_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* COMP_CPU_INT_IMASK[OUTRDYIFG] Bits */
#define COMP_CPU_INT_IMASK_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
#define COMP_CPU_INT_IMASK_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Masks OUTRDYIFG */
#define COMP_CPU_INT_IMASK_OUTRDYIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define COMP_CPU_INT_IMASK_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* COMP_CPU_INT_RIS Bits */
/* COMP_CPU_INT_RIS[COMPIFG] Bits */
#define COMP_CPU_INT_RIS_COMPIFG_OFS (1) /* !< COMPIFG Offset */
#define COMP_CPU_INT_RIS_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Raw interrupt status for comparator
output interrupt flag. The IES bit
defines the transition of the
comparator output setting this bit. */
#define COMP_CPU_INT_RIS_COMPIFG_CLR ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define COMP_CPU_INT_RIS_COMPIFG_SET ((uint32_t)0x00000002U) /* !< Interrupt pending */
/* COMP_CPU_INT_RIS[COMPINVIFG] Bits */
#define COMP_CPU_INT_RIS_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
#define COMP_CPU_INT_RIS_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Raw interrupt status for comparator
output inverted interrupt flag. The
IES bit defines the transition of the
comparator output setting this bit. */
#define COMP_CPU_INT_RIS_COMPINVIFG_CLR ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define COMP_CPU_INT_RIS_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< Interrupt pending */
/* COMP_CPU_INT_RIS[OUTRDYIFG] Bits */
#define COMP_CPU_INT_RIS_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
#define COMP_CPU_INT_RIS_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Raw interrupt status for comparator
output ready interrupt flag. This bit
is set when the comparator output is
valid. */
#define COMP_CPU_INT_RIS_OUTRDYIFG_CLR ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define COMP_CPU_INT_RIS_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< Interrupt pending */
/* COMP_CPU_INT_MIS Bits */
/* COMP_CPU_INT_MIS[COMPIFG] Bits */
#define COMP_CPU_INT_MIS_COMPIFG_OFS (1) /* !< COMPIFG Offset */
#define COMP_CPU_INT_MIS_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt status for COMPIFG */
#define COMP_CPU_INT_MIS_COMPIFG_CLR ((uint32_t)0x00000000U) /* !< COMPIFG does not request an
interrupt service routine */
#define COMP_CPU_INT_MIS_COMPIFG_SET ((uint32_t)0x00000002U) /* !< COMPIFG requests an interrupt
service routine */
/* COMP_CPU_INT_MIS[COMPINVIFG] Bits */
#define COMP_CPU_INT_MIS_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
#define COMP_CPU_INT_MIS_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Masked interrupt status for
COMPINVIFG */
#define COMP_CPU_INT_MIS_COMPINVIFG_CLR ((uint32_t)0x00000000U) /* !< COMPINVIFG does not request an
interrupt service routine */
#define COMP_CPU_INT_MIS_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< COMPINVIFG requests an interrupt
service routine */
/* COMP_CPU_INT_MIS[OUTRDYIFG] Bits */
#define COMP_CPU_INT_MIS_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
#define COMP_CPU_INT_MIS_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Masked interrupt status for
OUTRDYIFG */
#define COMP_CPU_INT_MIS_OUTRDYIFG_CLR ((uint32_t)0x00000000U) /* !< OUTRDYIFG does not request an
interrupt service routine */
#define COMP_CPU_INT_MIS_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< OUTRDYIFG requests an interrupt
service routine */
/* COMP_CPU_INT_ISET Bits */
/* COMP_CPU_INT_ISET[COMPIFG] Bits */
#define COMP_CPU_INT_ISET_COMPIFG_OFS (1) /* !< COMPIFG Offset */
#define COMP_CPU_INT_ISET_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Sets COMPIFG in RIS register */
#define COMP_CPU_INT_ISET_COMPIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define COMP_CPU_INT_ISET_COMPIFG_SET ((uint32_t)0x00000002U) /* !< RIS bit corresponding to COMPIFG is
set */
/* COMP_CPU_INT_ISET[COMPINVIFG] Bits */
#define COMP_CPU_INT_ISET_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
#define COMP_CPU_INT_ISET_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Sets COMPINVIFG in RIS register */
#define COMP_CPU_INT_ISET_COMPINVIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define COMP_CPU_INT_ISET_COMPINVIFG_SET ((uint32_t)0x00000004U) /* !< RIS bit corresponding to COMPINVIFG
is set */
/* COMP_CPU_INT_ISET[OUTRDYIFG] Bits */
#define COMP_CPU_INT_ISET_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
#define COMP_CPU_INT_ISET_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Sets OUTRDYIFG in RIS register */
#define COMP_CPU_INT_ISET_OUTRDYIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define COMP_CPU_INT_ISET_OUTRDYIFG_SET ((uint32_t)0x00000008U) /* !< RIS bit corresponding to OUTRDYIFG
is set */
/* COMP_CPU_INT_ICLR Bits */
/* COMP_CPU_INT_ICLR[COMPIFG] Bits */
#define COMP_CPU_INT_ICLR_COMPIFG_OFS (1) /* !< COMPIFG Offset */
#define COMP_CPU_INT_ICLR_COMPIFG_MASK ((uint32_t)0x00000002U) /* !< Clears COMPIFG in RIS register */
#define COMP_CPU_INT_ICLR_COMPIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define COMP_CPU_INT_ICLR_COMPIFG_CLR ((uint32_t)0x00000002U) /* !< RIS bit corresponding to COMPIFG is
cleared */
/* COMP_CPU_INT_ICLR[COMPINVIFG] Bits */
#define COMP_CPU_INT_ICLR_COMPINVIFG_OFS (2) /* !< COMPINVIFG Offset */
#define COMP_CPU_INT_ICLR_COMPINVIFG_MASK ((uint32_t)0x00000004U) /* !< Clears COMPINVIFG in RIS register */
#define COMP_CPU_INT_ICLR_COMPINVIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define COMP_CPU_INT_ICLR_COMPINVIFG_CLR ((uint32_t)0x00000004U) /* !< RIS bit corresponding to COMPINVIFG
is cleared */
/* COMP_CPU_INT_ICLR[OUTRDYIFG] Bits */
#define COMP_CPU_INT_ICLR_OUTRDYIFG_OFS (3) /* !< OUTRDYIFG Offset */
#define COMP_CPU_INT_ICLR_OUTRDYIFG_MASK ((uint32_t)0x00000008U) /* !< Clears OUTRDYIFG in RIS register */
#define COMP_CPU_INT_ICLR_OUTRDYIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define COMP_CPU_INT_ICLR_OUTRDYIFG_CLR ((uint32_t)0x00000008U) /* !< RIS bit corresponding to OUTRDYIFG
is cleared */
/* COMP_PWREN Bits */
/* COMP_PWREN[ENABLE] Bits */
#define COMP_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */
#define COMP_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */
#define COMP_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */
#define COMP_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */
/* COMP_PWREN[KEY] Bits */
#define COMP_PWREN_KEY_OFS (24) /* !< KEY Offset */
#define COMP_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */
#define COMP_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this
register */
/* COMP_RSTCTL Bits */
/* COMP_RSTCTL[RESETSTKYCLR] Bits */
#define COMP_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */
#define COMP_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT
register */
#define COMP_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define COMP_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */
/* COMP_RSTCTL[RESETASSERT] Bits */
#define COMP_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */
#define COMP_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */
#define COMP_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define COMP_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */
/* COMP_RSTCTL[KEY] Bits */
#define COMP_RSTCTL_KEY_OFS (24) /* !< KEY Offset */
#define COMP_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */
#define COMP_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this
register */
/* COMP_CLKCFG Bits */
/* COMP_CLKCFG[KEY] Bits */
#define COMP_CLKCFG_KEY_OFS (24) /* !< KEY Offset */
#define COMP_CLKCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to Allow State Change -- 0xA9 */
#define COMP_CLKCFG_KEY_UNLOCK ((uint32_t)0xA9000000U) /* !< Key value to be used in writing to
this register for the write to take
effect. */
/* COMP_CLKCFG[BLOCKASYNC] Bits */
#define COMP_CLKCFG_BLOCKASYNC_OFS (8) /* !< BLOCKASYNC Offset */
#define COMP_CLKCFG_BLOCKASYNC_MASK ((uint32_t)0x00000100U) /* !< Async Clock Request is blocked from
starting SYSOSC or forcing bus clock
to 32MHz */
#define COMP_CLKCFG_BLOCKASYNC_DISABLE ((uint32_t)0x00000000U) /* !< disable COMP to request SYSOSC */
#define COMP_CLKCFG_BLOCKASYNC_ENABLE ((uint32_t)0x00000100U) /* !< enable COMP to request SYSOSC */
/* COMP_GPRCM_STAT Bits */
/* COMP_GPRCM_STAT[RESETSTKY] Bits */
#define COMP_GPRCM_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */
#define COMP_GPRCM_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the
peripheral was reset, since this bit
was cleared by RESETSTKYCLR in the
RSTCTL register */
#define COMP_GPRCM_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset
since this bit was last cleared by
RESETSTKYCLR in the RSTCTL register */
#define COMP_GPRCM_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the
last bit clear */
/* COMP_FSUB_0 Bits */
/* COMP_FSUB_0[CHANID] Bits */
#define COMP_FSUB_0_CHANID_OFS (0) /* !< CHANID Offset */
#define COMP_FSUB_0_CHANID_MASK ((uint32_t)0x00007FFFU) /* !< 0 = disconnected. 1-15 = connected
to channelID = CHANID. */
#define COMP_FSUB_0_CHANID_MNIMUM ((uint32_t)0x00000000U) /* !< 0 is an allowed value, signifying
that the event is unconnected */
#define COMP_FSUB_0_CHANID_UNCONNECTED ((uint32_t)0x00000000U) /* !< A value of 0 specifies that the
event is not connected */
#define COMP_FSUB_0_CHANID_MAXIMUM ((uint32_t)0x0000000FU) /* !< Consult your device datasheet as
the actual allowed maximum may be
less than 15. */
/* COMP_FSUB_1 Bits */
/* COMP_FSUB_1[CHANID] Bits */
#define COMP_FSUB_1_CHANID_OFS (0) /* !< CHANID Offset */
#define COMP_FSUB_1_CHANID_MASK ((uint32_t)0x00007FFFU) /* !< 0 = disconnected. 1-15 = connected
to channelID = CHANID. */
#define COMP_FSUB_1_CHANID_MNIMUM ((uint32_t)0x00000000U) /* !< 0 is an allowed value, signifying
that the event is unconnected */
#define COMP_FSUB_1_CHANID_UNCONNECTED ((uint32_t)0x00000000U) /* !< A value of 0 specifies that the
event is not connected */
#define COMP_FSUB_1_CHANID_MAXIMUM ((uint32_t)0x0000000FU) /* !< Consult your device datasheet as
the actual allowed maximum may be
less than 15. */
/* COMP_FPUB_1 Bits */
/* COMP_FPUB_1[CHANID] Bits */
#define COMP_FPUB_1_CHANID_OFS (0) /* !< CHANID Offset */
#define COMP_FPUB_1_CHANID_MASK ((uint32_t)0x00007FFFU) /* !< 0 = disconnected. 1-15 = connected
to channelID = CHANID. */
#define COMP_FPUB_1_CHANID_MNIMUM ((uint32_t)0x00000000U) /* !< 0 is an allowed value, signifying
that the event is unconnected */
#define COMP_FPUB_1_CHANID_UNCONNECTED ((uint32_t)0x00000000U) /* !< A value of 0 specifies that the
event is not connected */
#define COMP_FPUB_1_CHANID_MAXIMUM ((uint32_t)0x0000000FU) /* !< Consult your device datasheet as
the actual allowed maximum may be
less than 15. */
/* COMP_EVT_MODE Bits */
/* COMP_EVT_MODE[INT0_CFG] Bits */
#define COMP_EVT_MODE_INT0_CFG_OFS (0) /* !< INT0_CFG Offset */
#define COMP_EVT_MODE_INT0_CFG_MASK ((uint32_t)0x00000003U) /* !< Event line mode select for event
corresponding to CPU_INT */
#define COMP_EVT_MODE_INT0_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
disabled. */
#define COMP_EVT_MODE_INT0_CFG_SOFTWARE ((uint32_t)0x00000001U) /* !< Event handled by software. Software
must clear the associated RIS flag. */
#define COMP_EVT_MODE_INT0_CFG_HARDWARE ((uint32_t)0x00000002U) /* !< Event handled by hardware. The
hardware (another module) clears
automatically the associated RIS
flag. */
/* COMP_EVT_MODE[EVT1_CFG] Bits */
#define COMP_EVT_MODE_EVT1_CFG_OFS (2) /* !< EVT1_CFG Offset */
#define COMP_EVT_MODE_EVT1_CFG_MASK ((uint32_t)0x0000000CU) /* !< Event line mode select for event
corresponding to GEN_EVENT */
#define COMP_EVT_MODE_EVT1_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
disabled. */
#define COMP_EVT_MODE_EVT1_CFG_SOFTWARE ((uint32_t)0x00000004U) /* !< Event handled by software. Software
must clear the associated RIS flag. */
#define COMP_EVT_MODE_EVT1_CFG_HARDWARE ((uint32_t)0x00000008U) /* !< Event handled by hardware. The
hardware (another module) clears
automatically the associated RIS
flag. */
/* COMP_DESC Bits */
/* COMP_DESC[MINREV] Bits */
#define COMP_DESC_MINREV_OFS (0) /* !< MINREV Offset */
#define COMP_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */
/* COMP_DESC[MAJREV] Bits */
#define COMP_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */
#define COMP_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */
/* COMP_DESC[FEATUREVER] Bits */
#define COMP_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */
#define COMP_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module
*instance* */
/* COMP_DESC[MODULEID] Bits */
#define COMP_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */
#define COMP_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module identification contains a
unique peripheral identification
number. The assignments are
maintained in a central database for
all of the platform modules to ensure
uniqueness. */
/* COMP_CTL0 Bits */
/* COMP_CTL0[IPSEL] Bits */
#define COMP_CTL0_IPSEL_OFS (0) /* !< IPSEL Offset */
#define COMP_CTL0_IPSEL_MASK ((uint32_t)0x00000007U) /* !< Channel input selected for the
positive terminal of the comparator
if IPEN is set to 1. */
#define COMP_CTL0_IPSEL_CH_0 ((uint32_t)0x00000000U) /* !< Channel 0 selected */
#define COMP_CTL0_IPSEL_CH_1 ((uint32_t)0x00000001U) /* !< Channel 1 selected */
#define COMP_CTL0_IPSEL_CH_2 ((uint32_t)0x00000002U) /* !< Channel 2 selected */
#define COMP_CTL0_IPSEL_CH_3 ((uint32_t)0x00000003U) /* !< Channel 3 selected */
#define COMP_CTL0_IPSEL_CH_4 ((uint32_t)0x00000004U) /* !< Channel 4 selected */
#define COMP_CTL0_IPSEL_CH_5 ((uint32_t)0x00000005U) /* !< Channel 5 selected */
#define COMP_CTL0_IPSEL_CH_6 ((uint32_t)0x00000006U) /* !< Channel 6 selected */
#define COMP_CTL0_IPSEL_CH_7 ((uint32_t)0x00000007U) /* !< Channel 7 selected */
/* COMP_CTL0[IPEN] Bits */
#define COMP_CTL0_IPEN_OFS (15) /* !< IPEN Offset */
#define COMP_CTL0_IPEN_MASK ((uint32_t)0x00008000U) /* !< Channel input enable for the
positive terminal of the comparator. */
#define COMP_CTL0_IPEN_DISABLE ((uint32_t)0x00000000U) /* !< Selected analog input channel for
positive terminal is disabled */
#define COMP_CTL0_IPEN_ENABLE ((uint32_t)0x00008000U) /* !< Selected analog input channel for
positive terminal is enabled */
/* COMP_CTL0[IMEN] Bits */
#define COMP_CTL0_IMEN_OFS (31) /* !< IMEN Offset */
#define COMP_CTL0_IMEN_MASK ((uint32_t)0x80000000U) /* !< Channel input enable for the
negative terminal of the comparator. */
#define COMP_CTL0_IMEN_DISABLE ((uint32_t)0x00000000U) /* !< Selected analog input channel for
negative terminal is disabled */
#define COMP_CTL0_IMEN_ENABLE ((uint32_t)0x80000000U) /* !< Selected analog input channel for
negative terminal is enabled */
/* COMP_CTL0[IMSEL] Bits */
#define COMP_CTL0_IMSEL_OFS (16) /* !< IMSEL Offset */
#define COMP_CTL0_IMSEL_MASK ((uint32_t)0x00070000U) /* !< Channel input selected for the
negative terminal of the comparator
if IMEN is set to 1. */
#define COMP_CTL0_IMSEL_CH_0 ((uint32_t)0x00000000U) /* !< Channel 0 selected */
#define COMP_CTL0_IMSEL_CH_1 ((uint32_t)0x00010000U) /* !< Channel 1 selected */
#define COMP_CTL0_IMSEL_CH_2 ((uint32_t)0x00020000U) /* !< Channel 2 selected */
#define COMP_CTL0_IMSEL_CH_3 ((uint32_t)0x00030000U) /* !< Channel 3 selected */
#define COMP_CTL0_IMSEL_CH_4 ((uint32_t)0x00040000U) /* !< Channel 4 selected */
#define COMP_CTL0_IMSEL_CH_5 ((uint32_t)0x00050000U) /* !< Channel 5 selected */
#define COMP_CTL0_IMSEL_CH_6 ((uint32_t)0x00060000U) /* !< Channel 6 selected */
#define COMP_CTL0_IMSEL_CH_7 ((uint32_t)0x00070000U) /* !< Channel 7 selected */
/* COMP_CTL1 Bits */
/* COMP_CTL1[ENABLE] Bits */
#define COMP_CTL1_ENABLE_OFS (0) /* !< ENABLE Offset */
#define COMP_CTL1_ENABLE_MASK ((uint32_t)0x00000001U) /* !< This bit turns on the comparator.
When the comparator is turned off it
consumes no power. */
#define COMP_CTL1_ENABLE_OFF ((uint32_t)0x00000000U) /* !< Comparator is off */
#define COMP_CTL1_ENABLE_ON ((uint32_t)0x00000001U) /* !< Comparator is on */
/* COMP_CTL1[MODE] Bits */
#define COMP_CTL1_MODE_OFS (1) /* !< MODE Offset */
#define COMP_CTL1_MODE_MASK ((uint32_t)0x00000002U) /* !< This bit selects the comparator
operating mode. */
#define COMP_CTL1_MODE_FAST ((uint32_t)0x00000000U) /* !< Comparator is in fast mode */
#define COMP_CTL1_MODE_ULP ((uint32_t)0x00000002U) /* !< Comparator is in ultra-low power
mode */
/* COMP_CTL1[EXCH] Bits */
#define COMP_CTL1_EXCH_OFS (2) /* !< EXCH Offset */
#define COMP_CTL1_EXCH_MASK ((uint32_t)0x00000004U) /* !< This bit exchanges the comparator
inputs and inverts the comparator
output. */
#define COMP_CTL1_EXCH_NO_EXC ((uint32_t)0x00000000U) /* !< Comparator inputs not exchanged and
output not inverted */
#define COMP_CTL1_EXCH_EXC ((uint32_t)0x00000004U) /* !< Comparator inputs exchanged and
output inverted */
/* COMP_CTL1[SHORT] Bits */
#define COMP_CTL1_SHORT_OFS (3) /* !< SHORT Offset */
#define COMP_CTL1_SHORT_MASK ((uint32_t)0x00000008U) /* !< This bit shorts the positive and
negative input terminals of the
comparator. */
#define COMP_CTL1_SHORT_NO_SHT ((uint32_t)0x00000000U) /* !< Comparator positive and negative
input terminals are not shorted */
#define COMP_CTL1_SHORT_SHT ((uint32_t)0x00000008U) /* !< Comparator positive and negative
input terminals are shorted */
/* COMP_CTL1[IES] Bits */
#define COMP_CTL1_IES_OFS (4) /* !< IES Offset */
#define COMP_CTL1_IES_MASK ((uint32_t)0x00000010U) /* !< This bit selected the interrupt
edge for COMPIFG and COMPINVIFG. */
#define COMP_CTL1_IES_RISING ((uint32_t)0x00000000U) /* !< Rising edge sets COMPIFG and
falling edge sets COMPINVIFG */
#define COMP_CTL1_IES_FALLING ((uint32_t)0x00000010U) /* !< Falling edge sets COMPIFG and
rising edge sets COMPINVIFG */
/* COMP_CTL1[HYST] Bits */
#define COMP_CTL1_HYST_OFS (5) /* !< HYST Offset */
#define COMP_CTL1_HYST_MASK ((uint32_t)0x00000060U) /* !< These bits select the hysteresis
setting of the comparator. */
#define COMP_CTL1_HYST_NO_HYS ((uint32_t)0x00000000U) /* !< No hysteresis */
#define COMP_CTL1_HYST_LOW_HYS ((uint32_t)0x00000020U) /* !< Low hysteresis, typical 10mV */
#define COMP_CTL1_HYST_MED_HYS ((uint32_t)0x00000040U) /* !< Medium hysteresis, typical 20mV */
#define COMP_CTL1_HYST_HIGH_HYS ((uint32_t)0x00000060U) /* !< High hysteresis, typical 30mV */
/* COMP_CTL1[OUTPOL] Bits */
#define COMP_CTL1_OUTPOL_OFS (7) /* !< OUTPOL Offset */
#define COMP_CTL1_OUTPOL_MASK ((uint32_t)0x00000080U) /* !< This bit selects the comparator
output polarity. */
#define COMP_CTL1_OUTPOL_NON_INV ((uint32_t)0x00000000U) /* !< Comparator output is non-inverted */
#define COMP_CTL1_OUTPOL_INV ((uint32_t)0x00000080U) /* !< Comparator output is inverted */
/* COMP_CTL1[FLTEN] Bits */
#define COMP_CTL1_FLTEN_OFS (8) /* !< FLTEN Offset */
#define COMP_CTL1_FLTEN_MASK ((uint32_t)0x00000100U) /* !< This bit enables the analog filter
at comparator output. */
#define COMP_CTL1_FLTEN_DISABLE ((uint32_t)0x00000000U) /* !< Comparator output filter is
disabled */
#define COMP_CTL1_FLTEN_ENABLE ((uint32_t)0x00000100U) /* !< Comparator output filter is enabled */
/* COMP_CTL1[FLTDLY] Bits */
#define COMP_CTL1_FLTDLY_OFS (9) /* !< FLTDLY Offset */
#define COMP_CTL1_FLTDLY_MASK ((uint32_t)0x00000600U) /* !< These bits select the comparator
output filter delay. See the
device-specific data sheet for
specific values on comparator
propagation delay for different
filter delay settings. */
#define COMP_CTL1_FLTDLY_DLY_0 ((uint32_t)0x00000000U) /* !< Typical filter delay of 70 ns */
#define COMP_CTL1_FLTDLY_DLY_1 ((uint32_t)0x00000200U) /* !< Typical filter delay of 500 ns */
#define COMP_CTL1_FLTDLY_DLY_2 ((uint32_t)0x00000400U) /* !< Typical filter delay of 1200 ns */
#define COMP_CTL1_FLTDLY_DLY_3 ((uint32_t)0x00000600U) /* !< Typical filter delay of 2700 ns */
/* COMP_CTL1[WINCOMPEN] Bits */
#define COMP_CTL1_WINCOMPEN_OFS (12) /* !< WINCOMPEN Offset */
#define COMP_CTL1_WINCOMPEN_MASK ((uint32_t)0x00001000U) /* !< This bit enables window comparator
operation of comparator. */
#define COMP_CTL1_WINCOMPEN_OFF ((uint32_t)0x00000000U) /* !< window comparator is disable */
#define COMP_CTL1_WINCOMPEN_ON ((uint32_t)0x00001000U) /* !< window comparator is enable */
/* COMP_CTL2 Bits */
/* COMP_CTL2[REFMODE] Bits */
#define COMP_CTL2_REFMODE_OFS (0) /* !< REFMODE Offset */
#define COMP_CTL2_REFMODE_MASK ((uint32_t)0x00000001U) /* !< This bit requests ULP_REF bandgap
operation in fast mode(static) or low
power mode (sampled). The local
reference buffer and 8-bit DAC inside
comparator module are also configured
accordingly. Fast mode operation
offers higher accuracy but consumes
higher current. Low power operation
consumes lower current but with
relaxed reference voltage accuracy.
Comparator requests for reference
voltage from ULP_REF only when REFLVL
> 0. */
#define COMP_CTL2_REFMODE_STATIC ((uint32_t)0x00000000U) /* !< ULP_REF bandgap, local reference
buffer and 8-bit DAC inside
comparator operate in static mode. */
#define COMP_CTL2_REFMODE_SAMPLED ((uint32_t)0x00000001U) /* !< ULP_REF bandgap, local reference
buffer and 8-bit DAC inside
comparator operate in sampled mode. */
/* COMP_CTL2[REFSRC] Bits */
#define COMP_CTL2_REFSRC_OFS (3) /* !< REFSRC Offset */
#define COMP_CTL2_REFSRC_MASK ((uint32_t)0x00000038U) /* !< These bits select the reference
source for the comparator. */
#define COMP_CTL2_REFSRC_OFF ((uint32_t)0x00000000U) /* !< Reference voltage generator is
disabled (local reference buffer as
well as DAC). */
#define COMP_CTL2_REFSRC_VDDA_DAC ((uint32_t)0x00000008U) /* !< VDDA selected as the reference
source to DAC and DAC output applied
as reference to comparator. */
#define COMP_CTL2_REFSRC_VREF_DAC ((uint32_t)0x00000010U) /* !< VREF selected as reference to DAC
and DAC output applied as reference
to comparator. */
#define COMP_CTL2_REFSRC_VREF ((uint32_t)0x00000018U) /* !< In devices where internal VREF is
buffered and hookedup to extrernal
VREF pin, VREF applied as reference
to comparator. DAC is switched off.
Note: In LEGO_A3, DAC is turned off
in this selection, in other deviced
DAC is kept on. */
#define COMP_CTL2_REFSRC_VDDA ((uint32_t)0x00000028U) /* !< VDDA is used as comparator
reference. Note: In LEGO_A3, DAC is
turned off in this selection, in
other deviced DAC is kept on. */
#define COMP_CTL2_REFSRC_INTVREF_DAC ((uint32_t)0x00000030U) /* !< Internal reference selected as the
reference source to DAC and DAC
output applied as reference to
comparator. */
#define COMP_CTL2_REFSRC_INTVREF ((uint32_t)0x00000038U) /* !< Internal VREF is used as the source
of comparator. Not all devices will
have this option. */
/* COMP_CTL2[REFSEL] Bits */
#define COMP_CTL2_REFSEL_OFS (7) /* !< REFSEL Offset */
#define COMP_CTL2_REFSEL_MASK ((uint32_t)0x00000080U) /* !< This bit selects if the selected
reference voltage is applied to
positive or negative terminal of the
comparator. */
#define COMP_CTL2_REFSEL_POSITIVE ((uint32_t)0x00000000U) /* !< If EXCH bit is 0, the selected
reference is applied to positive
terminal. If EXCH bit is 1, the
selected reference is applied to
negative terminal. */
#define COMP_CTL2_REFSEL_NEGATIVE ((uint32_t)0x00000080U) /* !< If EXCH bit is 0, the selected
reference is applied to negative
terminal. If EXCH bit is 1, the
selected reference is applied to
positive terminal. */
/* COMP_CTL2[DACCTL] Bits */
#define COMP_CTL2_DACCTL_OFS (16) /* !< DACCTL Offset */
#define COMP_CTL2_DACCTL_MASK ((uint32_t)0x00010000U) /* !< This bit determines if the
comparator output or DACSW bit
controls the selection between
DACCODE0 and DACCODE1. */
#define COMP_CTL2_DACCTL_COMPOUT_SEL ((uint32_t)0x00000000U) /* !< Comparator output controls
selection between DACCODE0 and
DACCODE1 */
#define COMP_CTL2_DACCTL_DACSW_SEL ((uint32_t)0x00010000U) /* !< DACSW bit controls selection
between DACCODE0 and DACCODE1 */
/* COMP_CTL2[DACSW] Bits */
#define COMP_CTL2_DACSW_OFS (17) /* !< DACSW Offset */
#define COMP_CTL2_DACSW_MASK ((uint32_t)0x00020000U) /* !< This bit selects between DACCODE0
and DACCODE1 to 8-bit DAC when DACCTL
bit is 1. */
#define COMP_CTL2_DACSW_DACCODE0_SEL ((uint32_t)0x00000000U) /* !< DACCODE0 selected for 8-bit DAC */
#define COMP_CTL2_DACSW_DACCODE1_SEL ((uint32_t)0x00020000U) /* !< DACCODE1 selected for 8-bit DAC */
/* COMP_CTL2[BLANKSRC] Bits */
#define COMP_CTL2_BLANKSRC_OFS (8) /* !< BLANKSRC Offset */
#define COMP_CTL2_BLANKSRC_MASK ((uint32_t)0x00000700U) /* !< These bits select the blanking
source for the comparator. */
#define COMP_CTL2_BLANKSRC_DISABLE ((uint32_t)0x00000000U) /* !< Blanking source disabled */
#define COMP_CTL2_BLANKSRC_BLANKSRC1 ((uint32_t)0x00000100U) /* !< Select Blanking Source 1 */
#define COMP_CTL2_BLANKSRC_BLANKSRC2 ((uint32_t)0x00000200U) /* !< Select Blanking Source 2 */
#define COMP_CTL2_BLANKSRC_BLANKSRC3 ((uint32_t)0x00000300U) /* !< Select Blanking Source 3 */
#define COMP_CTL2_BLANKSRC_BLANKSRC4 ((uint32_t)0x00000400U) /* !< Select Blanking Source 4 */
#define COMP_CTL2_BLANKSRC_BLANKSRC5 ((uint32_t)0x00000500U) /* !< Select Blanking Source 5 */
#define COMP_CTL2_BLANKSRC_BLANKSRC6 ((uint32_t)0x00000600U) /* !< Select Blanking Source 6 */
/* COMP_CTL2[SAMPMODE] Bits */
#define COMP_CTL2_SAMPMODE_OFS (24) /* !< SAMPMODE Offset */
#define COMP_CTL2_SAMPMODE_MASK ((uint32_t)0x01000000U) /* !< Enable sampled mode of comparator. */
#define COMP_CTL2_SAMPMODE_DISABLE ((uint32_t)0x00000000U) /* !< Sampled mode disabled */
#define COMP_CTL2_SAMPMODE_ENABLE ((uint32_t)0x01000000U) /* !< Sampled mode enabled */
/* COMP_CTL3 Bits */
/* COMP_CTL3[DACCODE0] Bits */
#define COMP_CTL3_DACCODE0_OFS (0) /* !< DACCODE0 Offset */
#define COMP_CTL3_DACCODE0_MASK ((uint32_t)0x000000FFU) /* !< This is the first 8-bit DAC code.
When the DAC code is 0x0 the DAC
output will be 0 V. When the DAC code
is 0xFF the DAC output will be
selected reference voltage x 255/256. */
#define COMP_CTL3_DACCODE0_MNIMUM ((uint32_t)0x00000000U) /* !< Minimum DAC code value */
#define COMP_CTL3_DACCODE0_MAXIMUM ((uint32_t)0x000000FFU) /* !< Minimum DAC code value */
/* COMP_CTL3[DACCODE1] Bits */
#define COMP_CTL3_DACCODE1_OFS (16) /* !< DACCODE1 Offset */
#define COMP_CTL3_DACCODE1_MASK ((uint32_t)0x00FF0000U) /* !< This is the second 8-bit DAC code.
When the DAC code is 0x0 the DAC
output will be 0 V. When the DAC code
is 0xFF the DAC output will be
selected reference voltage x 255/256. */
#define COMP_CTL3_DACCODE1_MNIMUM ((uint32_t)0x00000000U) /* !< Minimum DAC code value */
#define COMP_CTL3_DACCODE1_MAXIMUM ((uint32_t)0x00FF0000U) /* !< Minimum DAC code value */
/* COMP_STAT Bits */
/* COMP_STAT[OUT] Bits */
#define COMP_STAT_OUT_OFS (0) /* !< OUT Offset */
#define COMP_STAT_OUT_MASK ((uint32_t)0x00000001U) /* !< This bit reflects the value of the
comparator output. Writing to this
bit has no effect on the comparator
output. */
#define COMP_STAT_OUT_LOW ((uint32_t)0x00000000U) /* !< Comparator output is low */
#define COMP_STAT_OUT_HIGH ((uint32_t)0x00000001U) /* !< Comparator output is high */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_hw_comp__include */
libraries/sdk/ti/devices/msp/peripherals/hw_crc.h
+300
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@@ -0,0 +1,300 @@
/*****************************************************************************
Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_hw_crc__include
#define ti_devices_msp_peripherals_hw_crc__include
/* This preliminary header file does not have a version number */
/* MMR repo: https://bitbucket.itg.ti.com/projects/cmcu_msp65ip/repos/f65mspcrc */
/* MMR revision: 3dcce9f1dec4d9cd7395689f4e4c8a92d2dd7f5b */
/* Generator revision: 77992b62fb4e9926f5a9143aae1e89fec6a84738
(MInT: ec7ec7482a60c6871be32db8b378ec27aa4771f6) */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* CRC Registers
******************************************************************************/
#define CRC_GPRCM_OFS ((uint32_t)0x00000800U)
/** @addtogroup CRC_GPRCM
@{
*/
typedef struct {
__IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */
__O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */
uint32_t RESERVED0[3];
__I uint32_t STAT; /* !< (@ 0x00000814) Status Register */
} CRC_GPRCM_Regs;
/*@}*/ /* end of group CRC_GPRCM */
/** @addtogroup CRC
@{
*/
typedef struct {
uint32_t RESERVED0[512];
CRC_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */
uint32_t RESERVED1[507];
__I uint32_t CLKSEL; /* !< (@ 0x00001004) Clock Select */
uint32_t RESERVED2[61];
__I uint32_t DESC; /* !< (@ 0x000010FC) Module Description */
__IO uint32_t CRCCTRL; /* !< (@ 0x00001100) CRC Control Register */
__O uint32_t CRCSEED; /* !< (@ 0x00001104) CRC Seed Register */
__O uint32_t CRCIN; /* !< (@ 0x00001108) CRC Input Data Register */
__I uint32_t CRCOUT; /* !< (@ 0x0000110C) CRC Output Result Register */
uint32_t RESERVED3[444];
__O uint32_t CRCIN_IDX[512]; /* !< (@ 0x00001800) CRC Input Data Array Register */
} CRC_Regs;
/*@}*/ /* end of group CRC */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* CRC Register Control Bits
******************************************************************************/
/* CRC_PWREN Bits */
/* CRC_PWREN[ENABLE] Bits */
#define CRC_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */
#define CRC_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */
#define CRC_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */
#define CRC_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */
/* CRC_PWREN[KEY] Bits */
#define CRC_PWREN_KEY_OFS (24) /* !< KEY Offset */
#define CRC_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */
#define CRC_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this
register */
/* CRC_RSTCTL Bits */
/* CRC_RSTCTL[RESETSTKYCLR] Bits */
#define CRC_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */
#define CRC_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT
register */
#define CRC_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define CRC_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */
/* CRC_RSTCTL[RESETASSERT] Bits */
#define CRC_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */
#define CRC_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */
#define CRC_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define CRC_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */
/* CRC_RSTCTL[KEY] Bits */
#define CRC_RSTCTL_KEY_OFS (24) /* !< KEY Offset */
#define CRC_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */
#define CRC_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this
register */
/* CRC_STAT Bits */
/* CRC_STAT[RESETSTKY] Bits */
#define CRC_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */
#define CRC_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the
peripheral was reset, since this bit
was cleared by RESETSTKYCLR in the
RSTCTL register */
#define CRC_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset
since this bit was last cleared by
RESETSTKYCLR in the RSTCTL register */
#define CRC_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the
last bit clear */
/* CRC_CLKSEL Bits */
/* CRC_CLKSEL[MCLK_SEL] Bits */
#define CRC_CLKSEL_MCLK_SEL_OFS (0) /* !< MCLK_SEL Offset */
#define CRC_CLKSEL_MCLK_SEL_MASK ((uint32_t)0x00000001U) /* !< Selects main clock (MCLK) if
enabled */
#define CRC_CLKSEL_MCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a
source */
#define CRC_CLKSEL_MCLK_SEL_ENABLE ((uint32_t)0x00000001U) /* !< Select this clock as a source */
/* CRC_DESC Bits */
/* CRC_DESC[MINREV] Bits */
#define CRC_DESC_MINREV_OFS (0) /* !< MINREV Offset */
#define CRC_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */
#define CRC_DESC_MINREV_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define CRC_DESC_MINREV_MAXIMUM ((uint32_t)0x0000000FU) /* !< Highest possible value */
/* CRC_DESC[MAJREV] Bits */
#define CRC_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */
#define CRC_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */
#define CRC_DESC_MAJREV_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define CRC_DESC_MAJREV_MAXIMUM ((uint32_t)0x000000F0U) /* !< Highest possible value */
/* CRC_DESC[INSTNUM] Bits */
#define CRC_DESC_INSTNUM_OFS (8) /* !< INSTNUM Offset */
#define CRC_DESC_INSTNUM_MASK ((uint32_t)0x00000F00U) /* !< Instance Number within the device.
This will be a parameter to the RTL
for modules that can have multiple
instances */
#define CRC_DESC_INSTNUM_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define CRC_DESC_INSTNUM_MAXIMUM ((uint32_t)0x00000F00U) /* !< Highest possible value */
/* CRC_DESC[FEATUREVER] Bits */
#define CRC_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */
#define CRC_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module
*instance* */
#define CRC_DESC_FEATUREVER_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define CRC_DESC_FEATUREVER_MAXIMUM ((uint32_t)0x0000F000U) /* !< Highest possible value */
/* CRC_DESC[MODULEID] Bits */
#define CRC_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */
#define CRC_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module identification contains a
unique peripheral identification
number. The assignments are
maintained in a central database for
all of the platform modules to ensure
uniqueness. */
#define CRC_DESC_MODULEID_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define CRC_DESC_MODULEID_MAXIMUM ((uint32_t)0xFFFF0000U) /* !< Highest possible value */
/* CRC_CRCCTRL Bits */
/* CRC_CRCCTRL[POLYSIZE] Bits */
#define CRC_CRCCTRL_POLYSIZE_OFS (0) /* !< POLYSIZE Offset */
#define CRC_CRCCTRL_POLYSIZE_MASK ((uint32_t)0x00000001U) /* !< This bit indicates which CRC
calculation is performed by the
generator. */
#define CRC_CRCCTRL_POLYSIZE_CRC32 ((uint32_t)0x00000000U) /* !< CRC-32 ISO-3309 calculation is
performed */
#define CRC_CRCCTRL_POLYSIZE_CRC16 ((uint32_t)0x00000001U) /* !< CRC-16 CCITT is performed */
/* CRC_CRCCTRL[BITREVERSE] Bits */
#define CRC_CRCCTRL_BITREVERSE_OFS (1) /* !< BITREVERSE Offset */
#define CRC_CRCCTRL_BITREVERSE_MASK ((uint32_t)0x00000002U) /* !< CRC Bit Input and output Reverse.
This bit indicates that the bit order
of each input byte used for the CRC
calculation is reversed before it is
passed to the generator, and that the
bit order of the calculated CRC is be
reversed when read from CRC_RESULT. */
#define CRC_CRCCTRL_BITREVERSE_NOT_REVERSED ((uint32_t)0x00000000U) /* !< Bit order is not reversed. */
#define CRC_CRCCTRL_BITREVERSE_REVERSED ((uint32_t)0x00000002U) /* !< Bit order is reversed. */
/* CRC_CRCCTRL[INPUT_ENDIANNESS] Bits */
#define CRC_CRCCTRL_INPUT_ENDIANNESS_OFS (2) /* !< INPUT_ENDIANNESS Offset */
#define CRC_CRCCTRL_INPUT_ENDIANNESS_MASK ((uint32_t)0x00000004U) /* !< CRC Endian. This bit indicates the
byte order within a word or half word
of input data. */
#define CRC_CRCCTRL_INPUT_ENDIANNESS_LITTLE_ENDIAN ((uint32_t)0x00000000U) /* !< LSB is lowest memory address and
first to be processed. */
#define CRC_CRCCTRL_INPUT_ENDIANNESS_BIG_ENDIAN ((uint32_t)0x00000004U) /* !< LSB is highest memory address and
last to be processed. */
/* CRC_CRCCTRL[OUTPUT_BYTESWAP] Bits */
#define CRC_CRCCTRL_OUTPUT_BYTESWAP_OFS (4) /* !< OUTPUT_BYTESWAP Offset */
#define CRC_CRCCTRL_OUTPUT_BYTESWAP_MASK ((uint32_t)0x00000010U) /* !< CRC Output Byteswap Enable. This
bit controls whether the output is
byte-swapped upon a read of the
CRCOUT register. If CRCOUT is
accessed as a half-word, and the
OUTPUT_BYTESWAP is set to to 1, then
the two bytes in the 16-bit access
are swapped and returned. B1 is
returned as B0 B0 is returned as B1
If CRCOUT is accessed as a word, and
the OUTPUT_BYTESWAP is set to 1, then
the four bytes in the 32-bit read are
swapped. B3 is returned as B0 B2 is
returned as B1 B1 is returned as B2
B0 is returned as B3 Note that if
the CRC POLYSIZE is 16-bit and a
32-bit read of CRCOUT is performed
with OUTPUT_BYTESWAP enabled, then
the output is: MSB LSB
0x0 0x0 B0 B1 If the CRC
POLYSIZE is 16-bit and a 32-bit read
of CRCOUT is performed with
OUTPUT_BYTESWAP disabled, then the
output is: MSB LSB 0x0
0x0 B1 B0 */
#define CRC_CRCCTRL_OUTPUT_BYTESWAP_DISABLE ((uint32_t)0x00000000U) /* !< Output byteswapping is disabled */
#define CRC_CRCCTRL_OUTPUT_BYTESWAP_ENABLE ((uint32_t)0x00000010U) /* !< Output byteswapping is enabled. */
/* CRC_CRCSEED Bits */
/* CRC_CRCSEED[SEED] Bits */
#define CRC_CRCSEED_SEED_OFS (0) /* !< SEED Offset */
#define CRC_CRCSEED_SEED_MASK ((uint32_t)0xFFFFFFFFU) /* !< Seed Data */
#define CRC_CRCSEED_SEED_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum value */
#define CRC_CRCSEED_SEED_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Maximum value */
/* CRC_CRCIN Bits */
/* CRC_CRCIN[DATA] Bits */
#define CRC_CRCIN_DATA_OFS (0) /* !< DATA Offset */
#define CRC_CRCIN_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Input Data */
#define CRC_CRCIN_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum value */
#define CRC_CRCIN_DATA_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Maximum value */
/* CRC_CRCOUT Bits */
/* CRC_CRCOUT[RESULT] Bits */
#define CRC_CRCOUT_RESULT_OFS (0) /* !< RESULT Offset */
#define CRC_CRCOUT_RESULT_MASK ((uint32_t)0xFFFFFFFFU) /* !< Result */
#define CRC_CRCOUT_RESULT_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum value */
#define CRC_CRCOUT_RESULT_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Maximum value */
/* CRC_CRCIN_IDX Bits */
/* CRC_CRCIN_IDX[DATA] Bits */
#define CRC_CRCIN_IDX_DATA_OFS (0) /* !< DATA Offset */
#define CRC_CRCIN_IDX_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Input Data */
#define CRC_CRCIN_IDX_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum value */
#define CRC_CRCIN_IDX_DATA_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Maximum value */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_hw_crc__include */
libraries/sdk/ti/devices/msp/peripherals/hw_crcp.h
+306
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@@ -0,0 +1,306 @@
/*****************************************************************************
Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_hw_crcp__include
#define ti_devices_msp_peripherals_hw_crcp__include
/* This preliminary header file does not have a version number */
/* MMR repo: https://bitbucket.itg.ti.com/projects/cmcu_msp65ip/repos/f65mspcrcp */
/* MMR revision: c7a923985b92a7b6b96f570800afdbf6fa370b4e */
/* Generator revision: 0afd252131372f6ff2599f3ff4321e731df2364d
(MInT: ec7ec7482a60c6871be32db8b378ec27aa4771f6) */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* CRCP Registers
******************************************************************************/
#define CRCP_GPRCM_OFS ((uint32_t)0x00000800U)
/** @addtogroup CRCP_GPRCM
@{
*/
typedef struct {
__IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */
__O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */
uint32_t RESERVED0[3];
__I uint32_t STAT; /* !< (@ 0x00000814) Status Register */
} CRCP_GPRCM_Regs;
/*@}*/ /* end of group CRCP_GPRCM */
/** @addtogroup CRCP
@{
*/
typedef struct {
uint32_t RESERVED0[512];
CRCP_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */
uint32_t RESERVED1[507];
__I uint32_t CLKSEL; /* !< (@ 0x00001004) Clock Select */
uint32_t RESERVED2[61];
__I uint32_t DESC; /* !< (@ 0x000010FC) Module Description */
__IO uint32_t CRCCTRL; /* !< (@ 0x00001100) CRC Control Register */
__O uint32_t CRCSEED; /* !< (@ 0x00001104) CRC Seed Register */
__O uint32_t CRCIN; /* !< (@ 0x00001108) CRC Input Data Register */
__I uint32_t CRCOUT; /* !< (@ 0x0000110C) CRC Output Result Register */
__IO uint32_t CRCPOLY; /* !< (@ 0x00001110) CRC Polynomial configuration register */
uint32_t RESERVED3[443];
__O uint32_t CRCIN_IDX[512]; /* !< (@ 0x00001800) CRC Input Data Array Register */
} CRCP_Regs;
/*@}*/ /* end of group CRCP */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* CRCP Register Control Bits
******************************************************************************/
/* CRCP_PWREN Bits */
/* CRCP_PWREN[ENABLE] Bits */
#define CRCP_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */
#define CRCP_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */
#define CRCP_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */
#define CRCP_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */
/* CRCP_PWREN[KEY] Bits */
#define CRCP_PWREN_KEY_OFS (24) /* !< KEY Offset */
#define CRCP_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */
#define CRCP_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this
register */
/* CRCP_RSTCTL Bits */
/* CRCP_RSTCTL[RESETSTKYCLR] Bits */
#define CRCP_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */
#define CRCP_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT
register */
#define CRCP_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define CRCP_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */
/* CRCP_RSTCTL[RESETASSERT] Bits */
#define CRCP_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */
#define CRCP_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */
#define CRCP_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define CRCP_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */
/* CRCP_RSTCTL[KEY] Bits */
#define CRCP_RSTCTL_KEY_OFS (24) /* !< KEY Offset */
#define CRCP_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */
#define CRCP_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this
register */
/* CRCP_STAT Bits */
/* CRCP_STAT[RESETSTKY] Bits */
#define CRCP_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */
#define CRCP_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the
peripheral was reset, since this bit
was cleared by RESETSTKYCLR in the
RSTCTL register */
#define CRCP_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset
since this bit was last cleared by
RESETSTKYCLR in the RSTCTL register */
#define CRCP_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the
last bit clear */
/* CRCP_CLKSEL Bits */
/* CRCP_CLKSEL[MCLK_SEL] Bits */
#define CRCP_CLKSEL_MCLK_SEL_OFS (0) /* !< MCLK_SEL Offset */
#define CRCP_CLKSEL_MCLK_SEL_MASK ((uint32_t)0x00000001U) /* !< Selects main clock (MCLK) if
enabled */
#define CRCP_CLKSEL_MCLK_SEL_DISABLE ((uint32_t)0x00000000U) /* !< Does not select this clock as a
source */
#define CRCP_CLKSEL_MCLK_SEL_ENABLE ((uint32_t)0x00000001U) /* !< Select this clock as a source */
/* CRCP_DESC Bits */
/* CRCP_DESC[MINREV] Bits */
#define CRCP_DESC_MINREV_OFS (0) /* !< MINREV Offset */
#define CRCP_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */
#define CRCP_DESC_MINREV_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define CRCP_DESC_MINREV_MAXIMUM ((uint32_t)0x0000000FU) /* !< Highest possible value */
/* CRCP_DESC[MAJREV] Bits */
#define CRCP_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */
#define CRCP_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */
#define CRCP_DESC_MAJREV_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define CRCP_DESC_MAJREV_MAXIMUM ((uint32_t)0x000000F0U) /* !< Highest possible value */
/* CRCP_DESC[INSTNUM] Bits */
#define CRCP_DESC_INSTNUM_OFS (8) /* !< INSTNUM Offset */
#define CRCP_DESC_INSTNUM_MASK ((uint32_t)0x00000F00U) /* !< Instance Number within the device.
This will be a parameter to the RTL
for modules that can have multiple
instances */
#define CRCP_DESC_INSTNUM_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define CRCP_DESC_INSTNUM_MAXIMUM ((uint32_t)0x00000F00U) /* !< Highest possible value */
/* CRCP_DESC[FEATUREVER] Bits */
#define CRCP_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */
#define CRCP_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module
*instance* */
#define CRCP_DESC_FEATUREVER_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define CRCP_DESC_FEATUREVER_MAXIMUM ((uint32_t)0x0000F000U) /* !< Highest possible value */
/* CRCP_DESC[MODULEID] Bits */
#define CRCP_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */
#define CRCP_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module identification contains a
unique peripheral identification
number. The assignments are
maintained in a central database for
all of the platform modules to ensure
uniqueness. */
#define CRCP_DESC_MODULEID_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define CRCP_DESC_MODULEID_MAXIMUM ((uint32_t)0xFFFF0000U) /* !< Highest possible value */
/* CRCP_CRCCTRL Bits */
/* CRCP_CRCCTRL[POLYSIZE] Bits */
#define CRCP_CRCCTRL_POLYSIZE_OFS (0) /* !< POLYSIZE Offset */
#define CRCP_CRCCTRL_POLYSIZE_MASK ((uint32_t)0x00000001U) /* !< This bit indicates which CRC
calculation is performed by the
generator. */
#define CRCP_CRCCTRL_POLYSIZE_CRC32 ((uint32_t)0x00000000U) /* !< CRC-32 ISO-3309 calulation is
performed */
#define CRCP_CRCCTRL_POLYSIZE_CRC16 ((uint32_t)0x00000001U) /* !< CRC-16 CCITT is performed */
/* CRCP_CRCCTRL[BITREVERSE] Bits */
#define CRCP_CRCCTRL_BITREVERSE_OFS (1) /* !< BITREVERSE Offset */
#define CRCP_CRCCTRL_BITREVERSE_MASK ((uint32_t)0x00000002U) /* !< CRC Bit Input and output Reverse.
This bit indictes that the bit order
of each input byte used for the CRC
calculation is reversed before it is
passed to the generator, and that the
bit order of the calculated CRC is be
reversed when read from CRC_RESULT. */
#define CRCP_CRCCTRL_BITREVERSE_NOT_REVERSED ((uint32_t)0x00000000U) /* !< Bit order is not reversed. */
#define CRCP_CRCCTRL_BITREVERSE_REVERSED ((uint32_t)0x00000002U) /* !< Bit order is reversed. */
/* CRCP_CRCCTRL[INPUT_ENDIANNESS] Bits */
#define CRCP_CRCCTRL_INPUT_ENDIANNESS_OFS (2) /* !< INPUT_ENDIANNESS Offset */
#define CRCP_CRCCTRL_INPUT_ENDIANNESS_MASK ((uint32_t)0x00000004U) /* !< CRC Endian. This bit indicates the
byte order within a word or half word
of input data. */
#define CRCP_CRCCTRL_INPUT_ENDIANNESS_LITTLE_ENDIAN ((uint32_t)0x00000000U) /* !< LSB is lowest memory address and
first to be processed. */
#define CRCP_CRCCTRL_INPUT_ENDIANNESS_BIG_ENDIAN ((uint32_t)0x00000004U) /* !< LSB is highest memory address and
last to be processed. */
/* CRCP_CRCCTRL[OUTPUT_BYTESWAP] Bits */
#define CRCP_CRCCTRL_OUTPUT_BYTESWAP_OFS (4) /* !< OUTPUT_BYTESWAP Offset */
#define CRCP_CRCCTRL_OUTPUT_BYTESWAP_MASK ((uint32_t)0x00000010U) /* !< CRC Output Byteswap Enable. This
bit controls whether the output is
byte-swapped upon a read of the
CRCOUT register. If CRCOUT is
accessed as a half-word, and the
OUTPUT_BYTESWAP is set to to 1, then
the two bytes in the 16-bit access
are swapped and returned. B1 is
returned as B0 B0 is returned as B1
If CRCOUT is accessed as a word, and
the OUTPUT_BYTESWAP is set to 1, then
the four bytes in the 32-bit read are
swapped. B3 is returned as B0 B2 is
returned as B1 B1 is returned as B2
B0 is returned as B3 Note that if
the CRC POLYSIZE is 16-bit and a
32-bit read of CRCOUT is performed
with OUTPUT_BYTESWAP enabled, then
the output is: MSB LSB
0x0 0x0 B0 B1 If the CRC
POLYSIZE is 16-bit and a 32-bit read
of CRCOUT is performed with
OUTPUT_BYTESWAP disabled, then the
output is: MSB LSB 0x0
0x0 B1 B0 */
#define CRCP_CRCCTRL_OUTPUT_BYTESWAP_DISABLE ((uint32_t)0x00000000U) /* !< Output byteswapping is disabled */
#define CRCP_CRCCTRL_OUTPUT_BYTESWAP_ENABLE ((uint32_t)0x00000010U) /* !< Output byteswapping is enabled. */
/* CRCP_CRCSEED Bits */
/* CRCP_CRCSEED[SEED] Bits */
#define CRCP_CRCSEED_SEED_OFS (0) /* !< SEED Offset */
#define CRCP_CRCSEED_SEED_MASK ((uint32_t)0xFFFFFFFFU) /* !< Seed Data */
#define CRCP_CRCSEED_SEED_MINIMUM ((uint32_t)0x00000000U) /* !< Mnimum value */
#define CRCP_CRCSEED_SEED_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Maximum value */
/* CRCP_CRCIN Bits */
/* CRCP_CRCIN[DATA] Bits */
#define CRCP_CRCIN_DATA_OFS (0) /* !< DATA Offset */
#define CRCP_CRCIN_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Input Data */
#define CRCP_CRCIN_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Mnimum value */
#define CRCP_CRCIN_DATA_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Maximum value */
/* CRCP_CRCOUT Bits */
/* CRCP_CRCOUT[RESULT] Bits */
#define CRCP_CRCOUT_RESULT_OFS (0) /* !< RESULT Offset */
#define CRCP_CRCOUT_RESULT_MASK ((uint32_t)0xFFFFFFFFU) /* !< Result */
#define CRCP_CRCOUT_RESULT_MINIMUM ((uint32_t)0x00000000U) /* !< Mnimum value */
#define CRCP_CRCOUT_RESULT_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Maximum value */
/* CRCP_CRCPOLY Bits */
/* CRCP_CRCPOLY[DATA] Bits */
#define CRCP_CRCPOLY_DATA_OFS (0) /* !< DATA Offset */
#define CRCP_CRCPOLY_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Polynomial definition */
/* CRCP_CRCIN_IDX Bits */
/* CRCP_CRCIN_IDX[DATA] Bits */
#define CRCP_CRCIN_IDX_DATA_OFS (0) /* !< DATA Offset */
#define CRCP_CRCIN_IDX_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Input Data */
#define CRCP_CRCIN_IDX_DATA_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum value */
#define CRCP_CRCIN_IDX_DATA_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Maximum value */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_hw_crcp__include */
libraries/sdk/ti/devices/msp/peripherals/hw_dac12.h
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libraries/sdk/ti/devices/msp/peripherals/hw_dma.h
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libraries/sdk/ti/devices/msp/peripherals/hw_flashctl.h
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libraries/sdk/ti/devices/msp/peripherals/hw_gpio.h
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libraries/sdk/ti/devices/msp/peripherals/hw_iomux.h
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/*****************************************************************************
Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_hw_iomux__include
#define ti_devices_msp_peripherals_hw_iomux__include
/* Filename: hw_iomux.h */
/* Revised: 2023-05-10 21:32:43 */
/* Revision: ccc8d5592eceba00f0e63b10bdaec9c7cd64733b */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* IOMUX Registers
******************************************************************************/
#define IOMUX_SECCFG_OFS ((uint32_t)0x00000000U)
/** @addtogroup IOMUX_SECCFG
@{
*/
typedef struct {
uint32_t RESERVED0;
__IO uint32_t PINCM[251]; /* !< (@ 0x00000004) Pin Control Management Register in SECCFG region */
} IOMUX_SECCFG_Regs;
/*@}*/ /* end of group IOMUX_SECCFG */
/** @addtogroup IOMUX
@{
*/
typedef struct {
IOMUX_SECCFG_Regs SECCFG; /* !< (@ 0x00000000) SECCFG register region */
} IOMUX_Regs;
/*@}*/ /* end of group IOMUX */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* IOMUX Register Control Bits
******************************************************************************/
/* IOMUX_PINCM Bits */
/* IOMUX_PINCM[PF] Bits */
#define IOMUX_PINCM_PF_OFS (0) /* !< PF Offset */
#define IOMUX_PINCM_PF_MASK ((uint32_t)0x0000003FU) /* !< Peripheral Function selection bits */
#define IOMUX_PINCM_PF_MINIMUM ((uint32_t)0x00000000U) /* !< Reserved as unconnected */
#define IOMUX_PINCM_PF_MAXIMUM ((uint32_t)0x0000003FU) /* !< An encoding per function that can
be connected to this pin. */
/* IOMUX_PINCM[PC] Bits */
#define IOMUX_PINCM_PC_OFS (7) /* !< PC Offset */
#define IOMUX_PINCM_PC_MASK ((uint32_t)0x00000080U) /* !< Peripheral is Connected */
#define IOMUX_PINCM_PC_UNCONNECTED ((uint32_t)0x00000000U) /* !< The output of the peripheral (and
its output enable) will not propagate
to the IOCELL */
#define IOMUX_PINCM_PC_CONNECTED ((uint32_t)0x00000080U) /* !< The output latch of the dataflow
will be transparent */
/* IOMUX_PINCM[WAKESTAT] Bits */
#define IOMUX_PINCM_WAKESTAT_OFS (13) /* !< WAKESTAT Offset */
#define IOMUX_PINCM_WAKESTAT_MASK ((uint32_t)0x00002000U) /* !< This has the IOPAD WAKEUP signal as
status bit. */
#define IOMUX_PINCM_WAKESTAT_DISABLE ((uint32_t)0x00000000U) /* !< wakeup source is NOT from this
IOCELL */
#define IOMUX_PINCM_WAKESTAT_ENABLE ((uint32_t)0x00002000U) /* !< wakeup source is from this IOCELL */
/* IOMUX_PINCM[PIPD] Bits */
#define IOMUX_PINCM_PIPD_OFS (16) /* !< PIPD Offset */
#define IOMUX_PINCM_PIPD_MASK ((uint32_t)0x00010000U) /* !< Pull Down control selection */
#define IOMUX_PINCM_PIPD_DISABLE ((uint32_t)0x00000000U) /* !< Pull down is disabled. */
#define IOMUX_PINCM_PIPD_ENABLE ((uint32_t)0x00010000U) /* !< Pull down is enabled */
/* IOMUX_PINCM[PIPU] Bits */
#define IOMUX_PINCM_PIPU_OFS (17) /* !< PIPU Offset */
#define IOMUX_PINCM_PIPU_MASK ((uint32_t)0x00020000U) /* !< Pull Up control selection */
#define IOMUX_PINCM_PIPU_DISABLE ((uint32_t)0x00000000U) /* !< Pull up is disabled. */
#define IOMUX_PINCM_PIPU_ENABLE ((uint32_t)0x00020000U) /* !< Pull up is enabled */
/* IOMUX_PINCM[INENA] Bits */
#define IOMUX_PINCM_INENA_OFS (18) /* !< INENA Offset */
#define IOMUX_PINCM_INENA_MASK ((uint32_t)0x00040000U) /* !< Input Enable Control Selection */
#define IOMUX_PINCM_INENA_DISABLE ((uint32_t)0x00000000U) /* !< Input enable is disabled. */
#define IOMUX_PINCM_INENA_ENABLE ((uint32_t)0x00040000U) /* !< Input enable is enabled. */
/* IOMUX_PINCM[HYSTEN] Bits */
#define IOMUX_PINCM_HYSTEN_OFS (19) /* !< HYSTEN Offset */
#define IOMUX_PINCM_HYSTEN_MASK ((uint32_t)0x00080000U) /* !< Hysteresis Enable Control Selection */
#define IOMUX_PINCM_HYSTEN_ENABLE ((uint32_t)0x00000000U) /* !< hysteresis is enabled. */
#define IOMUX_PINCM_HYSTEN_DISABLE ((uint32_t)0x00080000U) /* !< hysteresis is disabled */
/* IOMUX_PINCM[DRV] Bits */
#define IOMUX_PINCM_DRV_OFS (20) /* !< DRV Offset */
#define IOMUX_PINCM_DRV_MASK ((uint32_t)0x00100000U) /* !< Drive strength control selection,
for HS IOCELL only */
#define IOMUX_PINCM_DRV_DRVVAL0 ((uint32_t)0x00000000U) /* !< Drive setting of 0 selected */
#define IOMUX_PINCM_DRV_DRVVAL1 ((uint32_t)0x00100000U) /* !< Drive setting of 1 selected */
/* IOMUX_PINCM[HIZ1] Bits */
#define IOMUX_PINCM_HIZ1_OFS (25) /* !< HIZ1 Offset */
#define IOMUX_PINCM_HIZ1_MASK ((uint32_t)0x02000000U) /* !< High output value will tri-state
the output when this bit is enabled */
#define IOMUX_PINCM_HIZ1_DISABLE ((uint32_t)0x00000000U) /* !< open-drain is disabled. */
#define IOMUX_PINCM_HIZ1_ENABLE ((uint32_t)0x02000000U) /* !< open-drain is enabled. */
/* IOMUX_PINCM[WUEN] Bits */
#define IOMUX_PINCM_WUEN_OFS (27) /* !< WUEN Offset */
#define IOMUX_PINCM_WUEN_MASK ((uint32_t)0x08000000U) /* !< Wakeup Enable bit */
#define IOMUX_PINCM_WUEN_DISABLE ((uint32_t)0x00000000U) /* !< wakeup is disabled. */
#define IOMUX_PINCM_WUEN_ENABLE ((uint32_t)0x08000000U) /* !< wakeup is enabled */
/* IOMUX_PINCM[WCOMP] Bits */
#define IOMUX_PINCM_WCOMP_OFS (28) /* !< WCOMP Offset */
#define IOMUX_PINCM_WCOMP_MASK ((uint32_t)0x10000000U) /* !< Wakeup Compare Value bit */
#define IOMUX_PINCM_WCOMP_MATCH0 ((uint32_t)0x00000000U) /* !< Wakeup on a match of 0 */
#define IOMUX_PINCM_WCOMP_MATCH1 ((uint32_t)0x10000000U) /* !< Wakeup on a match of 1 */
/* IOMUX_PINCM[INV] Bits */
#define IOMUX_PINCM_INV_OFS (26) /* !< INV Offset */
#define IOMUX_PINCM_INV_MASK ((uint32_t)0x04000000U) /* !< Data inversion selection */
#define IOMUX_PINCM_INV_DISABLE ((uint32_t)0x00000000U) /* !< Data inversion is disabled. */
#define IOMUX_PINCM_INV_ENABLE ((uint32_t)0x04000000U) /* !< Data inversion is enabled */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_hw_iomux__include */
libraries/sdk/ti/devices/msp/peripherals/hw_keystorectl.h
+203
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@@ -0,0 +1,203 @@
/*****************************************************************************
Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_hw_keystorectl__include
#define ti_devices_msp_peripherals_hw_keystorectl__include
/* This preliminary header file does not have a version number */
/* MMR repo: https://bitbucket.itg.ti.com/projects/cmcu_msp65ip/repos/f65mspkeystorectl */
/* MMR revision: da65027d31f78c7139cd945e99c27064d5e09c65 */
/* Generator revision: c98c4ac511e2bd0d918c5d427bd46b7a359dacf1
(MInT: ec7ec7482a60c6871be32db8b378ec27aa4771f6) */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* KEYSTORECTL Registers
******************************************************************************/
/** @addtogroup KEYSTORECTL
@{
*/
typedef struct {
uint32_t RESERVED0[1088];
__IO uint32_t CFG; /* !< (@ 0x00001100) Keystore configuration */
__IO uint32_t KEYWR; /* !< (@ 0x00001104) Key write configuration */
__IO uint32_t KEYRD; /* !< (@ 0x00001108) Key read configuration */
__I uint32_t STATUS; /* !< (@ 0x0000110C) Status */
__O uint32_t KEYIN; /* !< (@ 0x00001110) Input key */
} KEYSTORECTL_Regs;
/*@}*/ /* end of group KEYSTORECTL */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* KEYSTORECTL Register Control Bits
******************************************************************************/
/* KEYSTORECTL_CFG Bits */
/* KEYSTORECTL_CFG[NK256] Bits */
#define KEYSTORECTL_CFG_NK256_OFS (0) /* !< NK256 Offset */
#define KEYSTORECTL_CFG_NK256_MASK ((uint32_t)0x0000000FU) /* !< Number of 256 bit keys to be held
in the key-store. Can not exceed the
total number of slots present in the
hardware / 2. For eg: if SYS_N_SLOTS
= 4, then atmost 2 256-bit keys can
be held in the key-store. Incorrect
setting of this field will be
reported via STATUS register */
#define KEYSTORECTL_CFG_NK256_ZERO ((uint32_t)0x00000000U) /* !< No 256-bit keys */
#define KEYSTORECTL_CFG_NK256_ONE ((uint32_t)0x00000001U) /* !< One 256-bit key */
#define KEYSTORECTL_CFG_NK256_TWO ((uint32_t)0x00000002U) /* !< Two 256-bit keys */
#define KEYSTORECTL_CFG_NK256_THREE ((uint32_t)0x00000003U) /* !< Three 256-bit keys */
#define KEYSTORECTL_CFG_NK256_FOUR ((uint32_t)0x00000004U) /* !< Four 256-bit keys */
/* KEYSTORECTL_KEYWR Bits */
/* KEYSTORECTL_KEYWR[KEYSZSEL] Bits */
#define KEYSTORECTL_KEYWR_KEYSZSEL_OFS (0) /* !< KEYSZSEL Offset */
#define KEYSTORECTL_KEYWR_KEYSZSEL_MASK ((uint32_t)0x00000007U) /* !< Key size selection. Selection of
128 or 256 bit keys */
#define KEYSTORECTL_KEYWR_KEYSZSEL_K256 ((uint32_t)0x00000000U) /* !< 256 bit key */
#define KEYSTORECTL_KEYWR_KEYSZSEL_K128 ((uint32_t)0x00000001U) /* !< 128 bit key */
/* KEYSTORECTL_KEYWR[KEYSLOTSEL] Bits */
#define KEYSTORECTL_KEYWR_KEYSLOTSEL_OFS (4) /* !< KEYSLOTSEL Offset */
#define KEYSTORECTL_KEYWR_KEYSLOTSEL_MASK ((uint32_t)0x000000F0U) /* !< Select the key slot to write the
key into. NOTE: SW needs to ensure
that it is writing to the correct
slots. The slot numbering is from 0
through SYS_N_SLOTS-1. Each slot is a
128-bit slot. Therefore, when writing
a 256-bit key, two slots will need to
budgeted. */
#define KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT0 ((uint32_t)0x00000000U) /* !< Slot 0 */
#define KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT1 ((uint32_t)0x00000010U) /* !< Slot 1 */
#define KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT2 ((uint32_t)0x00000020U) /* !< Slot 2 */
#define KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT3 ((uint32_t)0x00000030U) /* !< Slot 3 */
#define KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT4 ((uint32_t)0x00000040U) /* !< Slot 4 */
#define KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT5 ((uint32_t)0x00000050U) /* !< Slot 5 */
#define KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT6 ((uint32_t)0x00000060U) /* !< Slot 6 */
#define KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT7 ((uint32_t)0x00000070U) /* !< Slot 7 */
/* KEYSTORECTL_KEYRD Bits */
/* KEYSTORECTL_KEYRD[KEYSZSEL] Bits */
#define KEYSTORECTL_KEYRD_KEYSZSEL_OFS (0) /* !< KEYSZSEL Offset */
#define KEYSTORECTL_KEYRD_KEYSZSEL_MASK ((uint32_t)0x00000007U) /* !< Key size selection. Selection of
128 or 256 bit keys */
#define KEYSTORECTL_KEYRD_KEYSZSEL_K256 ((uint32_t)0x00000000U) /* !< 256 bit key */
#define KEYSTORECTL_KEYRD_KEYSZSEL_K128 ((uint32_t)0x00000001U) /* !< 128 bit key */
/* KEYSTORECTL_KEYRD[KEYSLOTSEL] Bits */
#define KEYSTORECTL_KEYRD_KEYSLOTSEL_OFS (4) /* !< KEYSLOTSEL Offset */
#define KEYSTORECTL_KEYRD_KEYSLOTSEL_MASK ((uint32_t)0x000000F0U) /* !< Select the key slot to read the key
from. NOTE: SW needs to ensure that
it is reading from the correct slots.
The slot numbering is from 0 through
SYS_N_SLOTS-1. Each slot is a 128-bit
slot. Therefore, when reading a
256-bit key, two adjacent slots will
be read. */
/* KEYSTORECTL_KEYRD[CRYPTOSEL] Bits */
#define KEYSTORECTL_KEYRD_CRYPTOSEL_OFS (8) /* !< CRYPTOSEL Offset */
#define KEYSTORECTL_KEYRD_CRYPTOSEL_MASK ((uint32_t)0x00000300U) /* !< Crypto engine selector */
#define KEYSTORECTL_KEYRD_CRYPTOSEL_AES ((uint32_t)0x00000000U) /* !< Transfer key to AES */
/* KEYSTORECTL_STATUS Bits */
/* KEYSTORECTL_STATUS[STAT] Bits */
#define KEYSTORECTL_STATUS_STAT_OFS (0) /* !< STAT Offset */
#define KEYSTORECTL_STATUS_STAT_MASK ((uint32_t)0x0000000FU) /* !< Status information */
#define KEYSTORECTL_STATUS_STAT_VALID ((uint32_t)0x00000000U) /* !< Valid configuration */
#define KEYSTORECTL_STATUS_STAT_NO_CFG ((uint32_t)0x00000001U) /* !< Key-store has not been configured.
NK256 has not been set. */
#define KEYSTORECTL_STATUS_STAT_INVALID_NK256 ((uint32_t)0x00000002U) /* !< Invalid value for NK256 field in
CFG. */
#define KEYSTORECTL_STATUS_STAT_BUSY_RECEIVE ((uint32_t)0x00000003U) /* !< Busy receiving a key deposit */
#define KEYSTORECTL_STATUS_STAT_BUSY_TRANSMIT ((uint32_t)0x00000004U) /* !< Busy transmitting a key to a crypto
engine */
#define KEYSTORECTL_STATUS_STAT_INVALID_KEYSLOTSELW ((uint32_t)0x00000005U) /* !< Invalid keyslot selection for
writing */
#define KEYSTORECTL_STATUS_STAT_INVALID_KEYSLOTSELR ((uint32_t)0x00000006U) /* !< Invalid keyslot selection for
reading */
/* KEYSTORECTL_STATUS[VALID] Bits */
#define KEYSTORECTL_STATUS_VALID_OFS (4) /* !< VALID Offset */
#define KEYSTORECTL_STATUS_VALID_MASK ((uint32_t)0x00000FF0U) /* !< Bitvector of valid bits to indicate
which slots have been configured */
/* KEYSTORECTL_STATUS[NKEYSLOTS] Bits */
#define KEYSTORECTL_STATUS_NKEYSLOTS_OFS (16) /* !< NKEYSLOTS Offset */
#define KEYSTORECTL_STATUS_NKEYSLOTS_MASK ((uint32_t)0x00030000U) /* !< Size of keystorage: Number of
128-bit key slots */
#define KEYSTORECTL_STATUS_NKEYSLOTS_TWO ((uint32_t)0x00000000U) /* !< Two slots */
#define KEYSTORECTL_STATUS_NKEYSLOTS_THREE ((uint32_t)0x00010000U) /* !< Three slots */
#define KEYSTORECTL_STATUS_NKEYSLOTS_FOUR ((uint32_t)0x00020000U) /* !< Four slots */
/* KEYSTORECTL_KEYIN Bits */
/* KEYSTORECTL_KEYIN[DATA] Bits */
#define KEYSTORECTL_KEYIN_DATA_OFS (0) /* !< DATA Offset */
#define KEYSTORECTL_KEYIN_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< 32-bit key data */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_hw_keystorectl__include */
libraries/sdk/ti/devices/msp/peripherals/hw_lcd.h
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libraries/sdk/ti/devices/msp/peripherals/hw_lfss.h
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libraries/sdk/ti/devices/msp/peripherals/hw_mathacl.h
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/*****************************************************************************
Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_hw_mathacl__include
#define ti_devices_msp_peripherals_hw_mathacl__include
/* This preliminary header file does not have a version number */
/* MMR repo: https://bitbucket.itg.ti.com/projects/cmcu_msp65ip/repos/f65mspmathacl */
/* MMR revision: 9080fe468791d796cb4aed2ae9531011e6786af0 */
/* Generator revision: 77992b62fb4e9926f5a9143aae1e89fec6a84738
(MInT: ec7ec7482a60c6871be32db8b378ec27aa4771f6) */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* MATHACL Registers
******************************************************************************/
#define MATHACL_GPRCM_OFS ((uint32_t)0x00000800U)
/** @addtogroup MATHACL_GPRCM
@{
*/
typedef struct {
__IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */
__O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */
uint32_t RESERVED0[3];
__I uint32_t STAT; /* !< (@ 0x00000814) Status Register */
} MATHACL_GPRCM_Regs;
/*@}*/ /* end of group MATHACL_GPRCM */
/** @addtogroup MATHACL
@{
*/
typedef struct {
uint32_t RESERVED0[512];
MATHACL_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */
uint32_t RESERVED1[570];
__IO uint32_t CTL; /* !< (@ 0x00001100) Control Register */
uint32_t RESERVED2[5];
__IO uint32_t OP2; /* !< (@ 0x00001118) Operand 2 register. */
__IO uint32_t OP1; /* !< (@ 0x0000111C) Operand 1 register. */
__IO uint32_t RES1; /* !< (@ 0x00001120) Result 1 register. */
__IO uint32_t RES2; /* !< (@ 0x00001124) Result 2 register. */
uint32_t RESERVED3[2];
__I uint32_t STATUS; /* !< (@ 0x00001130) Status Register */
uint32_t RESERVED4[3];
__O uint32_t STATUSCLR; /* !< (@ 0x00001140) Status flag clear register */
} MATHACL_Regs;
/*@}*/ /* end of group MATHACL */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* MATHACL Register Control Bits
******************************************************************************/
/* MATHACL_PWREN Bits */
/* MATHACL_PWREN[ENABLE] Bits */
#define MATHACL_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */
#define MATHACL_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */
#define MATHACL_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */
#define MATHACL_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */
/* MATHACL_PWREN[KEY] Bits */
#define MATHACL_PWREN_KEY_OFS (24) /* !< KEY Offset */
#define MATHACL_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */
#define MATHACL_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this
register */
/* MATHACL_RSTCTL Bits */
/* MATHACL_RSTCTL[RESETSTKYCLR] Bits */
#define MATHACL_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */
#define MATHACL_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT
register */
#define MATHACL_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define MATHACL_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */
/* MATHACL_RSTCTL[RESETASSERT] Bits */
#define MATHACL_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */
#define MATHACL_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */
#define MATHACL_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define MATHACL_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */
/* MATHACL_RSTCTL[KEY] Bits */
#define MATHACL_RSTCTL_KEY_OFS (24) /* !< KEY Offset */
#define MATHACL_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */
#define MATHACL_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this
register */
/* MATHACL_STAT Bits */
/* MATHACL_STAT[RESETSTKY] Bits */
#define MATHACL_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */
#define MATHACL_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the
peripheral was reset, since this bit
was cleared by RESETSTKYCLR in the
RSTCTL register */
#define MATHACL_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset
since this bit was last cleared by
RESETSTKYCLR in the RSTCTL register */
#define MATHACL_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the
last bit clear */
/* MATHACL_CTL Bits */
/* MATHACL_CTL[FUNC] Bits */
#define MATHACL_CTL_FUNC_OFS (0) /* !< FUNC Offset */
#define MATHACL_CTL_FUNC_MASK ((uint32_t)0x0000001FU) /* !< ULP_ADCHP Enable Conversions. */
#define MATHACL_CTL_FUNC_NOP ((uint32_t)0x00000000U) /* !< No operation */
#define MATHACL_CTL_FUNC_SINCOS ((uint32_t)0x00000001U) /* !< Sine and Cosine operation */
#define MATHACL_CTL_FUNC_ATAN2 ((uint32_t)0x00000002U) /* !< Arc tangent with x and y values as
operands. */
#define MATHACL_CTL_FUNC_DIV ((uint32_t)0x00000004U) /* !< Divide, the operands are numerator,
denominator, and the divide type.
Result is the quotient and reminder. */
#define MATHACL_CTL_FUNC_SQRT ((uint32_t)0x00000005U) /* !< Do square root. Operand is the
number whoose square root needs to be
computed. The number if outside the
range needs to be scaled up down by
2 power 2n to bring it with in the
range. */
#define MATHACL_CTL_FUNC_MPY32 ((uint32_t)0x00000006U) /* !< 32-bit Multiply Result */
#define MATHACL_CTL_FUNC_SQUARE32 ((uint32_t)0x00000007U) /* !< 32-bit square result */
#define MATHACL_CTL_FUNC_MPY64 ((uint32_t)0x00000008U) /* !< 64-bit multiply result */
#define MATHACL_CTL_FUNC_SQUARE64 ((uint32_t)0x00000009U) /* !< 64-bit multiply result */
#define MATHACL_CTL_FUNC_MAC ((uint32_t)0x0000000AU) /* !< Multiply and accumulate operation */
#define MATHACL_CTL_FUNC_SAC ((uint32_t)0x0000000BU) /* !< Square and accumulate operation */
/* MATHACL_CTL[QVAL] Bits */
#define MATHACL_CTL_QVAL_OFS (8) /* !< QVAL Offset */
#define MATHACL_CTL_QVAL_MASK ((uint32_t)0x00001F00U) /* !< Indicates the fractional bits in
the operands, ranges from 0 to 31.
Applicable to DIV function. */
#define MATHACL_CTL_QVAL_Q0 ((uint32_t)0x00000000U) /* !< Q0 operands */
#define MATHACL_CTL_QVAL_Q1 ((uint32_t)0x00000100U) /* !< Q1 operands */
#define MATHACL_CTL_QVAL_Q2 ((uint32_t)0x00000200U) /* !< Q2 operands */
#define MATHACL_CTL_QVAL_Q3 ((uint32_t)0x00000300U) /* !< Q3 operands */
#define MATHACL_CTL_QVAL_Q4 ((uint32_t)0x00000400U) /* !< Q4 operands */
#define MATHACL_CTL_QVAL_Q5 ((uint32_t)0x00000500U) /* !< Q5 operands */
#define MATHACL_CTL_QVAL_Q6 ((uint32_t)0x00000600U) /* !< Q6 operands */
#define MATHACL_CTL_QVAL_Q7 ((uint32_t)0x00000700U) /* !< Q7 operands */
#define MATHACL_CTL_QVAL_Q8 ((uint32_t)0x00000800U) /* !< Q8 operands */
#define MATHACL_CTL_QVAL_Q9 ((uint32_t)0x00000900U) /* !< Q9 operands */
#define MATHACL_CTL_QVAL_Q10 ((uint32_t)0x00000A00U) /* !< Q10 operands */
#define MATHACL_CTL_QVAL_Q11 ((uint32_t)0x00000B00U) /* !< Q11 operands */
#define MATHACL_CTL_QVAL_Q12 ((uint32_t)0x00000C00U) /* !< Q12 operands */
#define MATHACL_CTL_QVAL_Q13 ((uint32_t)0x00000D00U) /* !< Q13 operands */
#define MATHACL_CTL_QVAL_Q14 ((uint32_t)0x00000E00U) /* !< Q14 operands */
#define MATHACL_CTL_QVAL_Q15 ((uint32_t)0x00000F00U) /* !< Q15 operands */
#define MATHACL_CTL_QVAL_Q16 ((uint32_t)0x00001000U) /* !< Q16 operands */
#define MATHACL_CTL_QVAL_Q17 ((uint32_t)0x00001100U) /* !< Q17 operands */
#define MATHACL_CTL_QVAL_Q18 ((uint32_t)0x00001200U) /* !< Q18 operands */
#define MATHACL_CTL_QVAL_Q19 ((uint32_t)0x00001300U) /* !< Q19 operands */
#define MATHACL_CTL_QVAL_Q20 ((uint32_t)0x00001400U) /* !< Q20 operands */
#define MATHACL_CTL_QVAL_Q21 ((uint32_t)0x00001500U) /* !< Q21 operands */
#define MATHACL_CTL_QVAL_Q22 ((uint32_t)0x00001600U) /* !< Q22 operands */
#define MATHACL_CTL_QVAL_Q23 ((uint32_t)0x00001700U) /* !< Q23 operands */
#define MATHACL_CTL_QVAL_Q24 ((uint32_t)0x00001800U) /* !< Q24 operands */
#define MATHACL_CTL_QVAL_Q25 ((uint32_t)0x00001900U) /* !< Q25 operands */
#define MATHACL_CTL_QVAL_Q26 ((uint32_t)0x00001A00U) /* !< Q26 operands */
#define MATHACL_CTL_QVAL_Q27 ((uint32_t)0x00001B00U) /* !< Q27 operands */
#define MATHACL_CTL_QVAL_Q28 ((uint32_t)0x00001C00U) /* !< Q28 operands */
#define MATHACL_CTL_QVAL_Q29 ((uint32_t)0x00001D00U) /* !< Q29 operands */
#define MATHACL_CTL_QVAL_Q30 ((uint32_t)0x00001E00U) /* !< Q30 operands */
#define MATHACL_CTL_QVAL_Q31 ((uint32_t)0x00001F00U) /* !< Q31 operands */
/* MATHACL_CTL[OPTYPE] Bits */
#define MATHACL_CTL_OPTYPE_OFS (5) /* !< OPTYPE Offset */
#define MATHACL_CTL_OPTYPE_MASK ((uint32_t)0x00000020U) /* !< Operand type, could signed or
unsigned. applicable to DIV function. */
#define MATHACL_CTL_OPTYPE_UNSIGNED ((uint32_t)0x00000000U) /* !< Unsigned operands */
#define MATHACL_CTL_OPTYPE_SIGNED ((uint32_t)0x00000020U) /* !< Signed operands. */
/* MATHACL_CTL[NUMITER] Bits */
#define MATHACL_CTL_NUMITER_OFS (24) /* !< NUMITER Offset */
#define MATHACL_CTL_NUMITER_MASK ((uint32_t)0x1F000000U) /* !< Number of iterations, applicable if
the function does the computations
iteratively, for example
sine/cosine/atan2/sqrt. Note: A value
of 0 is interpreted as 31. */
/* MATHACL_CTL[SFACTOR] Bits */
#define MATHACL_CTL_SFACTOR_OFS (16) /* !< SFACTOR Offset */
#define MATHACL_CTL_SFACTOR_MASK ((uint32_t)0x003F0000U) /* !< Scaling factor. In case of SQRT
function, the input operand needs to
be in a range. If not it has to be
scaled to 2^(+/-n). This field should
be written with the value 'n'. */
/* MATHACL_CTL[SATEN] Bits */
#define MATHACL_CTL_SATEN_OFS (22) /* !< SATEN Offset */
#define MATHACL_CTL_SATEN_MASK ((uint32_t)0x00400000U) /* !< Saturation enable This bit is
shared among DIV, SQUARE32, MPY32,
MAC and SAC functions. When enabled,
it will make the result to saturate
to maximum value in case of an
overflow event When disabled, the
result will overflow to an unknown
value. */
#define MATHACL_CTL_SATEN_DISABLE ((uint32_t)0x00000000U) /* !< Saturation is disabled */
#define MATHACL_CTL_SATEN_ENABLE ((uint32_t)0x00400000U) /* !< Saturation is enabled */
/* MATHACL_OP2 Bits */
/* MATHACL_OP2[DATA] Bits */
#define MATHACL_OP2_DATA_OFS (0) /* !< DATA Offset */
#define MATHACL_OP2_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Operand 2 Register */
/* MATHACL_OP1 Bits */
/* MATHACL_OP1[DATA] Bits */
#define MATHACL_OP1_DATA_OFS (0) /* !< DATA Offset */
#define MATHACL_OP1_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Operand 1 register. */
/* MATHACL_RES1 Bits */
/* MATHACL_RES1[DATA] Bits */
#define MATHACL_RES1_DATA_OFS (0) /* !< DATA Offset */
#define MATHACL_RES1_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Result 1 register */
/* MATHACL_RES2 Bits */
/* MATHACL_RES2[DATA] Bits */
#define MATHACL_RES2_DATA_OFS (0) /* !< DATA Offset */
#define MATHACL_RES2_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Result 2 register */
/* MATHACL_STATUS Bits */
/* MATHACL_STATUS[UF] Bits */
#define MATHACL_STATUS_UF_OFS (0) /* !< UF Offset */
#define MATHACL_STATUS_UF_MASK ((uint32_t)0x00000001U) /* !< Underflow Flag */
#define MATHACL_STATUS_UF_NO_UNDERFLOW ((uint32_t)0x00000000U) /* !< No undreflow error. */
#define MATHACL_STATUS_UF_UNDERFLOW ((uint32_t)0x00000001U) /* !< Underflow error. */
/* MATHACL_STATUS[OVF] Bits */
#define MATHACL_STATUS_OVF_OFS (1) /* !< OVF Offset */
#define MATHACL_STATUS_OVF_MASK ((uint32_t)0x00000002U) /* !< Overflow bit for MPY32, SQUARE32,
DIV, MAC, and SAC functions This bit
will be set on overflow and will
retain its value until cleared by
writing 1 into CLR.CLR_OVF */
#define MATHACL_STATUS_OVF_NO_OVERFLOW ((uint32_t)0x00000000U) /* !< No overflow error. */
#define MATHACL_STATUS_OVF_OVERFLOW ((uint32_t)0x00000000U) /* !< Overflow error. */
/* MATHACL_STATUS[ERR] Bits */
#define MATHACL_STATUS_ERR_OFS (2) /* !< ERR Offset */
#define MATHACL_STATUS_ERR_MASK ((uint32_t)0x0000000CU) /* !< Incorrect inputs/outputs. */
#define MATHACL_STATUS_ERR_NOERROR ((uint32_t)0x00000000U) /* !< No Error in computation. */
#define MATHACL_STATUS_ERR_DIVBY0 ((uint32_t)0x00000004U) /* !< DIVBY0 error */
/* MATHACL_STATUS[BUSY] Bits */
#define MATHACL_STATUS_BUSY_OFS (8) /* !< BUSY Offset */
#define MATHACL_STATUS_BUSY_MASK ((uint32_t)0x00000100U) /* !< MATHACL busy bit. */
#define MATHACL_STATUS_BUSY_DONE ((uint32_t)0x00000000U) /* !< Compute has completed. */
#define MATHACL_STATUS_BUSY_NOTDONE ((uint32_t)0x00000100U) /* !< Compute ongoing */
/* MATHACL_STATUSCLR Bits */
/* MATHACL_STATUSCLR[CLR_OVF] Bits */
#define MATHACL_STATUSCLR_CLR_OVF_OFS (1) /* !< CLR_OVF Offset */
#define MATHACL_STATUSCLR_CLR_OVF_MASK ((uint32_t)0x00000002U) /* !< Write 1 to this bit to clear
STATUS.OVF bit */
#define MATHACL_STATUSCLR_CLR_OVF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define MATHACL_STATUSCLR_CLR_OVF_CLR ((uint32_t)0x00000002U) /* !< Clear STATUS.OVF */
/* MATHACL_STATUSCLR[CLR_UF] Bits */
#define MATHACL_STATUSCLR_CLR_UF_OFS (0) /* !< CLR_UF Offset */
#define MATHACL_STATUSCLR_CLR_UF_MASK ((uint32_t)0x00000001U) /* !< Write 1 to this bit to clear
STATUS.UF bit */
#define MATHACL_STATUSCLR_CLR_UF_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define MATHACL_STATUSCLR_CLR_UF_CLR ((uint32_t)0x00000001U) /* !< Clear STATUS.UF */
/* MATHACL_STATUSCLR[CLR_ERR] Bits */
#define MATHACL_STATUSCLR_CLR_ERR_OFS (2) /* !< CLR_ERR Offset */
#define MATHACL_STATUSCLR_CLR_ERR_MASK ((uint32_t)0x00000004U) /* !< Write 1 to this bit to clear
STATUS.ERR field */
#define MATHACL_STATUSCLR_CLR_ERR_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define MATHACL_STATUSCLR_CLR_ERR_CLR ((uint32_t)0x00000004U) /* !< Clear STATUS.ERR */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_hw_mathacl__include */
libraries/sdk/ti/devices/msp/peripherals/hw_mcan.h
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libraries/sdk/ti/devices/msp/peripherals/hw_oa.h
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@@ -0,0 +1,292 @@
/*****************************************************************************
Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_hw_oa__include
#define ti_devices_msp_peripherals_hw_oa__include
/* This preliminary header file does not have a version number */
/* MMR repo: https://bitbucket.itg.ti.com/projects/cmcu_msp65ip/repos/f65mspoa */
/* MMR revision: 89377c76ba10fe939dabf3c32948d02a456b2167 */
/* Generator revision: b581896b67084e57bafba0cd5bf5aa0fc4c1ca1a
(MInT: ec7ec7482a60c6871be32db8b378ec27aa4771f6) */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* OA Registers
******************************************************************************/
#define OA_GPRCM_OFS ((uint32_t)0x00000800U)
/** @addtogroup OA_GPRCM
@{
*/
typedef struct {
__IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */
__O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */
uint32_t RESERVED0[3];
__I uint32_t STAT; /* !< (@ 0x00000814) Status Register */
} OA_GPRCM_Regs;
/*@}*/ /* end of group OA_GPRCM */
/** @addtogroup OA
@{
*/
typedef struct {
uint32_t RESERVED0[512];
OA_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */
uint32_t RESERVED1[510];
__IO uint32_t CLKOVR; /* !< (@ 0x00001010) Clock Override */
uint32_t RESERVED2[2];
__IO uint32_t PWRCTL; /* !< (@ 0x0000101C) Power Control */
uint32_t RESERVED3[56];
__IO uint32_t CTL; /* !< (@ 0x00001100) Control Register */
__IO uint32_t CFGBASE; /* !< (@ 0x00001104) Configuration Base Register */
__IO uint32_t CFG; /* !< (@ 0x00001108) Configuration Register */
uint32_t RESERVED4[3];
__I uint32_t STAT; /* !< (@ 0x00001118) Status Register */
} OA_Regs;
/*@}*/ /* end of group OA */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* OA Register Control Bits
******************************************************************************/
/* OA_PWREN Bits */
/* OA_PWREN[ENABLE] Bits */
#define OA_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */
#define OA_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */
#define OA_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */
#define OA_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */
/* OA_PWREN[KEY] Bits */
#define OA_PWREN_KEY_OFS (24) /* !< KEY Offset */
#define OA_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */
#define OA_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this
register */
/* OA_RSTCTL Bits */
/* OA_RSTCTL[RESETSTKYCLR] Bits */
#define OA_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */
#define OA_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT
register */
#define OA_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define OA_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */
/* OA_RSTCTL[RESETASSERT] Bits */
#define OA_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */
#define OA_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */
#define OA_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define OA_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */
/* OA_RSTCTL[KEY] Bits */
#define OA_RSTCTL_KEY_OFS (24) /* !< KEY Offset */
#define OA_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */
#define OA_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this
register */
/* OA_GPRCM_STAT Bits */
/* OA_GPRCM_STAT[RESETSTKY] Bits */
#define OA_GPRCM_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */
#define OA_GPRCM_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the
peripheral was reset, since this bit
was cleared by RESETSTKYCLR in the
RSTCTL register */
#define OA_GPRCM_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset
since this bit was last cleared by
RESETSTKYCLR in the RSTCTL register */
#define OA_GPRCM_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the
last bit clear */
/* OA_CLKOVR Bits */
/* OA_CLKOVR[OVERRIDE] Bits */
#define OA_CLKOVR_OVERRIDE_OFS (0) /* !< OVERRIDE Offset */
#define OA_CLKOVR_OVERRIDE_MASK ((uint32_t)0x00000001U) /* !< Unlocks the functionality of
[RUN_STOP] to override the automatic
peripheral clock request */
#define OA_CLKOVR_OVERRIDE_DISABLED ((uint32_t)0x00000000U) /* !< Override disabled */
#define OA_CLKOVR_OVERRIDE_ENABLED ((uint32_t)0x00000001U) /* !< Override enabled */
/* OA_CLKOVR[RUN_STOP] Bits */
#define OA_CLKOVR_RUN_STOP_OFS (1) /* !< RUN_STOP Offset */
#define OA_CLKOVR_RUN_STOP_MASK ((uint32_t)0x00000002U) /* !< If [OVERRIDE] is enabled, this
register is used to manually control
the peripheral's clock request to the
system */
#define OA_CLKOVR_RUN_STOP_RUN ((uint32_t)0x00000000U) /* !< Run/ungate functional clock */
#define OA_CLKOVR_RUN_STOP_STOP ((uint32_t)0x00000002U) /* !< Stop/gate functional clock */
/* OA_PWRCTL Bits */
/* OA_PWRCTL[AUTO_OFF] Bits */
#define OA_PWRCTL_AUTO_OFF_OFS (0) /* !< AUTO_OFF Offset */
#define OA_PWRCTL_AUTO_OFF_MASK ((uint32_t)0x00000001U) /* !< When set the peripheral will remove
its local IP request for enable so
that it can be disabled if no other
entities in the system are requesting
it to be enabled. */
#define OA_PWRCTL_AUTO_OFF_DISABLE ((uint32_t)0x00000000U) /* !< Disable automatic power off
function */
#define OA_PWRCTL_AUTO_OFF_ENABLE ((uint32_t)0x00000001U) /* !< Enable automatic power off function */
/* OA_CTL Bits */
/* OA_CTL[ENABLE] Bits */
#define OA_CTL_ENABLE_OFS (0) /* !< ENABLE Offset */
#define OA_CTL_ENABLE_MASK ((uint32_t)0x00000001U) /* !< OAxn Enable. */
#define OA_CTL_ENABLE_OFF ((uint32_t)0x00000000U) /* !< OAxn OFF */
#define OA_CTL_ENABLE_ON ((uint32_t)0x00000001U) /* !< OAxn ON */
/* OA_CFGBASE Bits */
/* OA_CFGBASE[GBW] Bits */
#define OA_CFGBASE_GBW_OFS (0) /* !< GBW Offset */
#define OA_CFGBASE_GBW_MASK ((uint32_t)0x00000001U) /* !< Select gain bandwidth which affects
current as well the gain bandwidth.
The lower gain bandwidth has lower
current. See device specific
datasheet for values. Can only be
modified when STAT.BUSY=0. */
#define OA_CFGBASE_GBW_LOWGAIN ((uint32_t)0x00000000U) /* !< Low gain bandwidth. See device
specific datasheet for gain
bandwidth. */
#define OA_CFGBASE_GBW_HIGHGAIN ((uint32_t)0x00000001U) /* !< High gain bandwidth. See device
specific datasheet for gain
bandwidth. */
/* OA_CFGBASE[RRI] Bits */
#define OA_CFGBASE_RRI_OFS (2) /* !< RRI Offset */
#define OA_CFGBASE_RRI_MASK ((uint32_t)0x00000004U) /* !< Rail-to-rail input enable. Can only
be modified when STAT.BUSY=0 */
#define OA_CFGBASE_RRI_OFF ((uint32_t)0x00000000U) /* !< Rail-to-rail input disable. */
#define OA_CFGBASE_RRI_ON ((uint32_t)0x00000004U) /* !< Rail-to-rail input enable. */
/* OA_CFG Bits */
/* OA_CFG[CHOP] Bits */
#define OA_CFG_CHOP_OFS (0) /* !< CHOP Offset */
#define OA_CFG_CHOP_MASK ((uint32_t)0x00000003U) /* !< Chopping enable. */
#define OA_CFG_CHOP_OFF ((uint32_t)0x00000000U) /* !< Chopping disable. */
#define OA_CFG_CHOP_ON ((uint32_t)0x00000001U) /* !< Standard chopping enable. */
#define OA_CFG_CHOP_AVGON ((uint32_t)0x00000002U) /* !< Chop with post average on. Requires
output to be connect to ADC in
average mode. */
/* OA_CFG[OUTPIN] Bits */
#define OA_CFG_OUTPIN_OFS (2) /* !< OUTPIN Offset */
#define OA_CFG_OUTPIN_MASK ((uint32_t)0x00000004U) /* !< Enable output pin */
#define OA_CFG_OUTPIN_DISABLED ((uint32_t)0x00000000U) /* !< Output pin disabled */
#define OA_CFG_OUTPIN_ENABLED ((uint32_t)0x00000004U) /* !< Output pin enabled */
/* OA_CFG[PSEL] Bits */
#define OA_CFG_PSEL_OFS (3) /* !< PSEL Offset */
#define OA_CFG_PSEL_MASK ((uint32_t)0x00000078U) /* !< Positive OA input selection.
Please refer to the device specific
datasheet for exact channels
available. */
#define OA_CFG_PSEL_NC ((uint32_t)0x00000000U) /* !< No connect */
#define OA_CFG_PSEL_EXTPIN0 ((uint32_t)0x00000008U) /* !< external pin OA+0 */
#define OA_CFG_PSEL_EXTPIN1 ((uint32_t)0x00000010U) /* !< external pin OAn+1 */
#define OA_CFG_PSEL_DAC12OUT ((uint32_t)0x00000018U) /* !< DAC12OUT */
#define OA_CFG_PSEL_DAC8OUT ((uint32_t)0x00000020U) /* !< DAC8OUT */
#define OA_CFG_PSEL_VREF ((uint32_t)0x00000028U) /* !< VREF Channel */
#define OA_CFG_PSEL_OANM1RTOP ((uint32_t)0x00000030U) /* !< OA[n-1]Rtop */
#define OA_CFG_PSEL_GPAMP_OUT_INT ((uint32_t)0x00000038U) /* !< GPAMP_OUT_INT Input */
#define OA_CFG_PSEL_VSS ((uint32_t)0x00000040U) /* !< Internal Grouund Connection */
/* OA_CFG[NSEL] Bits */
#define OA_CFG_NSEL_OFS (7) /* !< NSEL Offset */
#define OA_CFG_NSEL_MASK ((uint32_t)0x00000380U) /* !< Negative OA input selection. Please
refer to the device specific
datasheet for exact channels
available. */
#define OA_CFG_NSEL_NC ((uint32_t)0x00000000U) /* !< no connect */
#define OA_CFG_NSEL_EXTPIN0 ((uint32_t)0x00000080U) /* !< external pin OAn-0 */
#define OA_CFG_NSEL_EXTPIN1 ((uint32_t)0x00000100U) /* !< external pin OAn-1 */
#define OA_CFG_NSEL_OANP1RBOT ((uint32_t)0x00000180U) /* !< OA[n+1]Rbot */
#define OA_CFG_NSEL_OANRTAP ((uint32_t)0x00000200U) /* !< OA[n]Rtap */
#define OA_CFG_NSEL_OANRTOP ((uint32_t)0x00000280U) /* !< OA[n]Rtop */
#define OA_CFG_NSEL_SPARE ((uint32_t)0x00000300U) /* !< Spare input */
/* OA_CFG[MSEL] Bits */
#define OA_CFG_MSEL_OFS (10) /* !< MSEL Offset */
#define OA_CFG_MSEL_MASK ((uint32_t)0x00001C00U) /* !< MSEL Mux selection. Please refer
to the device specific datasheet for
exact channels available. */
#define OA_CFG_MSEL_NC ((uint32_t)0x00000000U) /* !< no connect */
#define OA_CFG_MSEL_EXTNPIN1 ((uint32_t)0x00000400U) /* !< external pin OAn-1 */
#define OA_CFG_MSEL_VSS ((uint32_t)0x00000800U) /* !< VSS */
#define OA_CFG_MSEL_DAC12OUT ((uint32_t)0x00000C00U) /* !< DAC12 Output */
#define OA_CFG_MSEL_OANM1RTOP ((uint32_t)0x00001000U) /* !< OA[n-1]Rtop */
/* OA_CFG[GAIN] Bits */
#define OA_CFG_GAIN_OFS (13) /* !< GAIN Offset */
#define OA_CFG_GAIN_MASK ((uint32_t)0x0000E000U) /* !< Gain setting. Refer to TRM for
enumeration information. */
#define OA_CFG_GAIN_MINIMUM ((uint32_t)0x00000000U) /* !< Minmum gain value */
#define OA_CFG_GAIN_MAXIMUM ((uint32_t)0x0000E000U) /* !< Maximum gain value. */
/* OA_STAT Bits */
/* OA_STAT[RDY] Bits */
#define OA_STAT_RDY_OFS (0) /* !< RDY Offset */
#define OA_STAT_RDY_MASK ((uint32_t)0x00000001U) /* !< OA ready status. */
#define OA_STAT_RDY_FALSE ((uint32_t)0x00000000U) /* !< OAxn is not ready. */
#define OA_STAT_RDY_TRUE ((uint32_t)0x00000001U) /* !< OAxn is ready. */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_hw_oa__include */
libraries/sdk/ti/devices/msp/peripherals/hw_rtc.h
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libraries/sdk/ti/devices/msp/peripherals/hw_spi.h
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libraries/sdk/ti/devices/msp/peripherals/hw_trng.h
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/*****************************************************************************
Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_hw_trng__include
#define ti_devices_msp_peripherals_hw_trng__include
/* Filename: hw_trng.h */
/* Revised: 2023-06-13 16:12:38 */
/* Revision: f9b237fa1b82e8166ce3ead25b505b784578352a */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* TRNG Registers
******************************************************************************/
#define TRNG_CPU_INT_OFS ((uint32_t)0x00001020U)
#define TRNG_GPRCM_OFS ((uint32_t)0x00000800U)
/** @addtogroup TRNG_CPU_INT
@{
*/
typedef struct {
__I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */
uint32_t RESERVED0;
__IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */
uint32_t RESERVED1;
__I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */
uint32_t RESERVED2;
__I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */
uint32_t RESERVED3;
__O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */
uint32_t RESERVED4;
__O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */
} TRNG_CPU_INT_Regs;
/*@}*/ /* end of group TRNG_CPU_INT */
/** @addtogroup TRNG_GPRCM
@{
*/
typedef struct {
__IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */
__O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */
uint32_t RESERVED0[3];
__I uint32_t STAT; /* !< (@ 0x00000814) Status Register */
} TRNG_GPRCM_Regs;
/*@}*/ /* end of group TRNG_GPRCM */
/** @addtogroup TRNG
@{
*/
typedef struct {
uint32_t RESERVED0[512];
TRNG_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */
uint32_t RESERVED1[514];
TRNG_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */
uint32_t RESERVED2[44];
__I uint32_t DESC; /* !< (@ 0x000010FC) Module descriptions */
__IO uint32_t CTL; /* !< (@ 0x00001100) Controls the command and decimation rate */
__I uint32_t STAT; /* !< (@ 0x00001104) Status register that informs health test results
and last issued command */
__I uint32_t DATA_CAPTURE; /* !< (@ 0x00001108) Captured word buffer of RNG data */
__I uint32_t TEST_RESULTS; /* !< (@ 0x0000110C) Test results from TEST_ANA and TEST_DIG */
__IO uint32_t CLKDIVIDE; /* !< (@ 0x00001110) Clock Divider */
} TRNG_Regs;
/*@}*/ /* end of group TRNG */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* TRNG Register Control Bits
******************************************************************************/
/* TRNG_IIDX Bits */
/* TRNG_IIDX[STAT] Bits */
#define TRNG_IIDX_STAT_OFS (0) /* !< STAT Offset */
#define TRNG_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */
#define TRNG_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No bit is set means there is no
pending interrupt request */
#define TRNG_IIDX_STAT_IRQ_HEALTH_FAIL ((uint32_t)0x00000001U) /* !< Indicates that a health test has
failed. The TRNG is in an error state
until the interrupt is cleared. */
#define TRNG_IIDX_STAT_IRQ_CMD_FAIL ((uint32_t)0x00000002U) /* !< Indicates that the just issued
command was rejected and is not being
performed. */
#define TRNG_IIDX_STAT_IRQ_CMD_DONE ((uint32_t)0x00000003U) /* !< Indicates that the current
command/mode is done. This may have
different meanings based on the mode:
OFF --> Power has been turned off
PWRUP_DIG --> Digital powerup tests
are done PWRUP_ANA --> Analog powerup
tests are done NORM_FUNC --> No IRQ,
since mode runs indefinitely until a
new command is issued */
#define TRNG_IIDX_STAT_IRQ_CAPTURED_RDY ((uint32_t)0x00000004U) /* !< Indicates that the captured word
buffer is ready to be copied to
memory */
/* TRNG_IMASK Bits */
/* TRNG_IMASK[IRQ_HEALTH_FAIL] Bits */
#define TRNG_IMASK_IRQ_HEALTH_FAIL_OFS (0) /* !< IRQ_HEALTH_FAIL Offset */
#define TRNG_IMASK_IRQ_HEALTH_FAIL_MASK ((uint32_t)0x00000001U) /* !< Mask for IRQ_HEALTH_FAIL. Indicates
that a health test has failed. */
#define TRNG_IMASK_IRQ_HEALTH_FAIL_DISABLED ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define TRNG_IMASK_IRQ_HEALTH_FAIL_ENABLED ((uint32_t)0x00000001U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* TRNG_IMASK[IRQ_CAPTURED_RDY] Bits */
#define TRNG_IMASK_IRQ_CAPTURED_RDY_OFS (3) /* !< IRQ_CAPTURED_RDY Offset */
#define TRNG_IMASK_IRQ_CAPTURED_RDY_MASK ((uint32_t)0x00000008U) /* !< Mask for IRQ_CAPTURED_RDY.
Indicates to the CPU that the
Captured Word is ready to be read. */
#define TRNG_IMASK_IRQ_CAPTURED_RDY_DISABLED ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define TRNG_IMASK_IRQ_CAPTURED_RDY_ENABLED ((uint32_t)0x00000008U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* TRNG_IMASK[IRQ_CMD_DONE] Bits */
#define TRNG_IMASK_IRQ_CMD_DONE_OFS (2) /* !< IRQ_CMD_DONE Offset */
#define TRNG_IMASK_IRQ_CMD_DONE_MASK ((uint32_t)0x00000004U) /* !< Mask for IRQ_CMD_DONE. Indicates
that a command has finished */
#define TRNG_IMASK_IRQ_CMD_DONE_DISABLED ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define TRNG_IMASK_IRQ_CMD_DONE_ENABLED ((uint32_t)0x00000004U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* TRNG_IMASK[IRQ_CMD_FAIL] Bits */
#define TRNG_IMASK_IRQ_CMD_FAIL_OFS (1) /* !< IRQ_CMD_FAIL Offset */
#define TRNG_IMASK_IRQ_CMD_FAIL_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt source for
IRQ_CMD_FAIL. Indicates that the just
issued command/mode has been
rejected. */
#define TRNG_IMASK_IRQ_CMD_FAIL_DISABLED ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define TRNG_IMASK_IRQ_CMD_FAIL_ENABLED ((uint32_t)0x00000002U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* TRNG_RIS Bits */
/* TRNG_RIS[IRQ_CAPTURED_RDY] Bits */
#define TRNG_RIS_IRQ_CAPTURED_RDY_OFS (3) /* !< IRQ_CAPTURED_RDY Offset */
#define TRNG_RIS_IRQ_CAPTURED_RDY_MASK ((uint32_t)0x00000008U) /* !< Indicates to the CPU that the
Captured Word is ready to be read.
Reading the IIDX will clear this
interrupt. */
#define TRNG_RIS_IRQ_CAPTURED_RDY_CLR ((uint32_t)0x00000000U) /* !< IRQ_CAPTURED_READY did not occur */
#define TRNG_RIS_IRQ_CAPTURED_RDY_SET ((uint32_t)0x00000008U) /* !< IRQ_CAPTURED_READY occurred */
/* TRNG_RIS[IRQ_HEALTH_FAIL] Bits */
#define TRNG_RIS_IRQ_HEALTH_FAIL_OFS (0) /* !< IRQ_HEALTH_FAIL Offset */
#define TRNG_RIS_IRQ_HEALTH_FAIL_MASK ((uint32_t)0x00000001U) /* !< Indicates to the CPU that any of
the health tests have failed. Reading
the IIDX will clear this interrupt. */
#define TRNG_RIS_IRQ_HEALTH_FAIL_CLR ((uint32_t)0x00000000U) /* !< IRQ_CAPTURED_READY did not occur */
#define TRNG_RIS_IRQ_HEALTH_FAIL_SET ((uint32_t)0x00000001U) /* !< IRQ_CAPTURED_READY occurred */
/* TRNG_RIS[IRQ_CMD_DONE] Bits */
#define TRNG_RIS_IRQ_CMD_DONE_OFS (2) /* !< IRQ_CMD_DONE Offset */
#define TRNG_RIS_IRQ_CMD_DONE_MASK ((uint32_t)0x00000004U) /* !< Raw interrupt source for
IRQ_CMD_DONE. Indicates that the
issued command/mode has completed. */
#define TRNG_RIS_IRQ_CMD_DONE_CLR ((uint32_t)0x00000000U) /* !< IRQ_CMD_DONE did not occur */
#define TRNG_RIS_IRQ_CMD_DONE_SET ((uint32_t)0x00000004U) /* !< IRQ_CMD_DONE occurred */
/* TRNG_RIS[IRQ_CMD_FAIL] Bits */
#define TRNG_RIS_IRQ_CMD_FAIL_OFS (1) /* !< IRQ_CMD_FAIL Offset */
#define TRNG_RIS_IRQ_CMD_FAIL_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt source for
IRQ_CMD_FAIL. Indicates that the just
issued command/mode has been
rejected. */
#define TRNG_RIS_IRQ_CMD_FAIL_CLR ((uint32_t)0x00000000U) /* !< IRQ_CMD_FAIL did not occur */
#define TRNG_RIS_IRQ_CMD_FAIL_SET ((uint32_t)0x00000002U) /* !< IRQ_CMD_FAIL occurred */
/* TRNG_MIS Bits */
/* TRNG_MIS[IRQ_CAPTURED_RDY] Bits */
#define TRNG_MIS_IRQ_CAPTURED_RDY_OFS (3) /* !< IRQ_CAPTURED_RDY Offset */
#define TRNG_MIS_IRQ_CAPTURED_RDY_MASK ((uint32_t)0x00000008U) /* !< Masked interrupt result for
CAPTURED_READY. Indicates to the CPU
that the Captured Word is ready to be
read. Reading the IIDX will clear
this interrupt. */
#define TRNG_MIS_IRQ_CAPTURED_RDY_CLR ((uint32_t)0x00000000U) /* !< IRQ_CAPTURED_READY did not request
an interrupt service routine */
#define TRNG_MIS_IRQ_CAPTURED_RDY_SET ((uint32_t)0x00000008U) /* !< IRQ_CAPTURED_READY requests an
interrupt service routine */
/* TRNG_MIS[IRQ_HEALTH_FAIL] Bits */
#define TRNG_MIS_IRQ_HEALTH_FAIL_OFS (0) /* !< IRQ_HEALTH_FAIL Offset */
#define TRNG_MIS_IRQ_HEALTH_FAIL_MASK ((uint32_t)0x00000001U) /* !< Masked interrupt result for
HEALTH_FAIL. Indicates to the CPU
that any of the health tests have
failed for the latest 1024-bit
window. */
#define TRNG_MIS_IRQ_HEALTH_FAIL_CLR ((uint32_t)0x00000000U) /* !< IRQ_CAPTURED_READY did not request
an interrupt service routine */
#define TRNG_MIS_IRQ_HEALTH_FAIL_SET ((uint32_t)0x00000001U) /* !< IRQ_CAPTURED_READY requests an
interrupt service routine */
/* TRNG_MIS[IRQ_CMD_DONE] Bits */
#define TRNG_MIS_IRQ_CMD_DONE_OFS (2) /* !< IRQ_CMD_DONE Offset */
#define TRNG_MIS_IRQ_CMD_DONE_MASK ((uint32_t)0x00000004U) /* !< Masked interrupt source for
IRQ_CMD_DONE. Indicates that the
issued command/mode has completed. */
#define TRNG_MIS_IRQ_CMD_DONE_CLR ((uint32_t)0x00000000U) /* !< IRQ_CAPTURED_READY did not request
an interrupt service routine */
#define TRNG_MIS_IRQ_CMD_DONE_SET ((uint32_t)0x00000004U) /* !< IRQ_CMD_DONE requests an interrupt
service routine */
/* TRNG_MIS[IRQ_CMD_FAIL] Bits */
#define TRNG_MIS_IRQ_CMD_FAIL_OFS (1) /* !< IRQ_CMD_FAIL Offset */
#define TRNG_MIS_IRQ_CMD_FAIL_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt source for
IRQ_CMD_FAIL. Indicates that the just
issued command/mode has been
rejected. */
#define TRNG_MIS_IRQ_CMD_FAIL_CLR ((uint32_t)0x00000000U) /* !< IRQ_CMD_FAIL did not request an
interrupt service routine */
#define TRNG_MIS_IRQ_CMD_FAIL_SET ((uint32_t)0x00000002U) /* !< IRQ_CMD_FAIL requests an interrupt
service routine */
/* TRNG_ISET Bits */
/* TRNG_ISET[IRQ_CAPTURED_RDY] Bits */
#define TRNG_ISET_IRQ_CAPTURED_RDY_OFS (3) /* !< IRQ_CAPTURED_RDY Offset */
#define TRNG_ISET_IRQ_CAPTURED_RDY_MASK ((uint32_t)0x00000008U) /* !< Indicates to the CPU that the
Captured Word is ready to be read.
Reading the IIDX or DATA_CAPTURE
registers will clear this interrupt. */
#define TRNG_ISET_IRQ_CAPTURED_RDY_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define TRNG_ISET_IRQ_CAPTURED_RDY_SET ((uint32_t)0x00000008U) /* !< RIS bit corresponding to
CAPTURED_READY is set */
/* TRNG_ISET[IRQ_HEALTH_FAIL] Bits */
#define TRNG_ISET_IRQ_HEALTH_FAIL_OFS (0) /* !< IRQ_HEALTH_FAIL Offset */
#define TRNG_ISET_IRQ_HEALTH_FAIL_MASK ((uint32_t)0x00000001U) /* !< Indicates to the CPU that any of
the health tests have failed. Reading
the IIDX or DATA_CAPTURE registers
will clear this interrupt. */
#define TRNG_ISET_IRQ_HEALTH_FAIL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define TRNG_ISET_IRQ_HEALTH_FAIL_SET ((uint32_t)0x00000001U) /* !< RIS bit corresponding to
HEALTH_FAIL is set */
/* TRNG_ISET[IRQ_CMD_DONE] Bits */
#define TRNG_ISET_IRQ_CMD_DONE_OFS (2) /* !< IRQ_CMD_DONE Offset */
#define TRNG_ISET_IRQ_CMD_DONE_MASK ((uint32_t)0x00000004U) /* !< Write to turn on CMD_DONE IRQ.
Indicates that the last issued TRNG
command has finished. */
#define TRNG_ISET_IRQ_CMD_DONE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect. */
#define TRNG_ISET_IRQ_CMD_DONE_SET ((uint32_t)0x00000004U) /* !< RIS bit corresponding to CMD_DONE
is set */
/* TRNG_ISET[IRQ_CMD_FAIL] Bits */
#define TRNG_ISET_IRQ_CMD_FAIL_OFS (1) /* !< IRQ_CMD_FAIL Offset */
#define TRNG_ISET_IRQ_CMD_FAIL_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt source for
IRQ_CMD_FAIL. Indicates that the just
issued command/mode has been
rejected. */
#define TRNG_ISET_IRQ_CMD_FAIL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect. */
#define TRNG_ISET_IRQ_CMD_FAIL_SET ((uint32_t)0x00000002U) /* !< RIS bit corresponding to CMD_FAIL
is set */
/* TRNG_ICLR Bits */
/* TRNG_ICLR[IRQ_CAPTURED_RDY] Bits */
#define TRNG_ICLR_IRQ_CAPTURED_RDY_OFS (3) /* !< IRQ_CAPTURED_RDY Offset */
#define TRNG_ICLR_IRQ_CAPTURED_RDY_MASK ((uint32_t)0x00000008U) /* !< Indicates to the CPU that the
Captured Word is ready to be read.
Reading the IIDX or DATA_CAPTURE
registers will clear this interrupt. */
#define TRNG_ICLR_IRQ_CAPTURED_RDY_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define TRNG_ICLR_IRQ_CAPTURED_RDY_CLR ((uint32_t)0x00000008U) /* !< RIS bit corresponding to
CAPTURED_READY is cleared */
/* TRNG_ICLR[IRQ_HEALTH_FAIL] Bits */
#define TRNG_ICLR_IRQ_HEALTH_FAIL_OFS (0) /* !< IRQ_HEALTH_FAIL Offset */
#define TRNG_ICLR_IRQ_HEALTH_FAIL_MASK ((uint32_t)0x00000001U) /* !< Indicates to the CPU that any of
the health tests have failed. Reading
the IIDX or DATA_CAPTURE registers
will clear this interrupt. */
#define TRNG_ICLR_IRQ_HEALTH_FAIL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define TRNG_ICLR_IRQ_HEALTH_FAIL_CLR ((uint32_t)0x00000001U) /* !< RIS bit corresponding to
CAPTURED_READY is cleared */
/* TRNG_ICLR[IRQ_CMD_DONE] Bits */
#define TRNG_ICLR_IRQ_CMD_DONE_OFS (2) /* !< IRQ_CMD_DONE Offset */
#define TRNG_ICLR_IRQ_CMD_DONE_MASK ((uint32_t)0x00000004U) /* !< Write to turn off CMD_DONE IRQ.
Indicates that the last issued TRNG
command has finished. */
#define TRNG_ICLR_IRQ_CMD_DONE_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect. */
#define TRNG_ICLR_IRQ_CMD_DONE_CLR ((uint32_t)0x00000004U) /* !< RIS bit corresponding to CMD_DONE
is cleared */
/* TRNG_ICLR[IRQ_CMD_FAIL] Bits */
#define TRNG_ICLR_IRQ_CMD_FAIL_OFS (1) /* !< IRQ_CMD_FAIL Offset */
#define TRNG_ICLR_IRQ_CMD_FAIL_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt source for
IRQ_CMD_FAIL. Indicates that the just
issued command/mode has been
rejected. */
#define TRNG_ICLR_IRQ_CMD_FAIL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect. */
#define TRNG_ICLR_IRQ_CMD_FAIL_CLR ((uint32_t)0x00000002U) /* !< RIS bit corresponding to CMD_FAIL
is cleared */
/* TRNG_PWREN Bits */
/* TRNG_PWREN[ENABLE] Bits */
#define TRNG_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */
#define TRNG_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */
#define TRNG_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */
#define TRNG_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */
/* TRNG_PWREN[KEY] Bits */
#define TRNG_PWREN_KEY_OFS (24) /* !< KEY Offset */
#define TRNG_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */
#define TRNG_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this
register */
/* TRNG_RSTCTL Bits */
/* TRNG_RSTCTL[RESETSTKYCLR] Bits */
#define TRNG_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */
#define TRNG_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT
register */
#define TRNG_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define TRNG_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */
/* TRNG_RSTCTL[RESETASSERT] Bits */
#define TRNG_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */
#define TRNG_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */
#define TRNG_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define TRNG_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */
/* TRNG_RSTCTL[KEY] Bits */
#define TRNG_RSTCTL_KEY_OFS (24) /* !< KEY Offset */
#define TRNG_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */
#define TRNG_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this
register */
/* TRNG_GPRCM_STAT Bits */
/* TRNG_GPRCM_STAT[RESETSTKY] Bits */
#define TRNG_GPRCM_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */
#define TRNG_GPRCM_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the
peripheral was reset, since this bit
was cleared by RESETSTKYCLR in the
RSTCTL register */
#define TRNG_GPRCM_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset
since this bit was last cleared by
RESETSTKYCLR in the RSTCTL register */
#define TRNG_GPRCM_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the
last bit clear */
/* TRNG_DESC Bits */
/* TRNG_DESC[MINREV] Bits */
#define TRNG_DESC_MINREV_OFS (0) /* !< MINREV Offset */
#define TRNG_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */
/* TRNG_DESC[MAJREV] Bits */
#define TRNG_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */
#define TRNG_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */
/* TRNG_DESC[INSTNUM] Bits */
#define TRNG_DESC_INSTNUM_OFS (8) /* !< INSTNUM Offset */
#define TRNG_DESC_INSTNUM_MASK ((uint32_t)0x00000F00U) /* !< Instance Number within the device.
This will be a parameter to the RTL
for modules that can have multiple
instances */
/* TRNG_DESC[FEATUREVER] Bits */
#define TRNG_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */
#define TRNG_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module
*instance* */
/* TRNG_DESC[MODULEID] Bits */
#define TRNG_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */
#define TRNG_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module Identifier - An internal TI
page has been created to request
unique module IDs */
/* TRNG_CTL Bits */
/* TRNG_CTL[DECIM_RATE] Bits */
#define TRNG_CTL_DECIM_RATE_OFS (8) /* !< DECIM_RATE Offset */
#define TRNG_CTL_DECIM_RATE_MASK ((uint32_t)0x00000700U) /* !< Set decimation rate. Decimate by n
0x0 = Decimation by 1 (no decimation)
0x1 = Decimation by 2 (Skip every
other sample) 0x7 = Decimation by 8
(Take every 8th sample) */
/* TRNG_CTL[PWRUP_CLKDIV] Bits */
#define TRNG_CTL_PWRUP_CLKDIV_OFS (16) /* !< PWRUP_CLKDIV Offset */
#define TRNG_CTL_PWRUP_CLKDIV_MASK ((uint32_t)0x00010000U) /* !< When '1', the powerup sequence will
take twice as long (i.e., clock
frequency halved) */
/* TRNG_CTL[PWRUP_PCHRG_CFG] Bits */
#define TRNG_CTL_PWRUP_PCHRG_CFG_OFS (17) /* !< PWRUP_PCHRG_CFG Offset */
#define TRNG_CTL_PWRUP_PCHRG_CFG_MASK ((uint32_t)0x00060000U) /* !< Configure PCHARGE sequence length
b00 = Disabled b01 = 20 us PCHARGE
b10 = 30 us PCHARGE (default) b11 =
40 us PCHARGE */
/* TRNG_CTL[PWRUP_PSTART_CFG] Bits */
#define TRNG_CTL_PWRUP_PSTART_CFG_OFS (19) /* !< PWRUP_PSTART_CFG Offset */
#define TRNG_CTL_PWRUP_PSTART_CFG_MASK ((uint32_t)0x00180000U) /* !< Configure pusle startup sequence
length b00 = Disabled b01 = rise at
10us, fall at 50us b10 = rise at
10us, fall at 70us (default) b11 =
rise at 10us, fall at 90us */
/* TRNG_CTL[CMD] Bits */
#define TRNG_CTL_CMD_OFS (0) /* !< CMD Offset */
#define TRNG_CTL_CMD_MASK ((uint32_t)0x00000003U) /* !< Sets the TRNG mode through a
command. The mode will not be updated
until the previous command is done,
as indicated by IRQ_CMD_DONE. 00 -->
OFF 01 --> PWRUP_DIG 10 --> PWRUP_ANA
11 --> NORM_FUNC */
#define TRNG_CTL_CMD_PWR_OFF ((uint32_t)0x00000000U) /* !< Turns the power off of the analog
source and clocks the digital
interface */
#define TRNG_CTL_CMD_PWRUP_DIG ((uint32_t)0x00000001U) /* !< Initiates the powerup test sequence
for the digital components. This
verifies that the digital components
are properly working. IRQ_CMD_DONE
indicates that the test is done. The
results of this test are in bits 0:6
in TEST_RESULTS register */
#define TRNG_CTL_CMD_PWRUP_ANA ((uint32_t)0x00000002U) /* !< Initiates the powerup test sequence
for the analog TRNG. This verifies
that the analog component is
generating sequences with enough
entropy. IRQ_CMD_DONE indicates that
the test is done. The results of this
test are in bit 7 in TEST_RESULTS
register */
#define TRNG_CTL_CMD_NORM_FUNC ((uint32_t)0x00000003U) /* !< Normal operating mode for TRNG. All
components are turned on. */
/* TRNG_STAT Bits */
/* TRNG_STAT[ADAP_FAIL] Bits */
#define TRNG_STAT_ADAP_FAIL_OFS (0) /* !< ADAP_FAIL Offset */
#define TRNG_STAT_ADAP_FAIL_MASK ((uint32_t)0x00000001U) /* !< Indicates that the Adaptive
Proportion Test (1,2,3, or 4-bit
counters) failed by having too many
or too few counted samples in the
last 1024 bit window. */
/* TRNG_STAT[ISSUED_CMD] Bits */
#define TRNG_STAT_ISSUED_CMD_OFS (8) /* !< ISSUED_CMD Offset */
#define TRNG_STAT_ISSUED_CMD_MASK ((uint32_t)0x00000300U) /* !< Indicates the last accepted command
that is issued to the TRNG interface.
Upon writing a valid command, this
register will update and the command
will be in progress until
CMD_DONE_IRQ is set. CMD_DONE_IRQ
indicates that the state is in
PWROFF, NORM_FUNC, or ERROR. These
states will accept new commands. 00
--> OFF 01 --> PWRUP_DIG 10 -->
PWRUP_ANA 11 --> NORM_FUNC */
/* TRNG_STAT[FSM_STATE] Bits */
#define TRNG_STAT_FSM_STATE_OFS (16) /* !< FSM_STATE Offset */
#define TRNG_STAT_FSM_STATE_MASK ((uint32_t)0x000F0000U) /* !< Current state of the front end FSM
(behind a clock domain crossing). 2
reads are REQUIRED as there is a
chance of metastability when reading
this States: 0000: OFF 0001: PWRUP_ES
0011: NORM_FUNC 0111: TEST_DIG 1011:
TEST_ANA 1010: ERROR 0010: PWRDOWN_ES */
/* TRNG_STAT[REP_FAIL] Bits */
#define TRNG_STAT_REP_FAIL_OFS (1) /* !< REP_FAIL Offset */
#define TRNG_STAT_REP_FAIL_MASK ((uint32_t)0x00000002U) /* !< Indicates that the repetition
counter test caused the most recent
failure. Thus, the health count
numbers are most likely not for a
complete 1024-bit window. */
/* TRNG_DATA_CAPTURE Bits */
/* TRNG_DATA_CAPTURE[BUFFER] Bits */
#define TRNG_DATA_CAPTURE_BUFFER_OFS (0) /* !< BUFFER Offset */
#define TRNG_DATA_CAPTURE_BUFFER_MASK ((uint32_t)0xFFFFFFFFU) /* !< Captured Data from the Decimation
Block */
/* TRNG_TEST_RESULTS Bits */
/* TRNG_TEST_RESULTS[DIG_TEST] Bits */
#define TRNG_TEST_RESULTS_DIG_TEST_OFS (0) /* !< DIG_TEST Offset */
#define TRNG_TEST_RESULTS_DIG_TEST_MASK ((uint32_t)0x000000FFU) /* !< Bit 0 indicates if the first
decimation rate test and health
test(verifies conditioning,
decimation, and captured buffer)
fails and Bit 1 indicates if the
second decimation test and health
test fails Bit 0 - decim_test0 (decim
= 0x0) Bit 1 - decim_test1 (decim =
0x1) ... */
/* TRNG_TEST_RESULTS[ANA_TEST] Bits */
#define TRNG_TEST_RESULTS_ANA_TEST_OFS (8) /* !< ANA_TEST Offset */
#define TRNG_TEST_RESULTS_ANA_TEST_MASK ((uint32_t)0x00000100U) /* !< Runs through 4096 samples from an
enabled entropy source and verifies
that none of the health tests failed,
indicating sufficient entropy was
produced by the analog components */
/* TRNG_CLKDIVIDE Bits */
/* TRNG_CLKDIVIDE[RATIO] Bits */
#define TRNG_CLKDIVIDE_RATIO_OFS (0) /* !< RATIO Offset */
#define TRNG_CLKDIVIDE_RATIO_MASK ((uint32_t)0x00000007U) /* !< Selects divide ratio of module
clock */
#define TRNG_CLKDIVIDE_RATIO_DIV_BY_1 ((uint32_t)0x00000000U) /* !< Do not divide clock source */
#define TRNG_CLKDIVIDE_RATIO_DIV_BY_2 ((uint32_t)0x00000001U) /* !< Divide clock source by 2 */
#define TRNG_CLKDIVIDE_RATIO_DIV_BY_4 ((uint32_t)0x00000003U) /* !< Divide clock source by 4 */
#define TRNG_CLKDIVIDE_RATIO_DIV_BY_6 ((uint32_t)0x00000005U) /* !< Divide clock source by 6 */
#define TRNG_CLKDIVIDE_RATIO_DIV_BY_8 ((uint32_t)0x00000007U) /* !< Divide clock source by 8 */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_hw_trng__include */
libraries/sdk/ti/devices/msp/peripherals/hw_uart.h
+1841
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File diff suppressed because it is too large Load Diff
libraries/sdk/ti/devices/msp/peripherals/hw_vref.h
+244
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@@ -0,0 +1,244 @@
/*****************************************************************************
Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_hw_vref__include
#define ti_devices_msp_peripherals_hw_vref__include
/* Filename: hw_vref.h */
/* Revised: 2023-05-10 21:34:47 */
/* Revision: 346daa750fb9270ab4d9c503b44addb19c7cc8cc */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* VREF Registers
******************************************************************************/
#define VREF_GPRCM_OFS ((uint32_t)0x00000800U)
/** @addtogroup VREF_GPRCM
@{
*/
typedef struct {
__IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */
__O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */
uint32_t RESERVED0[3];
__I uint32_t STAT; /* !< (@ 0x00000814) Status Register */
} VREF_GPRCM_Regs;
/*@}*/ /* end of group VREF_GPRCM */
/** @addtogroup VREF
@{
*/
typedef struct {
uint32_t RESERVED0[512];
VREF_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */
uint32_t RESERVED1[506];
__IO uint32_t CLKDIV; /* !< (@ 0x00001000) Clock Divider */
uint32_t RESERVED2;
__IO uint32_t CLKSEL; /* !< (@ 0x00001008) Clock Selection */
uint32_t RESERVED3[61];
__IO uint32_t CTL0; /* !< (@ 0x00001100) Control 0 */
__IO uint32_t CTL1; /* !< (@ 0x00001104) Control 1 */
__IO uint32_t CTL2; /* !< (@ 0x00001108) Control 2 */
} VREF_Regs;
/*@}*/ /* end of group VREF */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* VREF Register Control Bits
******************************************************************************/
/* VREF_PWREN Bits */
/* VREF_PWREN[ENABLE] Bits */
#define VREF_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */
#define VREF_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power */
#define VREF_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */
#define VREF_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */
/* VREF_PWREN[KEY] Bits */
#define VREF_PWREN_KEY_OFS (24) /* !< KEY Offset */
#define VREF_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */
#define VREF_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this
register */
/* VREF_RSTCTL Bits */
/* VREF_RSTCTL[RESETSTKYCLR] Bits */
#define VREF_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */
#define VREF_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear the RESETSTKY bit in the STAT
register */
#define VREF_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define VREF_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */
/* VREF_RSTCTL[RESETASSERT] Bits */
#define VREF_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */
#define VREF_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral */
#define VREF_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define VREF_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */
/* VREF_RSTCTL[KEY] Bits */
#define VREF_RSTCTL_KEY_OFS (24) /* !< KEY Offset */
#define VREF_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */
#define VREF_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this
register */
/* VREF_STAT Bits */
/* VREF_STAT[RESETSTKY] Bits */
#define VREF_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */
#define VREF_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the
peripheral was reset, since this bit
was cleared by RESETSTKYCLR in the
RSTCTL register */
#define VREF_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset
since this bit was last cleared by
RESETSTKYCLR in the RSTCTL register */
#define VREF_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the
last bit clear */
/* VREF_CLKDIV Bits */
/* VREF_CLKDIV[RATIO] Bits */
#define VREF_CLKDIV_RATIO_OFS (0) /* !< RATIO Offset */
#define VREF_CLKDIV_RATIO_MASK ((uint32_t)0x00000007U) /* !< Selects divide ratio of module
clock to be used in sample and hold
logic */
/* VREF_CLKSEL Bits */
/* VREF_CLKSEL[LFCLK_SEL] Bits */
#define VREF_CLKSEL_LFCLK_SEL_OFS (1) /* !< LFCLK_SEL Offset */
#define VREF_CLKSEL_LFCLK_SEL_MASK ((uint32_t)0x00000002U) /* !< Selects LFCLK as clock source if
enabled */
/* VREF_CLKSEL[MFCLK_SEL] Bits */
#define VREF_CLKSEL_MFCLK_SEL_OFS (2) /* !< MFCLK_SEL Offset */
#define VREF_CLKSEL_MFCLK_SEL_MASK ((uint32_t)0x00000004U) /* !< Selects MFCLK as clock source if
enabled */
/* VREF_CLKSEL[BUSCLK_SEL] Bits */
#define VREF_CLKSEL_BUSCLK_SEL_OFS (3) /* !< BUSCLK_SEL Offset */
#define VREF_CLKSEL_BUSCLK_SEL_MASK ((uint32_t)0x00000008U) /* !< Selects BUSCLK as clock source if
enabled */
/* VREF_CTL0 Bits */
/* VREF_CTL0[ENABLE] Bits */
#define VREF_CTL0_ENABLE_OFS (0) /* !< ENABLE Offset */
#define VREF_CTL0_ENABLE_MASK ((uint32_t)0x00000001U) /* !< This bit enables the VREF module. */
#define VREF_CTL0_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< VREF is disabled */
#define VREF_CTL0_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< VREF is enabled */
/* VREF_CTL0[BUFCONFIG] Bits */
#define VREF_CTL0_BUFCONFIG_OFS (7) /* !< BUFCONFIG Offset */
#define VREF_CTL0_BUFCONFIG_MASK ((uint32_t)0x00000080U) /* !< These bits configure output buffer. */
#define VREF_CTL0_BUFCONFIG_OUTPUT2P5V ((uint32_t)0x00000000U) /* !< Configure Output Buffer to 2.5v */
#define VREF_CTL0_BUFCONFIG_OUTPUT1P4V ((uint32_t)0x00000080U) /* !< Configure Output Buffer to 1.4v */
/* VREF_CTL0[SHMODE] Bits */
#define VREF_CTL0_SHMODE_OFS (8) /* !< SHMODE Offset */
#define VREF_CTL0_SHMODE_MASK ((uint32_t)0x00000100U) /* !< This bit enable sample and hold
mode */
#define VREF_CTL0_SHMODE_DISABLE ((uint32_t)0x00000000U) /* !< Sample and hold mode is disable */
#define VREF_CTL0_SHMODE_ENABLE ((uint32_t)0x00000100U) /* !< Sample and hold mode is enable */
/* VREF_CTL0[COMP_VREF_ENABLE] Bits */
#define VREF_CTL0_COMP_VREF_ENABLE_OFS (1) /* !< COMP_VREF_ENABLE Offset */
#define VREF_CTL0_COMP_VREF_ENABLE_MASK ((uint32_t)0x00000002U) /* !< Comparator Vref Enable */
#define VREF_CTL0_COMP_VREF_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< COMP VREF is disabled */
#define VREF_CTL0_COMP_VREF_ENABLE_ENABLE ((uint32_t)0x00000002U) /* !< COMP VREF is enabled */
/* VREF_CTL1 Bits */
/* VREF_CTL1[READY] Bits */
#define VREF_CTL1_READY_OFS (0) /* !< READY Offset */
#define VREF_CTL1_READY_MASK ((uint32_t)0x00000001U) /* !< These bits defines status of VREF */
#define VREF_CTL1_READY_NOTRDY ((uint32_t)0x00000000U) /* !< VREF output is not ready */
#define VREF_CTL1_READY_RDY ((uint32_t)0x00000001U) /* !< VREF output is ready */
/* VREF_CTL2 Bits */
/* VREF_CTL2[SHCYCLE] Bits */
#define VREF_CTL2_SHCYCLE_OFS (0) /* !< SHCYCLE Offset */
#define VREF_CTL2_SHCYCLE_MASK ((uint32_t)0x0000FFFFU) /* !< Sample and Hold cycle count Total
cycles of module clock for sample and
hold phase when VREF is working in
sample and hold mode in STANDBY to
save power. This field should be
greater than HCYCLE field. The
difference between this field and
HCYCLE gives the number of cycles of
sample phase. Please refer VREF
section of datasheet for recommended
values of sample and hold times. */
#define VREF_CTL2_SHCYCLE_MINIMUM ((uint32_t)0x00000000U) /* !< smallest sample and hold cycle
count */
#define VREF_CTL2_SHCYCLE_MAXIMUM ((uint32_t)0x0000FFFFU) /* !< largest sample and hold cycle */
/* VREF_CTL2[HCYCLE] Bits */
#define VREF_CTL2_HCYCLE_OFS (16) /* !< HCYCLE Offset */
#define VREF_CTL2_HCYCLE_MASK ((uint32_t)0xFFFF0000U) /* !< Hold cycle count Total cycles of
module clock for hold phase when VREF
is working in sample and hold mode in
STANDBY to save power. Please refer
VREF section of datasheet for
recommended values of sample and hold
times. */
#define VREF_CTL2_HCYCLE_MINIMUM ((uint32_t)0x00000000U) /* !< smallest hold cycle */
#define VREF_CTL2_HCYCLE_MAXIMUM ((uint32_t)0xFFFF0000U) /* !< largest hold cycle */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_hw_vref__include */
libraries/sdk/ti/devices/msp/peripherals/hw_wuc.h
+128
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@@ -0,0 +1,128 @@
/*****************************************************************************
Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_hw_wuc__include
#define ti_devices_msp_peripherals_hw_wuc__include
/* This preliminary header file does not have a version number */
/* MMR repo: https://bitbucket.itg.ti.com/projects/cmcu_msp65ip/repos/f65mspwuc */
/* MMR revision: 3f3c7febcc901c572b112d1a4f92d5ccd9701ce1 */
/* Generator revision: 77992b62fb4e9926f5a9143aae1e89fec6a84738
(MInT: ec7ec7482a60c6871be32db8b378ec27aa4771f6) */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* WUC Registers
******************************************************************************/
/** @addtogroup WUC
@{
*/
typedef struct {
uint32_t RESERVED0[256];
__IO uint32_t FSUB_0; /* !< (@ 0x00000400) Subscriber Port 0 */
__IO uint32_t FSUB_1; /* !< (@ 0x00000404) Subscriber Port 1 */
} WUC_Regs;
/*@}*/ /* end of group WUC */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* WUC Register Control Bits
******************************************************************************/
/* WUC_FSUB_0 Bits */
/* WUC_FSUB_0[CHANID] Bits */
#define WUC_FSUB_0_CHANID_OFS (0) /* !< CHANID Offset */
#define WUC_FSUB_0_CHANID_MASK ((uint32_t)0x000000FFU) /* !< 0 = disconnected. 1-15 = connected
to channelID = CHANID. */
#define WUC_FSUB_0_CHANID_MNIMUM ((uint32_t)0x00000000U) /* !< 0 is an allowed value, signifying
that the event is unconnected */
#define WUC_FSUB_0_CHANID_UNCONNECTED ((uint32_t)0x00000000U) /* !< A value of 0 specifies that the
event is not connected */
#define WUC_FSUB_0_CHANID_MAXIMUM ((uint32_t)0x0000000FU) /* !< Consult your device datasheet as
the actual allowed maximum may be
less than 15. */
/* WUC_FSUB_1 Bits */
/* WUC_FSUB_1[CHANID] Bits */
#define WUC_FSUB_1_CHANID_OFS (0) /* !< CHANID Offset */
#define WUC_FSUB_1_CHANID_MASK ((uint32_t)0x000000FFU) /* !< 0 = disconnected. 1-15 = connected
to channelID = CHANID. */
#define WUC_FSUB_1_CHANID_MNIMUM ((uint32_t)0x00000000U) /* !< 0 is an allowed value, signifying
that the event is unconnected */
#define WUC_FSUB_1_CHANID_UNCONNECTED ((uint32_t)0x00000000U) /* !< A value of 0 specifies that the
event is not connected */
#define WUC_FSUB_1_CHANID_MAXIMUM ((uint32_t)0x0000000FU) /* !< Consult your device datasheet as
the actual allowed maximum may be
less than15. */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_hw_wuc__include */
libraries/sdk/ti/devices/msp/peripherals/hw_wwdt.h
+448
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@@ -0,0 +1,448 @@
/*****************************************************************************
Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_hw_wwdt__include
#define ti_devices_msp_peripherals_hw_wwdt__include
/* Filename: hw_wwdt.h */
/* Revised: 2023-05-10 21:36:51 */
/* Revision: 662977591cca7f583e1df6fe4b402c6c07949212 */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* WWDT Registers
******************************************************************************/
#define WWDT_CPU_INT_OFS ((uint32_t)0x00001020U)
#define WWDT_GPRCM_OFS ((uint32_t)0x00000800U)
/** @addtogroup WWDT_CPU_INT
@{
*/
typedef struct {
__I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */
uint32_t RESERVED0;
__IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */
uint32_t RESERVED1;
__I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */
uint32_t RESERVED2;
__I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */
uint32_t RESERVED3;
__O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */
uint32_t RESERVED4;
__O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */
} WWDT_CPU_INT_Regs;
/*@}*/ /* end of group WWDT_CPU_INT */
/** @addtogroup WWDT_GPRCM
@{
*/
typedef struct {
__IO uint32_t PWREN; /* !< (@ 0x00000800) Power enable */
__O uint32_t RSTCTL; /* !< (@ 0x00000804) Reset Control */
uint32_t RESERVED0[3];
__I uint32_t STAT; /* !< (@ 0x00000814) Status Register */
} WWDT_GPRCM_Regs;
/*@}*/ /* end of group WWDT_GPRCM */
/** @addtogroup WWDT
@{
*/
typedef struct {
uint32_t RESERVED0[512];
WWDT_GPRCM_Regs GPRCM; /* !< (@ 0x00000800) */
uint32_t RESERVED1[512];
__IO uint32_t PDBGCTL; /* !< (@ 0x00001018) Peripheral Debug Control */
uint32_t RESERVED2;
WWDT_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */
uint32_t RESERVED3[37];
__IO uint32_t EVT_MODE; /* !< (@ 0x000010E0) Event Mode */
uint32_t RESERVED4[6];
__I uint32_t DESC; /* !< (@ 0x000010FC) Module Description */
__IO uint32_t WWDTCTL0; /* !< (@ 0x00001100) Window Watchdog Timer Control Register 0 */
__IO uint32_t WWDTCTL1; /* !< (@ 0x00001104) Window Watchdog Timer Control Register 0 */
__IO uint32_t WWDTCNTRST; /* !< (@ 0x00001108) Window Watchdog Timer Counter Reset Register */
__I uint32_t WWDTSTAT; /* !< (@ 0x0000110C) Window Watchdog Timer Status Register */
} WWDT_Regs;
/*@}*/ /* end of group WWDT */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* WWDT Register Control Bits
******************************************************************************/
/* WWDT_IIDX Bits */
/* WWDT_IIDX[STAT] Bits */
#define WWDT_IIDX_STAT_OFS (0) /* !< STAT Offset */
#define WWDT_IIDX_STAT_MASK ((uint32_t)0x0000001FU) /* !< Module Interrupt Vector Value.
This register provides the highest
priority interrupt index. A read
clears the corresponding interrupt
flag in RIS and MISC. */
#define WWDT_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define WWDT_IIDX_STAT_INTTIM ((uint32_t)0x00000001U) /* !< Interval Timer Interrupt; Interrupt
Flag: INTTIM; Interrupt Priority:
Highest */
/* WWDT_IMASK Bits */
/* WWDT_IMASK[INTTIM] Bits */
#define WWDT_IMASK_INTTIM_OFS (0) /* !< INTTIM Offset */
#define WWDT_IMASK_INTTIM_MASK ((uint32_t)0x00000001U) /* !< Interval Timer Interrupt. */
#define WWDT_IMASK_INTTIM_CLR ((uint32_t)0x00000000U) /* !< Clear Interrupt Mask */
#define WWDT_IMASK_INTTIM_SET ((uint32_t)0x00000001U) /* !< Set Interrupt Mask */
/* WWDT_RIS Bits */
/* WWDT_RIS[INTTIM] Bits */
#define WWDT_RIS_INTTIM_OFS (0) /* !< INTTIM Offset */
#define WWDT_RIS_INTTIM_MASK ((uint32_t)0x00000001U) /* !< Interval Timer Interrupt. */
#define WWDT_RIS_INTTIM_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */
#define WWDT_RIS_INTTIM_SET ((uint32_t)0x00000001U) /* !< Interrupt occurred */
/* WWDT_MIS Bits */
/* WWDT_MIS[INTTIM] Bits */
#define WWDT_MIS_INTTIM_OFS (0) /* !< INTTIM Offset */
#define WWDT_MIS_INTTIM_MASK ((uint32_t)0x00000001U) /* !< Interval Timer Interrupt. */
#define WWDT_MIS_INTTIM_CLR ((uint32_t)0x00000000U) /* !< Interrupt did not occur */
#define WWDT_MIS_INTTIM_SET ((uint32_t)0x00000001U) /* !< Interrupt occurred */
/* WWDT_ISET Bits */
/* WWDT_ISET[INTTIM] Bits */
#define WWDT_ISET_INTTIM_OFS (0) /* !< INTTIM Offset */
#define WWDT_ISET_INTTIM_MASK ((uint32_t)0x00000001U) /* !< Interval Timer Interrupt. */
#define WWDT_ISET_INTTIM_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define WWDT_ISET_INTTIM_SET ((uint32_t)0x00000001U) /* !< Set Interrupt */
/* WWDT_ICLR Bits */
/* WWDT_ICLR[INTTIM] Bits */
#define WWDT_ICLR_INTTIM_OFS (0) /* !< INTTIM Offset */
#define WWDT_ICLR_INTTIM_MASK ((uint32_t)0x00000001U) /* !< Interval Timer Interrupt. */
#define WWDT_ICLR_INTTIM_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define WWDT_ICLR_INTTIM_CLR ((uint32_t)0x00000001U) /* !< Clear Interrupt */
/* WWDT_PWREN Bits */
/* WWDT_PWREN[ENABLE] Bits */
#define WWDT_PWREN_ENABLE_OFS (0) /* !< ENABLE Offset */
#define WWDT_PWREN_ENABLE_MASK ((uint32_t)0x00000001U) /* !< Enable the power Note: For safety
devices the power cannot be disabled
once enabled. */
#define WWDT_PWREN_ENABLE_DISABLE ((uint32_t)0x00000000U) /* !< Disable Power */
#define WWDT_PWREN_ENABLE_ENABLE ((uint32_t)0x00000001U) /* !< Enable Power */
/* WWDT_PWREN[KEY] Bits */
#define WWDT_PWREN_KEY_OFS (24) /* !< KEY Offset */
#define WWDT_PWREN_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow Power State Change */
#define WWDT_PWREN_KEY_UNLOCK_W ((uint32_t)0x26000000U) /* !< KEY to allow write access to this
register */
/* WWDT_RSTCTL Bits */
/* WWDT_RSTCTL[RESETSTKYCLR] Bits */
#define WWDT_RSTCTL_RESETSTKYCLR_OFS (1) /* !< RESETSTKYCLR Offset */
#define WWDT_RSTCTL_RESETSTKYCLR_MASK ((uint32_t)0x00000002U) /* !< Clear [GPRCM.STAT.RESETSTKY] */
#define WWDT_RSTCTL_RESETSTKYCLR_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define WWDT_RSTCTL_RESETSTKYCLR_CLR ((uint32_t)0x00000002U) /* !< Clear reset sticky bit */
/* WWDT_RSTCTL[RESETASSERT] Bits */
#define WWDT_RSTCTL_RESETASSERT_OFS (0) /* !< RESETASSERT Offset */
#define WWDT_RSTCTL_RESETASSERT_MASK ((uint32_t)0x00000001U) /* !< Assert reset to the peripheral
Note: For safety devices a watchdog
reset by software is not possible. */
#define WWDT_RSTCTL_RESETASSERT_NOP ((uint32_t)0x00000000U) /* !< Writing 0 has no effect */
#define WWDT_RSTCTL_RESETASSERT_ASSERT ((uint32_t)0x00000001U) /* !< Assert reset */
/* WWDT_RSTCTL[KEY] Bits */
#define WWDT_RSTCTL_KEY_OFS (24) /* !< KEY Offset */
#define WWDT_RSTCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< Unlock key */
#define WWDT_RSTCTL_KEY_UNLOCK_W ((uint32_t)0xB1000000U) /* !< KEY to allow write access to this
register */
/* WWDT_STAT Bits */
/* WWDT_STAT[RESETSTKY] Bits */
#define WWDT_STAT_RESETSTKY_OFS (16) /* !< RESETSTKY Offset */
#define WWDT_STAT_RESETSTKY_MASK ((uint32_t)0x00010000U) /* !< This bit indicates, if the
peripheral was reset, since this bit
was cleared by RESETSTKYCLR in the
RSTCTL register */
#define WWDT_STAT_RESETSTKY_NORES ((uint32_t)0x00000000U) /* !< The peripheral has not been reset
since this bit was last cleared by
RESETSTKYCLR in the RSTCTL register */
#define WWDT_STAT_RESETSTKY_RESET ((uint32_t)0x00010000U) /* !< The peripheral was reset since the
last bit clear */
/* WWDT_PDBGCTL Bits */
/* WWDT_PDBGCTL[FREE] Bits */
#define WWDT_PDBGCTL_FREE_OFS (0) /* !< FREE Offset */
#define WWDT_PDBGCTL_FREE_MASK ((uint32_t)0x00000001U) /* !< Free run control */
#define WWDT_PDBGCTL_FREE_STOP ((uint32_t)0x00000000U) /* !< The peripheral freezes
functionality while the Core Halted
input is asserted and resumes when it
is deasserted. */
#define WWDT_PDBGCTL_FREE_RUN ((uint32_t)0x00000001U) /* !< The peripheral ignores the state of
the Core Halted input */
/* WWDT_EVT_MODE Bits */
/* WWDT_EVT_MODE[INT0_CFG] Bits */
#define WWDT_EVT_MODE_INT0_CFG_OFS (0) /* !< INT0_CFG Offset */
#define WWDT_EVT_MODE_INT0_CFG_MASK ((uint32_t)0x00000003U) /* !< Event line mode select for event
corresponding to
[IPSTANDARD.CPU_INT][0] */
#define WWDT_EVT_MODE_INT0_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
disabled. */
#define WWDT_EVT_MODE_INT0_CFG_SOFTWARE ((uint32_t)0x00000001U) /* !< The interrupt or event line is in
software mode. Software must clear
the RIS. */
#define WWDT_EVT_MODE_INT0_CFG_HARDWARE ((uint32_t)0x00000002U) /* !< The interrupt or event line is in
hardware mode. The hardware (another
module) clears automatically the
associated RIS flag. */
/* WWDT_DESC Bits */
/* WWDT_DESC[MINREV] Bits */
#define WWDT_DESC_MINREV_OFS (0) /* !< MINREV Offset */
#define WWDT_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */
#define WWDT_DESC_MINREV_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define WWDT_DESC_MINREV_MAXIMUM ((uint32_t)0x0000000FU) /* !< Highest possible value */
/* WWDT_DESC[MAJREV] Bits */
#define WWDT_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */
#define WWDT_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */
#define WWDT_DESC_MAJREV_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define WWDT_DESC_MAJREV_MAXIMUM ((uint32_t)0x000000F0U) /* !< Highest possible value */
/* WWDT_DESC[INSTNUM] Bits */
#define WWDT_DESC_INSTNUM_OFS (8) /* !< INSTNUM Offset */
#define WWDT_DESC_INSTNUM_MASK ((uint32_t)0x00000F00U) /* !< Instance Number within the device.
This will be a parameter to the RTL
for modules that can have multiple
instances */
#define WWDT_DESC_INSTNUM_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define WWDT_DESC_INSTNUM_MAXIMUM ((uint32_t)0x00000F00U) /* !< Highest possible value */
/* WWDT_DESC[FEATUREVER] Bits */
#define WWDT_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */
#define WWDT_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module
*instance* */
#define WWDT_DESC_FEATUREVER_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define WWDT_DESC_FEATUREVER_MAXIMUM ((uint32_t)0x0000F000U) /* !< Highest possible value */
/* WWDT_DESC[MODULEID] Bits */
#define WWDT_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */
#define WWDT_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module identification contains a
unique peripheral identification
number. The assignments are
maintained in a central database for
all of the platform modules to ensure
uniqueness. */
#define WWDT_DESC_MODULEID_MINIMUM ((uint32_t)0x00000000U) /* !< Smallest value */
#define WWDT_DESC_MODULEID_MAXIMUM ((uint32_t)0xFFFF0000U) /* !< Highest possible value */
/* WWDT_WWDTCTL0 Bits */
/* WWDT_WWDTCTL0[PER] Bits */
#define WWDT_WWDTCTL0_PER_OFS (4) /* !< PER Offset */
#define WWDT_WWDTCTL0_PER_MASK ((uint32_t)0x00000070U) /* !< Timer Period of the WWDT. These
bits select the total watchdog timer
count. */
#define WWDT_WWDTCTL0_PER_EN_25 ((uint32_t)0x00000000U) /* !< Total timer count is 2^25 */
#define WWDT_WWDTCTL0_PER_EN_21 ((uint32_t)0x00000010U) /* !< Total timer count is 2^21 */
#define WWDT_WWDTCTL0_PER_EN_18 ((uint32_t)0x00000020U) /* !< Total timer count is 2^18 */
#define WWDT_WWDTCTL0_PER_EN_15 ((uint32_t)0x00000030U) /* !< Total timer count is 2^15 */
#define WWDT_WWDTCTL0_PER_EN_12 ((uint32_t)0x00000040U) /* !< Total timer count is 2^12 (default) */
#define WWDT_WWDTCTL0_PER_EN_10 ((uint32_t)0x00000050U) /* !< Total timer count is 2^10 */
#define WWDT_WWDTCTL0_PER_EN_8 ((uint32_t)0x00000060U) /* !< Total timer count is 2^8 */
#define WWDT_WWDTCTL0_PER_EN_6 ((uint32_t)0x00000070U) /* !< Total timer count is 2^6 */
/* WWDT_WWDTCTL0[WINDOW0] Bits */
#define WWDT_WWDTCTL0_WINDOW0_OFS (8) /* !< WINDOW0 Offset */
#define WWDT_WWDTCTL0_WINDOW0_MASK ((uint32_t)0x00000700U) /* !< Closed window period in percentage
of the timer interval.
WWDTCTL1.WINSEL determines the active
window setting (WWDTCTL0.WINDOW0 or
WWDTCTL0.WINDOW1). */
#define WWDT_WWDTCTL0_WINDOW0_SIZE_0 ((uint32_t)0x00000000U) /* !< 0% (No closed Window) */
#define WWDT_WWDTCTL0_WINDOW0_SIZE_12 ((uint32_t)0x00000100U) /* !< 12.50% of the total timer period is
closed window */
#define WWDT_WWDTCTL0_WINDOW0_SIZE_18 ((uint32_t)0x00000200U) /* !< 18.75% of the total timer period is
closed window */
#define WWDT_WWDTCTL0_WINDOW0_SIZE_25 ((uint32_t)0x00000300U) /* !< 25% of the total timer period is
closed window */
#define WWDT_WWDTCTL0_WINDOW0_SIZE_50 ((uint32_t)0x00000400U) /* !< 50% of the total timer period is
closed window */
#define WWDT_WWDTCTL0_WINDOW0_SIZE_75 ((uint32_t)0x00000500U) /* !< 75% of the total timer period is
closed window */
#define WWDT_WWDTCTL0_WINDOW0_SIZE_81 ((uint32_t)0x00000600U) /* !< 81.25% of the total timer period is
closed window */
#define WWDT_WWDTCTL0_WINDOW0_SIZE_87 ((uint32_t)0x00000700U) /* !< 87.50% of the total timer period is
closed window */
/* WWDT_WWDTCTL0[MODE] Bits */
#define WWDT_WWDTCTL0_MODE_OFS (16) /* !< MODE Offset */
#define WWDT_WWDTCTL0_MODE_MASK ((uint32_t)0x00010000U) /* !< Window Watchdog Timer Mode */
#define WWDT_WWDTCTL0_MODE_WINDOW ((uint32_t)0x00000000U) /* !< Window Watchdog Timer Mode. The
WWDT will generate a error signal to
the ESM when following conditions
occur: - Timer Expiration (Timeout) -
Reset WWDT during the active window
closed period - Keyword violation */
#define WWDT_WWDTCTL0_MODE_INTERVAL ((uint32_t)0x00010000U) /* !< Interval Timer Mode. The WWDT acts
as an interval timer. It generates an
interrupt on timeout. */
/* WWDT_WWDTCTL0[STISM] Bits */
#define WWDT_WWDTCTL0_STISM_OFS (17) /* !< STISM Offset */
#define WWDT_WWDTCTL0_STISM_MASK ((uint32_t)0x00020000U) /* !< Stop In Sleep Mode. The
functionality of this bit requires
that POLICY.HWCEN = 0. If
POLICY.HWCEN = 1 the WWDT resets
during sleep and needs
re-configuration. Note: This bit has
no effect for the global Window
Watchdog as Sleep Mode is not
supported. */
#define WWDT_WWDTCTL0_STISM_CONT ((uint32_t)0x00000000U) /* !< The WWDT continues to function in
Sleep mode. */
#define WWDT_WWDTCTL0_STISM_STOP ((uint32_t)0x00020000U) /* !< The WWDT stops in Sleep mode and
resumes where it was stopped after
wakeup. */
/* WWDT_WWDTCTL0[KEY] Bits */
#define WWDT_WWDTCTL0_KEY_OFS (24) /* !< KEY Offset */
#define WWDT_WWDTCTL0_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow write access to this
register. Writing to this register
with an incorrect key activates the
WWDT error signal to the ESM. Read as
0. */
#define WWDT_WWDTCTL0_KEY_UNLOCK_W ((uint32_t)0xC9000000U) /* !< KEY to allow write access to this
register */
/* WWDT_WWDTCTL0[CLKDIV] Bits */
#define WWDT_WWDTCTL0_CLKDIV_OFS (0) /* !< CLKDIV Offset */
#define WWDT_WWDTCTL0_CLKDIV_MASK ((uint32_t)0x00000007U) /* !< Module Clock Divider, Divide the
clock source by CLKDIV+1. Divider
values from /1 to /8 are possible.
The clock divider is currently 4
bits. Bit 4 has no effect and should
always be written with 0. */
#define WWDT_WWDTCTL0_CLKDIV_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum value */
#define WWDT_WWDTCTL0_CLKDIV_MAXIMUM ((uint32_t)0x00000007U) /* !< Maximum value */
/* WWDT_WWDTCTL0[WINDOW1] Bits */
#define WWDT_WWDTCTL0_WINDOW1_OFS (12) /* !< WINDOW1 Offset */
#define WWDT_WWDTCTL0_WINDOW1_MASK ((uint32_t)0x00007000U) /* !< Closed window period in percentage
of the timer interval.
WWDTCTL1.WINSEL determines the active
window setting (WWDTCTL0.WINDOW0 or
WWDTCTL0.WINDOW1). */
#define WWDT_WWDTCTL0_WINDOW1_SIZE_0 ((uint32_t)0x00000000U) /* !< 0% (No closed Window) */
#define WWDT_WWDTCTL0_WINDOW1_SIZE_12 ((uint32_t)0x00001000U) /* !< 12.50% of the total timer period is
closed window */
#define WWDT_WWDTCTL0_WINDOW1_SIZE_18 ((uint32_t)0x00002000U) /* !< 18.75% of the total timer period is
closed window */
#define WWDT_WWDTCTL0_WINDOW1_SIZE_25 ((uint32_t)0x00003000U) /* !< 25% of the total timer period is
closed window */
#define WWDT_WWDTCTL0_WINDOW1_SIZE_50 ((uint32_t)0x00004000U) /* !< 50% of the total timer period is
closed window */
#define WWDT_WWDTCTL0_WINDOW1_SIZE_75 ((uint32_t)0x00005000U) /* !< 75% of the total timer period is
closed window */
#define WWDT_WWDTCTL0_WINDOW1_SIZE_81 ((uint32_t)0x00006000U) /* !< 81.25% of the total timer period is
closed window */
#define WWDT_WWDTCTL0_WINDOW1_SIZE_87 ((uint32_t)0x00007000U) /* !< 87.50% of the total timer period is
closed window */
/* WWDT_WWDTCTL1 Bits */
/* WWDT_WWDTCTL1[KEY] Bits */
#define WWDT_WWDTCTL1_KEY_OFS (24) /* !< KEY Offset */
#define WWDT_WWDTCTL1_KEY_MASK ((uint32_t)0xFF000000U) /* !< KEY to allow write access to this
register. Writing to this register
with an incorrect key activates the
WWDT error signal to the ESM. Read as
0. */
#define WWDT_WWDTCTL1_KEY_UNLOCK_W ((uint32_t)0xBE000000U) /* !< KEY to allow write access to this
register */
/* WWDT_WWDTCTL1[WINSEL] Bits */
#define WWDT_WWDTCTL1_WINSEL_OFS (0) /* !< WINSEL Offset */
#define WWDT_WWDTCTL1_WINSEL_MASK ((uint32_t)0x00000001U) /* !< Close Window Select */
#define WWDT_WWDTCTL1_WINSEL_WIN0 ((uint32_t)0x00000000U) /* !< In window mode field WINDOW0 of
WDDTCTL0 defines the closed window
size. */
#define WWDT_WWDTCTL1_WINSEL_WIN1 ((uint32_t)0x00000001U) /* !< In window mode field WINDOW1 of
WDDTCTL0 defines the closed window
size. */
/* WWDT_WWDTCNTRST Bits */
/* WWDT_WWDTCNTRST[RESTART] Bits */
#define WWDT_WWDTCNTRST_RESTART_OFS (0) /* !< RESTART Offset */
#define WWDT_WWDTCNTRST_RESTART_MASK ((uint32_t)0xFFFFFFFFU) /* !< Window Watchdog Timer Counter
Restart Writing 00A7h to this
register restarts the WWDT Counter.
Writing any other value causes an
error generation to the ESM. Read as
0. */
#define WWDT_WWDTCNTRST_RESTART_MINIMUM ((uint32_t)0x00000000U) /* !< Minimum value */
#define WWDT_WWDTCNTRST_RESTART_MAXIMUM ((uint32_t)0xFFFFFFFFU) /* !< Maximum value */
/* WWDT_WWDTSTAT Bits */
/* WWDT_WWDTSTAT[RUN] Bits */
#define WWDT_WWDTSTAT_RUN_OFS (0) /* !< RUN Offset */
#define WWDT_WWDTSTAT_RUN_MASK ((uint32_t)0x00000001U) /* !< Watchdog running status flag. */
#define WWDT_WWDTSTAT_RUN_OFF ((uint32_t)0x00000000U) /* !< Watchdog counter stopped. */
#define WWDT_WWDTSTAT_RUN_ON ((uint32_t)0x00000001U) /* !< Watchdog running. */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_hw_wwdt__include */
libraries/sdk/ti/devices/msp/peripherals/m0p/hw_cpuss.h
+268
View File
@@ -0,0 +1,268 @@
/*****************************************************************************
Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_m0p_hw_cpuss__include
#define ti_devices_msp_peripherals_m0p_hw_cpuss__include
/* Filename: hw_cpuss.h */
/* Revised: 2023-04-30 21:36:20 */
/* Revision: ec4f3de051dafa6135b4867f4e796eec5f1a339b */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* CPUSS Registers
******************************************************************************/
#define CPUSS_INT_GROUP_OFS ((uint32_t)0x00001100U)
/** @addtogroup CPUSS_INT_GROUP
@{
*/
typedef struct {
__I uint32_t IIDX; /* !< (@ 0x00001100) Interrupt index */
uint32_t RESERVED0;
__I uint32_t IMASK; /* !< (@ 0x00001108) Interrupt mask */
uint32_t RESERVED1;
__I uint32_t RIS; /* !< (@ 0x00001110) Raw interrupt status */
uint32_t RESERVED2;
__I uint32_t MIS; /* !< (@ 0x00001118) Masked interrupt status */
uint32_t RESERVED3;
__O uint32_t ISET; /* !< (@ 0x00001120) Interrupt set */
uint32_t RESERVED4;
__O uint32_t ICLR; /* !< (@ 0x00001128) Interrupt clear */
uint32_t RESERVED5;
} CPUSS_INT_GROUP_Regs;
/*@}*/ /* end of group CPUSS_INT_GROUP */
/** @addtogroup CPUSS
@{
*/
typedef struct {
uint32_t RESERVED0[1080];
__I uint32_t EVT_MODE; /* !< (@ 0x000010E0) Event Mode */
uint32_t RESERVED1[6];
__I uint32_t DESC; /* !< (@ 0x000010FC) Module Description */
CPUSS_INT_GROUP_Regs INT_GROUP[5]; /* !< (@ 0x00001100) */
uint32_t RESERVED2[68];
__IO uint32_t CTL; /* !< (@ 0x00001300) Prefetch/Cache control */
} CPUSS_Regs;
/*@}*/ /* end of group CPUSS */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* CPUSS Register Control Bits
******************************************************************************/
/* CPUSS_INT_GROUP_IIDX Bits */
/* CPUSS_INT_GROUP_IIDX[STAT] Bits */
#define CPUSS_INT_GROUP_IIDX_STAT_OFS (0) /* !< STAT Offset */
#define CPUSS_INT_GROUP_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */
#define CPUSS_INT_GROUP_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No pending interrupt */
#define CPUSS_INT_GROUP_IIDX_STAT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
#define CPUSS_INT_GROUP_IIDX_STAT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
#define CPUSS_INT_GROUP_IIDX_STAT_INT2 ((uint32_t)0x00000003U) /* !< Interrupt 2 */
#define CPUSS_INT_GROUP_IIDX_STAT_INT3 ((uint32_t)0x00000004U) /* !< Interrupt 3 */
#define CPUSS_INT_GROUP_IIDX_STAT_INT4 ((uint32_t)0x00000005U) /* !< Interrupt 4 */
#define CPUSS_INT_GROUP_IIDX_STAT_INT5 ((uint32_t)0x00000006U) /* !< Interrupt 5 */
#define CPUSS_INT_GROUP_IIDX_STAT_INT6 ((uint32_t)0x00000007U) /* !< Interrupt 6 */
#define CPUSS_INT_GROUP_IIDX_STAT_INT7 ((uint32_t)0x00000008U) /* !< Interrupt 7 */
/* CPUSS_INT_GROUP_IMASK Bits */
/* CPUSS_INT_GROUP_IMASK[INT] Bits */
#define CPUSS_INT_GROUP_IMASK_INT_OFS (0) /* !< INT Offset */
#define CPUSS_INT_GROUP_IMASK_INT_MASK ((uint32_t)0x000000FFU) /* !< Masks the corresponding interrupt */
#define CPUSS_INT_GROUP_IMASK_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
#define CPUSS_INT_GROUP_IMASK_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
#define CPUSS_INT_GROUP_IMASK_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
#define CPUSS_INT_GROUP_IMASK_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
#define CPUSS_INT_GROUP_IMASK_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
#define CPUSS_INT_GROUP_IMASK_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
#define CPUSS_INT_GROUP_IMASK_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
#define CPUSS_INT_GROUP_IMASK_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
/* CPUSS_INT_GROUP_RIS Bits */
/* CPUSS_INT_GROUP_RIS[INT] Bits */
#define CPUSS_INT_GROUP_RIS_INT_OFS (0) /* !< INT Offset */
#define CPUSS_INT_GROUP_RIS_INT_MASK ((uint32_t)0x000000FFU) /* !< Raw interrupt status for INT */
#define CPUSS_INT_GROUP_RIS_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
#define CPUSS_INT_GROUP_RIS_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
#define CPUSS_INT_GROUP_RIS_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
#define CPUSS_INT_GROUP_RIS_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
#define CPUSS_INT_GROUP_RIS_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
#define CPUSS_INT_GROUP_RIS_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
#define CPUSS_INT_GROUP_RIS_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
#define CPUSS_INT_GROUP_RIS_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
/* CPUSS_INT_GROUP_MIS Bits */
/* CPUSS_INT_GROUP_MIS[INT] Bits */
#define CPUSS_INT_GROUP_MIS_INT_OFS (0) /* !< INT Offset */
#define CPUSS_INT_GROUP_MIS_INT_MASK ((uint32_t)0x000000FFU) /* !< Masked interrupt status for INT0 */
#define CPUSS_INT_GROUP_MIS_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
#define CPUSS_INT_GROUP_MIS_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
#define CPUSS_INT_GROUP_MIS_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
#define CPUSS_INT_GROUP_MIS_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
#define CPUSS_INT_GROUP_MIS_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
#define CPUSS_INT_GROUP_MIS_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
#define CPUSS_INT_GROUP_MIS_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
#define CPUSS_INT_GROUP_MIS_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
/* CPUSS_INT_GROUP_ISET Bits */
/* CPUSS_INT_GROUP_ISET[INT] Bits */
#define CPUSS_INT_GROUP_ISET_INT_OFS (0) /* !< INT Offset */
#define CPUSS_INT_GROUP_ISET_INT_MASK ((uint32_t)0x000000FFU) /* !< Sets INT in RIS register */
#define CPUSS_INT_GROUP_ISET_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
#define CPUSS_INT_GROUP_ISET_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
#define CPUSS_INT_GROUP_ISET_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
#define CPUSS_INT_GROUP_ISET_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
#define CPUSS_INT_GROUP_ISET_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
#define CPUSS_INT_GROUP_ISET_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
#define CPUSS_INT_GROUP_ISET_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
#define CPUSS_INT_GROUP_ISET_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
/* CPUSS_INT_GROUP_ICLR Bits */
/* CPUSS_INT_GROUP_ICLR[INT] Bits */
#define CPUSS_INT_GROUP_ICLR_INT_OFS (0) /* !< INT Offset */
#define CPUSS_INT_GROUP_ICLR_INT_MASK ((uint32_t)0x000000FFU) /* !< Clears INT in RIS register */
#define CPUSS_INT_GROUP_ICLR_INT_INT0 ((uint32_t)0x00000001U) /* !< Interrupt 0 */
#define CPUSS_INT_GROUP_ICLR_INT_INT1 ((uint32_t)0x00000002U) /* !< Interrupt 1 */
#define CPUSS_INT_GROUP_ICLR_INT_INT2 ((uint32_t)0x00000004U) /* !< Interrupt 2 */
#define CPUSS_INT_GROUP_ICLR_INT_INT3 ((uint32_t)0x00000008U) /* !< Interrupt 3 */
#define CPUSS_INT_GROUP_ICLR_INT_INT4 ((uint32_t)0x00000010U) /* !< Interrupt 4 */
#define CPUSS_INT_GROUP_ICLR_INT_INT5 ((uint32_t)0x00000020U) /* !< Interrupt 5 */
#define CPUSS_INT_GROUP_ICLR_INT_INT6 ((uint32_t)0x00000040U) /* !< Interrupt 6 */
#define CPUSS_INT_GROUP_ICLR_INT_INT7 ((uint32_t)0x00000080U) /* !< Interrupt 7 */
/* CPUSS_EVT_MODE Bits */
/* CPUSS_EVT_MODE[INT_CFG] Bits */
#define CPUSS_EVT_MODE_INT_CFG_OFS (0) /* !< INT_CFG Offset */
#define CPUSS_EVT_MODE_INT_CFG_MASK ((uint32_t)0x00000003U) /* !< Event line mode select */
#define CPUSS_EVT_MODE_INT_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
disabled. */
#define CPUSS_EVT_MODE_INT_CFG_SOFTWARE ((uint32_t)0x00000001U) /* !< Event handled by software. Software
must clear the associated RIS flag. */
#define CPUSS_EVT_MODE_INT_CFG_HARDWARE ((uint32_t)0x00000002U) /* !< Event handled by hardware. The
hardware (another module) clears
automatically the associated RIS
flag. */
/* CPUSS_DESC Bits */
/* CPUSS_DESC[MINREV] Bits */
#define CPUSS_DESC_MINREV_OFS (0) /* !< MINREV Offset */
#define CPUSS_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */
/* CPUSS_DESC[MAJREV] Bits */
#define CPUSS_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */
#define CPUSS_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */
/* CPUSS_DESC[FEATUREVER] Bits */
#define CPUSS_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */
#define CPUSS_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module
*instance* */
/* CPUSS_DESC[MODULEID] Bits */
#define CPUSS_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */
#define CPUSS_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module identification contains a
unique peripheral identification
number. The assignments are
maintained in a central database for
all of the platform modules to ensure
uniqueness. */
/* CPUSS_CTL Bits */
/* CPUSS_CTL[PREFETCH] Bits */
#define CPUSS_CTL_PREFETCH_OFS (0) /* !< PREFETCH Offset */
#define CPUSS_CTL_PREFETCH_MASK ((uint32_t)0x00000001U) /* !< Used to enable/disable instruction
prefetch to Flash. */
#define CPUSS_CTL_PREFETCH_DISABLE ((uint32_t)0x00000000U) /* !< Disable instruction prefetch. */
#define CPUSS_CTL_PREFETCH_ENABLE ((uint32_t)0x00000001U) /* !< Enable instruction prefetch. */
/* CPUSS_CTL[ICACHE] Bits */
#define CPUSS_CTL_ICACHE_OFS (1) /* !< ICACHE Offset */
#define CPUSS_CTL_ICACHE_MASK ((uint32_t)0x00000002U) /* !< Used to enable/disable Instruction
caching on flash access. */
#define CPUSS_CTL_ICACHE_DISABLE ((uint32_t)0x00000000U) /* !< Disable instruction caching. */
#define CPUSS_CTL_ICACHE_ENABLE ((uint32_t)0x00000002U) /* !< Enable instruction caching. */
/* CPUSS_CTL[LITEN] Bits */
#define CPUSS_CTL_LITEN_OFS (2) /* !< LITEN Offset */
#define CPUSS_CTL_LITEN_MASK ((uint32_t)0x00000004U) /* !< Literal caching and prefetch
enable. This bit is a subset of
ICACHE/PREFETCH bit i.e. literal
caching or literal prefetching will
only happen if ICACHE or PREFETCH
bits have been set respectively When
enabled, the cache and prefetcher
structures inside CPUSS will cache
and prefetch literals When disabled,
the cache and prefetcher structures
inside CPUSS will not cache and
prefetch literals */
#define CPUSS_CTL_LITEN_DISABLE ((uint32_t)0x00000000U) /* !< Literal caching disabled */
#define CPUSS_CTL_LITEN_ENABLE ((uint32_t)0x00000004U) /* !< Literal caching enabled */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_m0p_hw_cpuss__include */
libraries/sdk/ti/devices/msp/peripherals/m0p/hw_debugss.h
+460
View File
@@ -0,0 +1,460 @@
/*****************************************************************************
Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_m0p_hw_debugss__include
#define ti_devices_msp_peripherals_m0p_hw_debugss__include
/* Filename: hw_debugss.h */
/* Revised: 2023-05-10 21:16:53 */
/* Revision: 2f29710894b537f621c6ebedd563efb234664827 */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* DEBUGSS Registers
******************************************************************************/
#define DEBUGSS_CPU_INT_OFS ((uint32_t)0x00001020U)
/** @addtogroup DEBUGSS_CPU_INT
@{
*/
typedef struct {
__I uint32_t IIDX; /* !< (@ 0x00001020) Interrupt index */
uint32_t RESERVED0;
__IO uint32_t IMASK; /* !< (@ 0x00001028) Interrupt mask */
uint32_t RESERVED1;
__I uint32_t RIS; /* !< (@ 0x00001030) Raw interrupt status */
uint32_t RESERVED2;
__I uint32_t MIS; /* !< (@ 0x00001038) Masked interrupt status */
uint32_t RESERVED3;
__O uint32_t ISET; /* !< (@ 0x00001040) Interrupt set */
uint32_t RESERVED4;
__O uint32_t ICLR; /* !< (@ 0x00001048) Interrupt clear */
} DEBUGSS_CPU_INT_Regs;
/*@}*/ /* end of group DEBUGSS_CPU_INT */
/** @addtogroup DEBUGSS
@{
*/
typedef struct {
uint32_t RESERVED0[1032];
DEBUGSS_CPU_INT_Regs CPU_INT; /* !< (@ 0x00001020) */
uint32_t RESERVED1[37];
__I uint32_t EVT_MODE; /* !< (@ 0x000010E0) Event Mode */
uint32_t RESERVED2[6];
__I uint32_t DESC; /* !< (@ 0x000010FC) Module Description */
__I uint32_t TXD; /* !< (@ 0x00001100) Transmit data register */
__I uint32_t TXCTL; /* !< (@ 0x00001104) Transmit control register */
__IO uint32_t RXD; /* !< (@ 0x00001108) Receive data register */
__IO uint32_t RXCTL; /* !< (@ 0x0000110C) Receive control register */
uint32_t RESERVED3[60];
__I uint32_t SPECIAL_AUTH; /* !< (@ 0x00001200) Special enable authorization register */
uint32_t RESERVED4[3];
__I uint32_t APP_AUTH; /* !< (@ 0x00001210) Application CPU0 authorization register */
} DEBUGSS_Regs;
/*@}*/ /* end of group DEBUGSS */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* DEBUGSS Register Control Bits
******************************************************************************/
/* DEBUGSS_IIDX Bits */
/* DEBUGSS_IIDX[STAT] Bits */
#define DEBUGSS_IIDX_STAT_OFS (0) /* !< STAT Offset */
#define DEBUGSS_IIDX_STAT_MASK ((uint32_t)0x000000FFU) /* !< Interrupt index status */
#define DEBUGSS_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No pending interrupt request */
#define DEBUGSS_IIDX_STAT_TXIFG ((uint32_t)0x00000001U) /* !< TX interrupt */
#define DEBUGSS_IIDX_STAT_RXIFG ((uint32_t)0x00000002U) /* !< RX interrupt */
#define DEBUGSS_IIDX_STAT_PWRUP ((uint32_t)0x00000003U) /* !< Power-up interrupt. A debug session
has started. */
#define DEBUGSS_IIDX_STAT_PWRDWN ((uint32_t)0x00000004U) /* !< Power-up interrupt. A debug session
has started. */
/* DEBUGSS_IMASK Bits */
/* DEBUGSS_IMASK[TXIFG] Bits */
#define DEBUGSS_IMASK_TXIFG_OFS (0) /* !< TXIFG Offset */
#define DEBUGSS_IMASK_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Masks TXIFG in MIS register */
#define DEBUGSS_IMASK_TXIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define DEBUGSS_IMASK_TXIFG_SET ((uint32_t)0x00000001U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* DEBUGSS_IMASK[RXIFG] Bits */
#define DEBUGSS_IMASK_RXIFG_OFS (1) /* !< RXIFG Offset */
#define DEBUGSS_IMASK_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Masks RXIFG in MIS register */
#define DEBUGSS_IMASK_RXIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define DEBUGSS_IMASK_RXIFG_SET ((uint32_t)0x00000002U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* DEBUGSS_IMASK[PWRUPIFG] Bits */
#define DEBUGSS_IMASK_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
#define DEBUGSS_IMASK_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Masks PWRUPIFG in MIS register */
#define DEBUGSS_IMASK_PWRUPIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define DEBUGSS_IMASK_PWRUPIFG_SET ((uint32_t)0x00000004U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* DEBUGSS_IMASK[PWRDWNIFG] Bits */
#define DEBUGSS_IMASK_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
#define DEBUGSS_IMASK_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Masks PWRDWNIFG in MIS register */
#define DEBUGSS_IMASK_PWRDWNIFG_CLR ((uint32_t)0x00000000U) /* !< Interrupt is masked out */
#define DEBUGSS_IMASK_PWRDWNIFG_SET ((uint32_t)0x00000008U) /* !< Interrupt will request an interrupt
service routine and corresponding bit
in MIS will be set */
/* DEBUGSS_RIS Bits */
/* DEBUGSS_RIS[TXIFG] Bits */
#define DEBUGSS_RIS_TXIFG_OFS (0) /* !< TXIFG Offset */
#define DEBUGSS_RIS_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Raw interrupt status for TXIFG */
#define DEBUGSS_RIS_TXIFG_CLR ((uint32_t)0x00000000U) /* !< TXIFG did not occur */
#define DEBUGSS_RIS_TXIFG_SET ((uint32_t)0x00000001U) /* !< TXIFG occurred */
/* DEBUGSS_RIS[RXIFG] Bits */
#define DEBUGSS_RIS_RXIFG_OFS (1) /* !< RXIFG Offset */
#define DEBUGSS_RIS_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Raw interrupt status for RXIFG */
#define DEBUGSS_RIS_RXIFG_CLR ((uint32_t)0x00000000U) /* !< RXIFG did not occur */
#define DEBUGSS_RIS_RXIFG_SET ((uint32_t)0x00000002U) /* !< RXIFG occurred */
/* DEBUGSS_RIS[PWRUPIFG] Bits */
#define DEBUGSS_RIS_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
#define DEBUGSS_RIS_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Raw interrupt status for PWRUPIFG */
#define DEBUGSS_RIS_PWRUPIFG_CLR ((uint32_t)0x00000000U) /* !< PWRUPIFG did not occur */
#define DEBUGSS_RIS_PWRUPIFG_SET ((uint32_t)0x00000004U) /* !< PWRUPIFG occurred */
/* DEBUGSS_RIS[PWRDWNIFG] Bits */
#define DEBUGSS_RIS_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
#define DEBUGSS_RIS_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Raw interrupt status for PWRDWNIFG */
#define DEBUGSS_RIS_PWRDWNIFG_CLR ((uint32_t)0x00000000U) /* !< PWRUPIFG did not occur */
#define DEBUGSS_RIS_PWRDWNIFG_SET ((uint32_t)0x00000008U) /* !< PWRUPIFG occurred */
/* DEBUGSS_MIS Bits */
/* DEBUGSS_MIS[TXIFG] Bits */
#define DEBUGSS_MIS_TXIFG_OFS (0) /* !< TXIFG Offset */
#define DEBUGSS_MIS_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Masked interrupt status for TXIFG */
#define DEBUGSS_MIS_TXIFG_CLR ((uint32_t)0x00000000U) /* !< TXIFG did not request an interrupt
service routine */
#define DEBUGSS_MIS_TXIFG_SET ((uint32_t)0x00000001U) /* !< TXIFG requests an interrupt service
routine */
/* DEBUGSS_MIS[RXIFG] Bits */
#define DEBUGSS_MIS_RXIFG_OFS (1) /* !< RXIFG Offset */
#define DEBUGSS_MIS_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Masked interrupt status for RXIFG */
#define DEBUGSS_MIS_RXIFG_CLR ((uint32_t)0x00000000U) /* !< RXIFG did not request an interrupt
service routine */
#define DEBUGSS_MIS_RXIFG_SET ((uint32_t)0x00000002U) /* !< RXIFG requests an interrupt service
routine */
/* DEBUGSS_MIS[PWRUPIFG] Bits */
#define DEBUGSS_MIS_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
#define DEBUGSS_MIS_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Masked interrupt status for
PWRUPIFG */
#define DEBUGSS_MIS_PWRUPIFG_CLR ((uint32_t)0x00000000U) /* !< PWRUPIFG did not request an
interrupt service routine */
#define DEBUGSS_MIS_PWRUPIFG_SET ((uint32_t)0x00000004U) /* !< PWRUPIFG requests an interrupt
service routine */
/* DEBUGSS_MIS[PWRDWNIFG] Bits */
#define DEBUGSS_MIS_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
#define DEBUGSS_MIS_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Masked interrupt status for
PWRDWNIFG */
#define DEBUGSS_MIS_PWRDWNIFG_CLR ((uint32_t)0x00000000U) /* !< PWRUPIFG did not request an
interrupt service routine */
#define DEBUGSS_MIS_PWRDWNIFG_SET ((uint32_t)0x00000008U) /* !< PWRUPIFG requests an interrupt
service routine */
/* DEBUGSS_ISET Bits */
/* DEBUGSS_ISET[TXIFG] Bits */
#define DEBUGSS_ISET_TXIFG_OFS (0) /* !< TXIFG Offset */
#define DEBUGSS_ISET_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Sets TXIFG in RIS register */
#define DEBUGSS_ISET_TXIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ISET_TXIFG_SET ((uint32_t)0x00000001U) /* !< RIS bit corresponding to TXIFG is
set */
/* DEBUGSS_ISET[RXIFG] Bits */
#define DEBUGSS_ISET_RXIFG_OFS (1) /* !< RXIFG Offset */
#define DEBUGSS_ISET_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Sets RXIFG in RIS register */
#define DEBUGSS_ISET_RXIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ISET_RXIFG_SET ((uint32_t)0x00000002U) /* !< RIS bit corresponding to RXIFG is
set */
/* DEBUGSS_ISET[PWRUPIFG] Bits */
#define DEBUGSS_ISET_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
#define DEBUGSS_ISET_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Sets PWRUPIFG in RIS register */
#define DEBUGSS_ISET_PWRUPIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ISET_PWRUPIFG_SET ((uint32_t)0x00000004U) /* !< RIS bit corresponding to PWRUPIFG
is set */
/* DEBUGSS_ISET[PWRDWNIFG] Bits */
#define DEBUGSS_ISET_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
#define DEBUGSS_ISET_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Sets PWRDWNIFG in RIS register */
#define DEBUGSS_ISET_PWRDWNIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ISET_PWRDWNIFG_SET ((uint32_t)0x00000008U) /* !< RIS bit corresponding to PWRUPIFG
is set */
/* DEBUGSS_ICLR Bits */
/* DEBUGSS_ICLR[TXIFG] Bits */
#define DEBUGSS_ICLR_TXIFG_OFS (0) /* !< TXIFG Offset */
#define DEBUGSS_ICLR_TXIFG_MASK ((uint32_t)0x00000001U) /* !< Clears TXIFG in RIS register */
#define DEBUGSS_ICLR_TXIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ICLR_TXIFG_CLR ((uint32_t)0x00000001U) /* !< RIS bit corresponding to TXIFG is
cleared */
/* DEBUGSS_ICLR[RXIFG] Bits */
#define DEBUGSS_ICLR_RXIFG_OFS (1) /* !< RXIFG Offset */
#define DEBUGSS_ICLR_RXIFG_MASK ((uint32_t)0x00000002U) /* !< Clears RXIFG in RIS register */
#define DEBUGSS_ICLR_RXIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ICLR_RXIFG_CLR ((uint32_t)0x00000002U) /* !< RIS bit corresponding to RXIFG is
cleared */
/* DEBUGSS_ICLR[PWRUPIFG] Bits */
#define DEBUGSS_ICLR_PWRUPIFG_OFS (2) /* !< PWRUPIFG Offset */
#define DEBUGSS_ICLR_PWRUPIFG_MASK ((uint32_t)0x00000004U) /* !< Clears PWRUPIFG in RIS register */
#define DEBUGSS_ICLR_PWRUPIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ICLR_PWRUPIFG_CLR ((uint32_t)0x00000004U) /* !< RIS bit corresponding to PWRUPIFG
is cleared */
/* DEBUGSS_ICLR[PWRDWNIFG] Bits */
#define DEBUGSS_ICLR_PWRDWNIFG_OFS (3) /* !< PWRDWNIFG Offset */
#define DEBUGSS_ICLR_PWRDWNIFG_MASK ((uint32_t)0x00000008U) /* !< Clears PWRDWNIFG in RIS register */
#define DEBUGSS_ICLR_PWRDWNIFG_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing a 0 has no effect */
#define DEBUGSS_ICLR_PWRDWNIFG_CLR ((uint32_t)0x00000008U) /* !< RIS bit corresponding to PWRUPIFG
is cleared */
/* DEBUGSS_EVT_MODE Bits */
/* DEBUGSS_EVT_MODE[INT0_CFG] Bits */
#define DEBUGSS_EVT_MODE_INT0_CFG_OFS (0) /* !< INT0_CFG Offset */
#define DEBUGSS_EVT_MODE_INT0_CFG_MASK ((uint32_t)0x00000003U) /* !< Event line mode select for
peripheral events */
#define DEBUGSS_EVT_MODE_INT0_CFG_DISABLE ((uint32_t)0x00000000U) /* !< The interrupt or event line is
disabled. */
#define DEBUGSS_EVT_MODE_INT0_CFG_SOFTWARE ((uint32_t)0x00000001U) /* !< The interrupt or event line is in
software mode. Software must clear
the RIS. */
#define DEBUGSS_EVT_MODE_INT0_CFG_HARDWARE ((uint32_t)0x00000002U) /* !< The interrupt or event line is in
hardware mode. The hardware (another
module) clears automatically the
associated RIS flag. */
/* DEBUGSS_DESC Bits */
/* DEBUGSS_DESC[MINREV] Bits */
#define DEBUGSS_DESC_MINREV_OFS (0) /* !< MINREV Offset */
#define DEBUGSS_DESC_MINREV_MASK ((uint32_t)0x0000000FU) /* !< Minor rev of the IP */
/* DEBUGSS_DESC[MAJREV] Bits */
#define DEBUGSS_DESC_MAJREV_OFS (4) /* !< MAJREV Offset */
#define DEBUGSS_DESC_MAJREV_MASK ((uint32_t)0x000000F0U) /* !< Major rev of the IP */
/* DEBUGSS_DESC[INSTNUM] Bits */
#define DEBUGSS_DESC_INSTNUM_OFS (8) /* !< INSTNUM Offset */
#define DEBUGSS_DESC_INSTNUM_MASK ((uint32_t)0x00000F00U) /* !< Instance Number within the device.
This will be a parameter to the RTL
for modules that can have multiple
instances */
/* DEBUGSS_DESC[FEATUREVER] Bits */
#define DEBUGSS_DESC_FEATUREVER_OFS (12) /* !< FEATUREVER Offset */
#define DEBUGSS_DESC_FEATUREVER_MASK ((uint32_t)0x0000F000U) /* !< Feature Set for the module
*instance* */
/* DEBUGSS_DESC[MODULEID] Bits */
#define DEBUGSS_DESC_MODULEID_OFS (16) /* !< MODULEID Offset */
#define DEBUGSS_DESC_MODULEID_MASK ((uint32_t)0xFFFF0000U) /* !< Module identification contains a
unique peripheral identification
number. The assignments are
maintained in a central database for
all of the platform modules to ensure
uniqueness. */
/* DEBUGSS_TXD Bits */
/* DEBUGSS_TXD[TX_DATA] Bits */
#define DEBUGSS_TXD_TX_DATA_OFS (0) /* !< TX_DATA Offset */
#define DEBUGSS_TXD_TX_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Contains data written by an
external debug tool to the SEC-AP
TXDATA register */
/* DEBUGSS_TXCTL Bits */
/* DEBUGSS_TXCTL[TRANSMIT] Bits */
#define DEBUGSS_TXCTL_TRANSMIT_OFS (0) /* !< TRANSMIT Offset */
#define DEBUGSS_TXCTL_TRANSMIT_MASK ((uint32_t)0x00000001U) /* !< Indicates data request in DSSM.TXD,
set on write via Debug AP to
DSSM.TXD. A read of the DSSM.TXD
register by SW will clear the TX
field. The tool can check that TXD is
empty by reading this field. */
#define DEBUGSS_TXCTL_TRANSMIT_EMPTY ((uint32_t)0x00000000U) /* !< TXD is empty */
#define DEBUGSS_TXCTL_TRANSMIT_FULL ((uint32_t)0x00000001U) /* !< TXD is full */
/* DEBUGSS_TXCTL[TRANSMIT_FLAGS] Bits */
#define DEBUGSS_TXCTL_TRANSMIT_FLAGS_OFS (1) /* !< TRANSMIT_FLAGS Offset */
#define DEBUGSS_TXCTL_TRANSMIT_FLAGS_MASK ((uint32_t)0xFFFFFFFEU) /* !< Generic TX flags that can be set by
external debug tool. Functionality is
defined by SW. */
/* DEBUGSS_RXD Bits */
/* DEBUGSS_RXD[RX_DATA] Bits */
#define DEBUGSS_RXD_RX_DATA_OFS (0) /* !< RX_DATA Offset */
#define DEBUGSS_RXD_RX_DATA_MASK ((uint32_t)0xFFFFFFFFU) /* !< Contains data written by SM/OW. */
/* DEBUGSS_RXCTL Bits */
/* DEBUGSS_RXCTL[RECEIVE] Bits */
#define DEBUGSS_RXCTL_RECEIVE_OFS (0) /* !< RECEIVE Offset */
#define DEBUGSS_RXCTL_RECEIVE_MASK ((uint32_t)0x00000001U) /* !< Indicates SW write to the DSSM.RXD
register. A read of the DSSM.RXD
register by SWD Access Port will
clear the RX field. */
#define DEBUGSS_RXCTL_RECEIVE_EMPTY ((uint32_t)0x00000000U) /* !< RXD empty */
#define DEBUGSS_RXCTL_RECEIVE_FULL ((uint32_t)0x00000001U) /* !< RXD full */
/* DEBUGSS_RXCTL[RECEIVE_FLAGS] Bits */
#define DEBUGSS_RXCTL_RECEIVE_FLAGS_OFS (1) /* !< RECEIVE_FLAGS Offset */
#define DEBUGSS_RXCTL_RECEIVE_FLAGS_MASK ((uint32_t)0x000000FEU) /* !< Generic RX flags that can be set by
SW and read by external debug tool.
Functionality is defined by SW. */
/* DEBUGSS_SPECIAL_AUTH Bits */
/* DEBUGSS_SPECIAL_AUTH[SECAPEN] Bits */
#define DEBUGSS_SPECIAL_AUTH_SECAPEN_OFS (0) /* !< SECAPEN Offset */
#define DEBUGSS_SPECIAL_AUTH_SECAPEN_MASK ((uint32_t)0x00000001U) /* !< An active high input. When asserted
(and SWD access is also permitted),
the debug tools can use the
Security-AP to communicate with
security control logic. When
deasserted, a DAPBUS firewall will
isolate the AP and prevent access to
the Security-AP. */
#define DEBUGSS_SPECIAL_AUTH_SECAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable SEC-AP */
#define DEBUGSS_SPECIAL_AUTH_SECAPEN_ENABLE ((uint32_t)0x00000001U) /* !< Enable SEC-AP */
/* DEBUGSS_SPECIAL_AUTH[SWDPORTEN] Bits */
#define DEBUGSS_SPECIAL_AUTH_SWDPORTEN_OFS (1) /* !< SWDPORTEN Offset */
#define DEBUGSS_SPECIAL_AUTH_SWDPORTEN_MASK ((uint32_t)0x00000002U) /* !< When asserted, the SW-DP functions
normally. When deasserted, the SW-DP
effectively disables all external
debug access. */
#define DEBUGSS_SPECIAL_AUTH_SWDPORTEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable SWD port */
#define DEBUGSS_SPECIAL_AUTH_SWDPORTEN_ENABLE ((uint32_t)0x00000002U) /* !< Enable SWD port */
/* DEBUGSS_SPECIAL_AUTH[DFTAPEN] Bits */
#define DEBUGSS_SPECIAL_AUTH_DFTAPEN_OFS (2) /* !< DFTAPEN Offset */
#define DEBUGSS_SPECIAL_AUTH_DFTAPEN_MASK ((uint32_t)0x00000004U) /* !< An active high input. When asserted
(and SWD access is also permitted),
the debug tools can then access the
DFT-AP external to the DebugSS lite.
When deasserted, a DAPBUS firewall
will isolate the AP and prevent
access. */
#define DEBUGSS_SPECIAL_AUTH_DFTAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable DFT-TAP */
#define DEBUGSS_SPECIAL_AUTH_DFTAPEN_ENABLE ((uint32_t)0x00000004U) /* !< Enable DFT-TAP */
/* DEBUGSS_SPECIAL_AUTH[ETAPEN] Bits */
#define DEBUGSS_SPECIAL_AUTH_ETAPEN_OFS (3) /* !< ETAPEN Offset */
#define DEBUGSS_SPECIAL_AUTH_ETAPEN_MASK ((uint32_t)0x00000008U) /* !< An active high input. When asserted
(and SWD access is also permitted),
the debug tools can then access an
ET-AP external to the DebugSS lite.
When deasserted, a DAPBUS firewall
will isolate the AP and prevent
access. */
#define DEBUGSS_SPECIAL_AUTH_ETAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable ET+ -AP */
#define DEBUGSS_SPECIAL_AUTH_ETAPEN_ENABLE ((uint32_t)0x00000008U) /* !< Enable ET+ -AP */
/* DEBUGSS_SPECIAL_AUTH[CFGAPEN] Bits */
#define DEBUGSS_SPECIAL_AUTH_CFGAPEN_OFS (4) /* !< CFGAPEN Offset */
#define DEBUGSS_SPECIAL_AUTH_CFGAPEN_MASK ((uint32_t)0x00000010U) /* !< An active high input. When asserted
(and SWD access is also permitted),
the debug tools can use the Config-AP
to read device configuration
information. When deasserted, a
DAPBUS firewall will isolate the AP
and prevent access to the Config-AP. */
#define DEBUGSS_SPECIAL_AUTH_CFGAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable CFG-AP */
#define DEBUGSS_SPECIAL_AUTH_CFGAPEN_ENABLE ((uint32_t)0x00000010U) /* !< Enable CFG-AP */
/* DEBUGSS_SPECIAL_AUTH[AHBAPEN] Bits */
#define DEBUGSS_SPECIAL_AUTH_AHBAPEN_OFS (5) /* !< AHBAPEN Offset */
#define DEBUGSS_SPECIAL_AUTH_AHBAPEN_MASK ((uint32_t)0x00000020U) /* !< Disabling / enabling debug access
to the M0+ Core via the AHB-AP DAP
bus isolation. */
#define DEBUGSS_SPECIAL_AUTH_AHBAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable AHB-AP */
#define DEBUGSS_SPECIAL_AUTH_AHBAPEN_ENABLE ((uint32_t)0x00000020U) /* !< Enable AHB-AP */
/* DEBUGSS_SPECIAL_AUTH[PWRAPEN] Bits */
#define DEBUGSS_SPECIAL_AUTH_PWRAPEN_OFS (6) /* !< PWRAPEN Offset */
#define DEBUGSS_SPECIAL_AUTH_PWRAPEN_MASK ((uint32_t)0x00000040U) /* !< An active high input. When asserted
(and SWD access is also permitted),
the debug tools can then access the
PWR-AP to power and reset state of
the CPU. When deasserted, a DAPBUS
firewall will isolate the AP and
prevent access. */
#define DEBUGSS_SPECIAL_AUTH_PWRAPEN_DISABLE ((uint32_t)0x00000000U) /* !< Disable PWR-AP */
#define DEBUGSS_SPECIAL_AUTH_PWRAPEN_ENABLE ((uint32_t)0x00000040U) /* !< Enable PWR-AP */
/* DEBUGSS_APP_AUTH Bits */
/* DEBUGSS_APP_AUTH[DBGEN] Bits */
#define DEBUGSS_APP_AUTH_DBGEN_OFS (0) /* !< DBGEN Offset */
#define DEBUGSS_APP_AUTH_DBGEN_MASK ((uint32_t)0x00000001U) /* !< Controls invasive debug enable. */
#define DEBUGSS_APP_AUTH_DBGEN_DISABLE ((uint32_t)0x00000000U) /* !< Invasive debug disabled */
#define DEBUGSS_APP_AUTH_DBGEN_ENABLE ((uint32_t)0x00000001U) /* !< Invasive debug enabled */
/* DEBUGSS_APP_AUTH[NIDEN] Bits */
#define DEBUGSS_APP_AUTH_NIDEN_OFS (1) /* !< NIDEN Offset */
#define DEBUGSS_APP_AUTH_NIDEN_MASK ((uint32_t)0x00000002U) /* !< Controls non-invasive debug enable. */
#define DEBUGSS_APP_AUTH_NIDEN_DISABLE ((uint32_t)0x00000000U) /* !< Non-invasive debug disabled */
#define DEBUGSS_APP_AUTH_NIDEN_ENABLE ((uint32_t)0x00000002U) /* !< Non-invasive debug enabled */
/* DEBUGSS_APP_AUTH[SPIDEN] Bits */
#define DEBUGSS_APP_AUTH_SPIDEN_OFS (2) /* !< SPIDEN Offset */
#define DEBUGSS_APP_AUTH_SPIDEN_MASK ((uint32_t)0x00000004U) /* !< Secure invasive debug enable. */
#define DEBUGSS_APP_AUTH_SPIDEN_DISABLE ((uint32_t)0x00000000U) /* !< Invasive debug disabled */
#define DEBUGSS_APP_AUTH_SPIDEN_ENABLE ((uint32_t)0x00000004U) /* !< Invasive debug enabled */
/* DEBUGSS_APP_AUTH[SPNIDEN] Bits */
#define DEBUGSS_APP_AUTH_SPNIDEN_OFS (3) /* !< SPNIDEN Offset */
#define DEBUGSS_APP_AUTH_SPNIDEN_MASK ((uint32_t)0x00000008U) /* !< Secure non-invasive debug enable. */
#define DEBUGSS_APP_AUTH_SPNIDEN_DISABLE ((uint32_t)0x00000000U) /* !< Invasive debug disabled */
#define DEBUGSS_APP_AUTH_SPNIDEN_ENABLE ((uint32_t)0x00000008U) /* !< Invasive debug enabled */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_m0p_hw_debugss__include */
libraries/sdk/ti/devices/msp/peripherals/m0p/hw_factoryregion.h
+441
View File
@@ -0,0 +1,441 @@
/*****************************************************************************
Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_hw_factoryregion__include
#define ti_devices_msp_peripherals_hw_factoryregion__include
/* This preliminary header file does not have a version number */
/* MMR repo: https://bitbucket.itg.ti.com/projects/cmcu_msp65soc/repos/trim_platform_constants */
/* MMR revision: ff4b6bcad5d93ca548bdb94b818a30dc3f4acd3f */
/* Generator revision: c98c4ac511e2bd0d918c5d427bd46b7a359dacf1
(MInT: ec7ec7482a60c6871be32db8b378ec27aa4771f6) */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* FACTORYREGION Registers
******************************************************************************/
#define FACTORYREGION_OPEN_OFS ((uint32_t)0x41C40000U)
/** @addtogroup FACTORYREGION_OPEN
@{
*/
typedef struct {
__I uint32_t TRACEID; /* !< (@ 0x41C40000) Defined by TI, during ATE, based on wafer */
__I uint32_t DEVICEID; /* !< (@ 0x41C40004) This is the JTAGIDCODE that comes from the Ramp
system */
__I uint32_t USERID; /* !< (@ 0x41C40008) Defined by TI, depending on device spin */
__I uint32_t BSLPIN_UART; /* !< (@ 0x41C4000C) BSL UART Pin Configuration */
__I uint32_t BSLPIN_I2C; /* !< (@ 0x41C40010) BSL I2C Pin Configuration */
__I uint32_t BSLPIN_INVOKE; /* !< (@ 0x41C40014) BSL Pin Invocation Configuration */
__I uint32_t SRAMFLASH; /* !< (@ 0x41C40018) */
__I uint32_t PLLSTARTUP0_4_8MHZ; /* !< (@ 0x41C4001C) */
__I uint32_t PLLSTARTUP1_4_8MHZ; /* !< (@ 0x41C40020) System PLL Paramater 1 MMR --- Data from Flash
Table Lookup */
__I uint32_t PLLSTARTUP0_8_16MHZ; /* !< (@ 0x41C40024) */
__I uint32_t PLLSTARTUP1_8_16MHZ; /* !< (@ 0x41C40028) System PLL Paramater 1 MMR --- Data from Flash
Table Lookup */
__I uint32_t PLLSTARTUP0_16_32MHZ; /* !< (@ 0x41C4002C) */
__I uint32_t PLLSTARTUP1_16_32MHZ; /* !< (@ 0x41C40030) System PLL Paramater 1 MMR --- Data from Flash
Table Lookup */
__I uint32_t PLLSTARTUP0_32_48MHZ; /* !< (@ 0x41C40034) */
__I uint32_t PLLSTARTUP1_32_48MHZ; /* !< (@ 0x41C40038) System PLL Paramater 1 MMR --- Data from Flash
Table Lookup */
__I uint32_t TEMP_SENSE0; /* !< (@ 0x41C4003C) Temperature sensor room temperature calibration
code. This is ADC conversion results of temperature sensor output
voltage. Included in BOOTCRC calculation. */
__I uint32_t RESERVED0; /* !< (@ 0x41C40040) */
__I uint32_t RESERVED1; /* !< (@ 0x41C40044) */
__I uint32_t RESERVED2; /* !< (@ 0x41C40048) */
__I uint32_t RESERVED3; /* !< (@ 0x41C4004C) */
__I uint32_t RESERVED4; /* !< (@ 0x41C40050) */
__I uint32_t RESERVED5; /* !< (@ 0x41C40054) */
__I uint32_t RESERVED6; /* !< (@ 0x41C40058) */
__I uint32_t RESERVED7; /* !< (@ 0x41C4005C) */
__I uint32_t RESERVED8; /* !< (@ 0x41C40060) */
__I uint32_t RESERVED9; /* !< (@ 0x41C40064) */
__I uint32_t RESERVED10; /* !< (@ 0x41C40068) */
__I uint32_t RESERVED11; /* !< (@ 0x41C4006C) */
__I uint32_t RESERVED12; /* !< (@ 0x41C40070) */
__I uint32_t RESERVED13; /* !< (@ 0x41C40074) */
__I uint32_t RESERVED14; /* !< (@ 0x41C40078) */
__I uint32_t BOOTCRC; /* !< (@ 0x41C4007C) BOOTCRC records the 32-bit CRC of all locations in
OPEN including reserved locations. */
} FACTORYREGION_OPEN_Regs;
/*@}*/ /* end of group FACTORYREGION_OPEN */
/** @addtogroup FACTORYREGION
@{
*/
typedef struct {
uint32_t RESERVED0[275841024];
FACTORYREGION_OPEN_Regs OPEN; /* !< (@ 0x41C40000) Customer-visible data (IDs, PLL trims,...) */
} FACTORYREGION_Regs;
/*@}*/ /* end of group FACTORYREGION */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* FACTORYREGION Register Control Bits
******************************************************************************/
/* FACTORYREGION_TRACEID Bits */
/* FACTORYREGION_TRACEID[DATA] Bits */
#define FACTORYREGION_TRACEID_DATA_OFS (0) /* !< DATA Offset */
#define FACTORYREGION_TRACEID_DATA_MASK ((uint32_t)0xFFFFFFFFU)
/* FACTORYREGION_DEVICEID Bits */
/* FACTORYREGION_DEVICEID[VERSION] Bits */
#define FACTORYREGION_DEVICEID_VERSION_OFS (28) /* !< VERSION Offset */
#define FACTORYREGION_DEVICEID_VERSION_MASK ((uint32_t)0xF0000000U) /* !< Revision of the device. This field
should change each time that the
logic or mask set of the device is
revised. */
/* FACTORYREGION_DEVICEID[PARTNUM] Bits */
#define FACTORYREGION_DEVICEID_PARTNUM_OFS (12) /* !< PARTNUM Offset */
#define FACTORYREGION_DEVICEID_PARTNUM_MASK ((uint32_t)0x0FFFF000U) /* !< Part number of the device. */
/* FACTORYREGION_DEVICEID[MANUFACTURER] Bits */
#define FACTORYREGION_DEVICEID_MANUFACTURER_OFS (1) /* !< MANUFACTURER Offset */
#define FACTORYREGION_DEVICEID_MANUFACTURER_MASK ((uint32_t)0x00000FFEU) /* !< TI's JEDEC bank and company code,
which is: 00000010111b */
/* FACTORYREGION_DEVICEID[ALWAYS_1] Bits */
#define FACTORYREGION_DEVICEID_ALWAYS_1_OFS (0) /* !< ALWAYS_1 Offset */
#define FACTORYREGION_DEVICEID_ALWAYS_1_MASK ((uint32_t)0x00000001U) /* !< This is always 1 */
/* FACTORYREGION_USERID Bits */
/* FACTORYREGION_USERID[PART] Bits */
#define FACTORYREGION_USERID_PART_OFS (0) /* !< PART Offset */
#define FACTORYREGION_USERID_PART_MASK ((uint32_t)0x0000FFFFU) /* !< Bit pattern that uniquely
identifying a part. This is used to
identify the specific part based on
the die identified in
DEVICEID.device. This number shall be
selected at random among the
remaining numbers for DEVICEID.device
such that the order of creation
cannot be inferred by the number.
This value does not encode the part
number directly. */
/* FACTORYREGION_USERID[VARIANT] Bits */
#define FACTORYREGION_USERID_VARIANT_OFS (16) /* !< VARIANT Offset */
#define FACTORYREGION_USERID_VARIANT_MASK ((uint32_t)0x00FF0000U) /* !< Bit pattern uniquely identifying a
variant of a part. This is used to
indicate memory or package variations
of the same part number. This number
shall be selected at random among the
remaining numbers for the relevant
combination of IDCODE.device and
USERCODE.part such that the order of
creation cannot be inferred by the
number. The variant number does not
encode specifics of the variant
directly. */
/* FACTORYREGION_USERID[MINORREV] Bits */
#define FACTORYREGION_USERID_MINORREV_OFS (24) /* !< MINORREV Offset */
#define FACTORYREGION_USERID_MINORREV_MASK ((uint32_t)0x0F000000U) /* !< Monotonic increasing value
indicating a new revision of the SKU
that preserves compatibility with
lesser minorrev values. New
capability may be introduced such
that lesser minorrev numbers may not
be compatible with greater if the new
capability is used. */
/* FACTORYREGION_USERID[MAJORREV] Bits */
#define FACTORYREGION_USERID_MAJORREV_OFS (28) /* !< MAJORREV Offset */
#define FACTORYREGION_USERID_MAJORREV_MASK ((uint32_t)0x70000000U) /* !< Monotonic increasing value
indicating a new revision of the SKU
significant enough that users of the
device may have to revise PCB or or
software design */
/* FACTORYREGION_USERID[START] Bits */
#define FACTORYREGION_USERID_START_OFS (31) /* !< START Offset */
#define FACTORYREGION_USERID_START_MASK ((uint32_t)0x80000000U)
/* FACTORYREGION_BSLPIN_UART Bits */
/* FACTORYREGION_BSLPIN_UART[UART_RXD_PAD] Bits */
#define FACTORYREGION_BSLPIN_UART_UART_RXD_PAD_OFS (0) /* !< UART_RXD_PAD Offset */
#define FACTORYREGION_BSLPIN_UART_UART_RXD_PAD_MASK ((uint32_t)0x000000FFU) /* !< UART RXD Pad used by BSL */
/* FACTORYREGION_BSLPIN_UART[UART_RXD_PF] Bits */
#define FACTORYREGION_BSLPIN_UART_UART_RXD_PF_OFS (8) /* !< UART_RXD_PF Offset */
#define FACTORYREGION_BSLPIN_UART_UART_RXD_PF_MASK ((uint32_t)0x0000FF00U) /* !< UART RXD Pin Function Selection
Value */
/* FACTORYREGION_BSLPIN_UART[UART_TXD_PAD] Bits */
#define FACTORYREGION_BSLPIN_UART_UART_TXD_PAD_OFS (16) /* !< UART_TXD_PAD Offset */
#define FACTORYREGION_BSLPIN_UART_UART_TXD_PAD_MASK ((uint32_t)0x00FF0000U) /* !< UART TXD Pin used by BSL */
/* FACTORYREGION_BSLPIN_UART[UART_TXD_PF] Bits */
#define FACTORYREGION_BSLPIN_UART_UART_TXD_PF_OFS (24) /* !< UART_TXD_PF Offset */
#define FACTORYREGION_BSLPIN_UART_UART_TXD_PF_MASK ((uint32_t)0xFF000000U) /* !< UART TXD Pin Function Selection
Value */
/* FACTORYREGION_BSLPIN_I2C Bits */
/* FACTORYREGION_BSLPIN_I2C[I2C_SDA_PAD] Bits */
#define FACTORYREGION_BSLPIN_I2C_I2C_SDA_PAD_OFS (0) /* !< I2C_SDA_PAD Offset */
#define FACTORYREGION_BSLPIN_I2C_I2C_SDA_PAD_MASK ((uint32_t)0x000000FFU) /* !< I2C SDA Pin used by BSL */
/* FACTORYREGION_BSLPIN_I2C[I2C_SDA_PF] Bits */
#define FACTORYREGION_BSLPIN_I2C_I2C_SDA_PF_OFS (8) /* !< I2C_SDA_PF Offset */
#define FACTORYREGION_BSLPIN_I2C_I2C_SDA_PF_MASK ((uint32_t)0x0000FF00U) /* !< I2C SDA Pin Function Selection
Value */
/* FACTORYREGION_BSLPIN_I2C[I2C_SCL_PAD] Bits */
#define FACTORYREGION_BSLPIN_I2C_I2C_SCL_PAD_OFS (16) /* !< I2C_SCL_PAD Offset */
#define FACTORYREGION_BSLPIN_I2C_I2C_SCL_PAD_MASK ((uint32_t)0x00FF0000U) /* !< I2C SCL Pin used by BSL */
/* FACTORYREGION_BSLPIN_I2C[I2C_SCL_PF] Bits */
#define FACTORYREGION_BSLPIN_I2C_I2C_SCL_PF_OFS (24) /* !< I2C_SCL_PF Offset */
#define FACTORYREGION_BSLPIN_I2C_I2C_SCL_PF_MASK ((uint32_t)0xFF000000U) /* !< I2C SCL Pin Function Selection
Value */
/* FACTORYREGION_BSLPIN_INVOKE Bits */
/* FACTORYREGION_BSLPIN_INVOKE[BSL_PAD] Bits */
#define FACTORYREGION_BSLPIN_INVOKE_BSL_PAD_OFS (0) /* !< BSL_PAD Offset */
#define FACTORYREGION_BSLPIN_INVOKE_BSL_PAD_MASK ((uint32_t)0x0000007FU) /* !< BSL Invocation Pin Number */
/* FACTORYREGION_BSLPIN_INVOKE[GPIO_LEVEL] Bits */
#define FACTORYREGION_BSLPIN_INVOKE_GPIO_LEVEL_OFS (7) /* !< GPIO_LEVEL Offset */
#define FACTORYREGION_BSLPIN_INVOKE_GPIO_LEVEL_MASK ((uint32_t)0x00000080U) /* !< GPIO Level Configuration for BSL
Invocation */
/* FACTORYREGION_BSLPIN_INVOKE[GPIO_PIN_SEL] Bits */
#define FACTORYREGION_BSLPIN_INVOKE_GPIO_PIN_SEL_OFS (8) /* !< GPIO_PIN_SEL Offset */
#define FACTORYREGION_BSLPIN_INVOKE_GPIO_PIN_SEL_MASK ((uint32_t)0x00001F00U) /* !< GPIO Pin Number in GPIO Module */
/* FACTORYREGION_BSLPIN_INVOKE[GPIO_REG_SEL] Bits */
#define FACTORYREGION_BSLPIN_INVOKE_GPIO_REG_SEL_OFS (13) /* !< GPIO_REG_SEL Offset */
#define FACTORYREGION_BSLPIN_INVOKE_GPIO_REG_SEL_MASK ((uint32_t)0x00006000U) /* !< GPIO Module Selection */
/* FACTORYREGION_SRAMFLASH Bits */
/* FACTORYREGION_SRAMFLASH[MAINFLASH_SZ] Bits */
#define FACTORYREGION_SRAMFLASH_MAINFLASH_SZ_OFS (0) /* !< MAINFLASH_SZ Offset */
#define FACTORYREGION_SRAMFLASH_MAINFLASH_SZ_MASK ((uint32_t)0x00000FFFU) /* !< The encoding of the field is that
the value of the field is an integer
to be interpreted as number of KBs.
For eg: if the value of the field id
4, then it is 4KB, if the value is
32, then 32KB, and so on. */
/* FACTORYREGION_SRAMFLASH[SRAM_SZ] Bits */
#define FACTORYREGION_SRAMFLASH_SRAM_SZ_OFS (16) /* !< SRAM_SZ Offset */
#define FACTORYREGION_SRAMFLASH_SRAM_SZ_MASK ((uint32_t)0x03FF0000U) /* !< The encoding of the field is that
the value of the field is an integer
to be interpreted as number of KBs.
For eg: if the value of the field id
4, then it is 4KB, if the value is
32, then 32KB, and so on. */
/* FACTORYREGION_SRAMFLASH[DATAFLASH_SZ] Bits */
#define FACTORYREGION_SRAMFLASH_DATAFLASH_SZ_OFS (26) /* !< DATAFLASH_SZ Offset */
#define FACTORYREGION_SRAMFLASH_DATAFLASH_SZ_MASK ((uint32_t)0xFC000000U) /* !< The encoding of the field is that
the value of the field is an integer
to be interpreted as number of KBs.
For eg: if the value of the field id
4, then it is 4KB, if the value is
32, then 32KB, and so on. */
/* FACTORYREGION_SRAMFLASH[MAINNUMBANKS] Bits */
#define FACTORYREGION_SRAMFLASH_MAINNUMBANKS_OFS (12) /* !< MAINNUMBANKS Offset */
#define FACTORYREGION_SRAMFLASH_MAINNUMBANKS_MASK ((uint32_t)0x00003000U)
#define FACTORYREGION_SRAMFLASH_MAINNUMBANKS_ONEBANK ((uint32_t)0x00000000U)
#define FACTORYREGION_SRAMFLASH_MAINNUMBANKS_TWOBANKS ((uint32_t)0x00001000U)
#define FACTORYREGION_SRAMFLASH_MAINNUMBANKS_THREEBANKS ((uint32_t)0x00002000U)
#define FACTORYREGION_SRAMFLASH_MAINNUMBANKS_FOURBANKS ((uint32_t)0x00003000U)
/* FACTORYREGION_PLLSTARTUP0_4_8MHZ Bits */
/* FACTORYREGION_PLLSTARTUP0_4_8MHZ[STARTTIME] Bits */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_STARTTIME_OFS (0) /* !< STARTTIME Offset */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_STARTTIME_MASK ((uint32_t)0x0000003FU) /* !< Startup time from Enable to Locked
Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_4_8MHZ[STARTTIMELP] Bits */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_STARTTIMELP_OFS (8) /* !< STARTTIMELP Offset */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_STARTTIMELP_MASK ((uint32_t)0x00003F00U) /* !< Startup time from Low Power Exit to
Locked Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_4_8MHZ[CPCURRENT] Bits */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CPCURRENT_OFS (16) /* !< CPCURRENT Offset */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CPCURRENT_MASK ((uint32_t)0x003F0000U) /* !< Charge Pump Current */
/* FACTORYREGION_PLLSTARTUP0_4_8MHZ[CAPBVAL] Bits */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CAPBVAL_OFS (24) /* !< CAPBVAL Offset */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CAPBVAL_MASK ((uint32_t)0x1F000000U) /* !< Override Value for Cap B */
/* FACTORYREGION_PLLSTARTUP0_4_8MHZ[CAPBOVERRIDE] Bits */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CAPBOVERRIDE_OFS (31) /* !< CAPBOVERRIDE Offset */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CAPBOVERRIDE_MASK ((uint32_t)0x80000000U) /* !< Override Enable For Cap B */
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CAPBOVERRIDE_DISABLE ((uint32_t)0x00000000U)
#define FACTORYREGION_PLLSTARTUP0_4_8MHZ_CAPBOVERRIDE_ENABLE ((uint32_t)0x80000000U)
/* FACTORYREGION_PLLSTARTUP1_4_8MHZ Bits */
/* FACTORYREGION_PLLSTARTUP1_4_8MHZ[LPFCAPA] Bits */
#define FACTORYREGION_PLLSTARTUP1_4_8MHZ_LPFCAPA_OFS (0) /* !< LPFCAPA Offset */
#define FACTORYREGION_PLLSTARTUP1_4_8MHZ_LPFCAPA_MASK ((uint32_t)0x0000001FU) /* !< Loop Filter Cap A */
/* FACTORYREGION_PLLSTARTUP1_4_8MHZ[LPFRESA] Bits */
#define FACTORYREGION_PLLSTARTUP1_4_8MHZ_LPFRESA_OFS (8) /* !< LPFRESA Offset */
#define FACTORYREGION_PLLSTARTUP1_4_8MHZ_LPFRESA_MASK ((uint32_t)0x0003FF00U) /* !< Loop Filter Res A */
/* FACTORYREGION_PLLSTARTUP1_4_8MHZ[LPFRESC] Bits */
#define FACTORYREGION_PLLSTARTUP1_4_8MHZ_LPFRESC_OFS (24) /* !< LPFRESC Offset */
#define FACTORYREGION_PLLSTARTUP1_4_8MHZ_LPFRESC_MASK ((uint32_t)0xFF000000U) /* !< Loop Filter Res C */
/* FACTORYREGION_PLLSTARTUP0_8_16MHZ Bits */
/* FACTORYREGION_PLLSTARTUP0_8_16MHZ[STARTTIME] Bits */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_STARTTIME_OFS (0) /* !< STARTTIME Offset */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_STARTTIME_MASK ((uint32_t)0x0000003FU) /* !< Startup time from Enable to Locked
Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_8_16MHZ[STARTTIMELP] Bits */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_STARTTIMELP_OFS (8) /* !< STARTTIMELP Offset */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_STARTTIMELP_MASK ((uint32_t)0x00003F00U) /* !< Startup time from Low Power Exit to
Locked Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_8_16MHZ[CPCURRENT] Bits */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CPCURRENT_OFS (16) /* !< CPCURRENT Offset */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CPCURRENT_MASK ((uint32_t)0x003F0000U) /* !< Charge Pump Current */
/* FACTORYREGION_PLLSTARTUP0_8_16MHZ[CAPBVAL] Bits */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CAPBVAL_OFS (24) /* !< CAPBVAL Offset */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CAPBVAL_MASK ((uint32_t)0x1F000000U) /* !< Override Value for Cap B */
/* FACTORYREGION_PLLSTARTUP0_8_16MHZ[CAPBOVERRIDE] Bits */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CAPBOVERRIDE_OFS (31) /* !< CAPBOVERRIDE Offset */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CAPBOVERRIDE_MASK ((uint32_t)0x80000000U) /* !< Override Enable For Cap B */
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CAPBOVERRIDE_DISABLE ((uint32_t)0x00000000U)
#define FACTORYREGION_PLLSTARTUP0_8_16MHZ_CAPBOVERRIDE_ENABLE ((uint32_t)0x80000000U)
/* FACTORYREGION_PLLSTARTUP1_8_16MHZ Bits */
/* FACTORYREGION_PLLSTARTUP1_8_16MHZ[LPFCAPA] Bits */
#define FACTORYREGION_PLLSTARTUP1_8_16MHZ_LPFCAPA_OFS (0) /* !< LPFCAPA Offset */
#define FACTORYREGION_PLLSTARTUP1_8_16MHZ_LPFCAPA_MASK ((uint32_t)0x0000001FU) /* !< Loop Filter Cap A */
/* FACTORYREGION_PLLSTARTUP1_8_16MHZ[LPFRESA] Bits */
#define FACTORYREGION_PLLSTARTUP1_8_16MHZ_LPFRESA_OFS (8) /* !< LPFRESA Offset */
#define FACTORYREGION_PLLSTARTUP1_8_16MHZ_LPFRESA_MASK ((uint32_t)0x0003FF00U) /* !< Loop Filter Res A */
/* FACTORYREGION_PLLSTARTUP1_8_16MHZ[LPFRESC] Bits */
#define FACTORYREGION_PLLSTARTUP1_8_16MHZ_LPFRESC_OFS (24) /* !< LPFRESC Offset */
#define FACTORYREGION_PLLSTARTUP1_8_16MHZ_LPFRESC_MASK ((uint32_t)0xFF000000U) /* !< Loop Filter Res C */
/* FACTORYREGION_PLLSTARTUP0_16_32MHZ Bits */
/* FACTORYREGION_PLLSTARTUP0_16_32MHZ[STARTTIME] Bits */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_STARTTIME_OFS (0) /* !< STARTTIME Offset */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_STARTTIME_MASK ((uint32_t)0x0000003FU) /* !< Startup time from Enable to Locked
Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_16_32MHZ[STARTTIMELP] Bits */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_STARTTIMELP_OFS (8) /* !< STARTTIMELP Offset */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_STARTTIMELP_MASK ((uint32_t)0x00003F00U) /* !< Startup time from Low Power Exit to
Locked Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_16_32MHZ[CPCURRENT] Bits */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CPCURRENT_OFS (16) /* !< CPCURRENT Offset */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CPCURRENT_MASK ((uint32_t)0x003F0000U) /* !< Charge Pump Current */
/* FACTORYREGION_PLLSTARTUP0_16_32MHZ[CAPBVAL] Bits */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CAPBVAL_OFS (24) /* !< CAPBVAL Offset */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CAPBVAL_MASK ((uint32_t)0x1F000000U) /* !< Override Value for Cap B */
/* FACTORYREGION_PLLSTARTUP0_16_32MHZ[CAPBOVERRIDE] Bits */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CAPBOVERRIDE_OFS (31) /* !< CAPBOVERRIDE Offset */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CAPBOVERRIDE_MASK ((uint32_t)0x80000000U) /* !< Override Enable For Cap B */
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CAPBOVERRIDE_DISABLE ((uint32_t)0x00000000U)
#define FACTORYREGION_PLLSTARTUP0_16_32MHZ_CAPBOVERRIDE_ENABLE ((uint32_t)0x80000000U)
/* FACTORYREGION_PLLSTARTUP1_16_32MHZ Bits */
/* FACTORYREGION_PLLSTARTUP1_16_32MHZ[LPFCAPA] Bits */
#define FACTORYREGION_PLLSTARTUP1_16_32MHZ_LPFCAPA_OFS (0) /* !< LPFCAPA Offset */
#define FACTORYREGION_PLLSTARTUP1_16_32MHZ_LPFCAPA_MASK ((uint32_t)0x0000001FU) /* !< Loop Filter Cap A */
/* FACTORYREGION_PLLSTARTUP1_16_32MHZ[LPFRESA] Bits */
#define FACTORYREGION_PLLSTARTUP1_16_32MHZ_LPFRESA_OFS (8) /* !< LPFRESA Offset */
#define FACTORYREGION_PLLSTARTUP1_16_32MHZ_LPFRESA_MASK ((uint32_t)0x0003FF00U) /* !< Loop Filter Res A */
/* FACTORYREGION_PLLSTARTUP1_16_32MHZ[LPFRESC] Bits */
#define FACTORYREGION_PLLSTARTUP1_16_32MHZ_LPFRESC_OFS (24) /* !< LPFRESC Offset */
#define FACTORYREGION_PLLSTARTUP1_16_32MHZ_LPFRESC_MASK ((uint32_t)0xFF000000U) /* !< Loop Filter Res C */
/* FACTORYREGION_PLLSTARTUP0_32_48MHZ Bits */
/* FACTORYREGION_PLLSTARTUP0_32_48MHZ[STARTTIME] Bits */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_STARTTIME_OFS (0) /* !< STARTTIME Offset */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_STARTTIME_MASK ((uint32_t)0x0000003FU) /* !< Startup time from Enable to Locked
Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_32_48MHZ[STARTTIMELP] Bits */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_STARTTIMELP_OFS (8) /* !< STARTTIMELP Offset */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_STARTTIMELP_MASK ((uint32_t)0x00003F00U) /* !< Startup time from Low Power Exit to
Locked Clock in resolution of 1usec */
/* FACTORYREGION_PLLSTARTUP0_32_48MHZ[CPCURRENT] Bits */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CPCURRENT_OFS (16) /* !< CPCURRENT Offset */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CPCURRENT_MASK ((uint32_t)0x003F0000U) /* !< Charge Pump Current */
/* FACTORYREGION_PLLSTARTUP0_32_48MHZ[CAPBVAL] Bits */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CAPBVAL_OFS (24) /* !< CAPBVAL Offset */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CAPBVAL_MASK ((uint32_t)0x1F000000U) /* !< Override Value for Cap B */
/* FACTORYREGION_PLLSTARTUP0_32_48MHZ[CAPBOVERRIDE] Bits */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CAPBOVERRIDE_OFS (31) /* !< CAPBOVERRIDE Offset */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CAPBOVERRIDE_MASK ((uint32_t)0x80000000U) /* !< Override Enable For Cap B */
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CAPBOVERRIDE_DISABLE ((uint32_t)0x00000000U)
#define FACTORYREGION_PLLSTARTUP0_32_48MHZ_CAPBOVERRIDE_ENABLE ((uint32_t)0x80000000U)
/* FACTORYREGION_PLLSTARTUP1_32_48MHZ Bits */
/* FACTORYREGION_PLLSTARTUP1_32_48MHZ[LPFCAPA] Bits */
#define FACTORYREGION_PLLSTARTUP1_32_48MHZ_LPFCAPA_OFS (0) /* !< LPFCAPA Offset */
#define FACTORYREGION_PLLSTARTUP1_32_48MHZ_LPFCAPA_MASK ((uint32_t)0x0000001FU) /* !< Loop Filter Cap A */
/* FACTORYREGION_PLLSTARTUP1_32_48MHZ[LPFRESA] Bits */
#define FACTORYREGION_PLLSTARTUP1_32_48MHZ_LPFRESA_OFS (8) /* !< LPFRESA Offset */
#define FACTORYREGION_PLLSTARTUP1_32_48MHZ_LPFRESA_MASK ((uint32_t)0x0003FF00U) /* !< Loop Filter Res A */
/* FACTORYREGION_PLLSTARTUP1_32_48MHZ[LPFRESC] Bits */
#define FACTORYREGION_PLLSTARTUP1_32_48MHZ_LPFRESC_OFS (24) /* !< LPFRESC Offset */
#define FACTORYREGION_PLLSTARTUP1_32_48MHZ_LPFRESC_MASK ((uint32_t)0xFF000000U) /* !< Loop Filter Res C */
/* FACTORYREGION_TEMP_SENSE0 Bits */
/* FACTORYREGION_TEMP_SENSE0[DATA] Bits */
#define FACTORYREGION_TEMP_SENSE0_DATA_OFS (0) /* !< DATA Offset */
#define FACTORYREGION_TEMP_SENSE0_DATA_MASK ((uint32_t)0xFFFFFFFFU)
/* FACTORYREGION_BOOTCRC Bits */
/* FACTORYREGION_BOOTCRC[DATA] Bits */
#define FACTORYREGION_BOOTCRC_DATA_OFS (0) /* !< DATA Offset */
#define FACTORYREGION_BOOTCRC_DATA_MASK ((uint32_t)0xFFFFFFFFU)
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_hw_factoryregion__include */
libraries/sdk/ti/devices/msp/peripherals/m0p/hw_sysctl.h
+70
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@@ -0,0 +1,70 @@
/*****************************************************************************
Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
/* This file automatically includes the specific device sysctl header file
without the need to include a specific device sysctl header.
The device #define is set automatically through the toolchain on basis
of the device chosen in the device selection menu (.e.g -D__MICRO1__). */
#ifndef ti_devices_msp_peripheral_m0p_sysctl__include
#define ti_devices_msp_peripheral_m0p_sysctl__include
/******************************************************************************
* MSP devices
******************************************************************************/
#include <ti/devices/DeviceFamily.h>
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G1X0X_G3X0X)
#include <ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0g1x0x_g3x0x.h>
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L11XX_L13XX)
#include <ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0l11xx_l13xx.h>
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0C110X) || (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPS003FX)
#include <ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0c110x.h>
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L122X_L222X)
#include <ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0l122x_l222x.h>
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0GX51X)
#include <ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0gx51x.h>
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L111X)
#include <ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0l111x.h>
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0H321X)
#include <ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0h321x.h>
/********************************************************************
*
********************************************************************/
#else
#error "Failed to match a default include file"
#endif
#endif /* ti_devices_msp_peripheral_m0p_sysctl__include */
libraries/sdk/ti/devices/msp/peripherals/m0p/sysctl/hw_sysctl_mspm0c110x.h
+991
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@@ -0,0 +1,991 @@
/*****************************************************************************
Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the
distribution.
Neither the name of Texas Instruments Incorporated nor the names of
its contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0c110x__include
#define ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0c110x__include
/* Filename: hw_sysctl_mspm0c110x.h */
/* Revised: 2024-11-18 03:51:42 */
/* Revision: 71ad117d0ac260e84eba242c6eff6a9062e15e6c */
#ifndef __CORTEX_M
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#endif
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* SYSCTL Registers
******************************************************************************/
#define SYSCTL_SOCLOCK_OFS ((uint32_t)0x00001000U)
/** @addtogroup SYSCTL_SOCLOCK
@{
*/
typedef struct {
uint32_t RESERVED0[8];
__I uint32_t IIDX; /* !< (@ 0x00001020) SYSCTL interrupt index */
uint32_t RESERVED1;
__IO uint32_t IMASK; /* !< (@ 0x00001028) SYSCTL interrupt mask */
uint32_t RESERVED2;
__I uint32_t RIS; /* !< (@ 0x00001030) SYSCTL raw interrupt status */
uint32_t RESERVED3;
__I uint32_t MIS; /* !< (@ 0x00001038) SYSCTL masked interrupt status */
uint32_t RESERVED4;
__O uint32_t ISET; /* !< (@ 0x00001040) SYSCTL interrupt set */
uint32_t RESERVED5;
__O uint32_t ICLR; /* !< (@ 0x00001048) SYSCTL interrupt clear */
uint32_t RESERVED6;
__I uint32_t NMIIIDX; /* !< (@ 0x00001050) NMI interrupt index */
uint32_t RESERVED7[3];
__I uint32_t NMIRIS; /* !< (@ 0x00001060) NMI raw interrupt status */
uint32_t RESERVED8[3];
__O uint32_t NMIISET; /* !< (@ 0x00001070) NMI interrupt set */
uint32_t RESERVED9;
__O uint32_t NMIICLR; /* !< (@ 0x00001078) NMI interrupt clear */
uint32_t RESERVED10[33];
__IO uint32_t SYSOSCCFG; /* !< (@ 0x00001100) SYSOSC configuration */
__IO uint32_t MCLKCFG; /* !< (@ 0x00001104) Main clock (MCLK) configuration */
__IO uint32_t HSCLKEN; /* !< (@ 0x00001108) High-speed clock (HSCLK) source enable/disable */
uint32_t RESERVED11[11];
__IO uint32_t GENCLKCFG; /* !< (@ 0x00001138) General clock configuration */
__IO uint32_t GENCLKEN; /* !< (@ 0x0000113C) General clock enable control */
__IO uint32_t PMODECFG; /* !< (@ 0x00001140) Power mode configuration */
uint32_t RESERVED12[3];
__I uint32_t FCC; /* !< (@ 0x00001150) Frequency clock counter (FCC) count */
uint32_t RESERVED13[9];
__IO uint32_t SRAMBOUNDARY; /* !< (@ 0x00001178) SRAM Write Boundary */
uint32_t RESERVED14;
__IO uint32_t SYSTEMCFG; /* !< (@ 0x00001180) System configuration */
uint32_t RESERVED15[3];
__IO uint32_t BEEPCFG; /* !< (@ 0x00001190) BEEPER Configuration */
uint32_t RESERVED16[27];
__IO uint32_t WRITELOCK; /* !< (@ 0x00001200) SYSCTL register write lockout */
__I uint32_t CLKSTATUS; /* !< (@ 0x00001204) Clock module (CKM) status */
__I uint32_t SYSSTATUS; /* !< (@ 0x00001208) System status information */
uint32_t RESERVED17[5];
__I uint32_t RSTCAUSE; /* !< (@ 0x00001220) Reset cause */
uint32_t RESERVED18[55];
__IO uint32_t RESETLEVEL; /* !< (@ 0x00001300) Reset level for application-triggered reset
command */
__O uint32_t RESETCMD; /* !< (@ 0x00001304) Execute an application-triggered reset command */
__IO uint32_t BORTHRESHOLD; /* !< (@ 0x00001308) BOR threshold selection */
__O uint32_t BORCLRCMD; /* !< (@ 0x0000130C) Set the BOR threshold */
__O uint32_t SYSOSCFCLCTL; /* !< (@ 0x00001310) SYSOSC frequency correction loop (FCL) ROSC enable */
uint32_t RESERVED19;
__O uint32_t EXLFCTL; /* !< (@ 0x00001318) LFCLK_IN and LFCLK control */
__O uint32_t SHDNIOREL; /* !< (@ 0x0000131C) SHUTDOWN IO release control */
__O uint32_t EXRSTPIN; /* !< (@ 0x00001320) Disable the reset function of the NRST pin */
__O uint32_t SYSSTATUSCLR; /* !< (@ 0x00001324) Clear sticky bits of SYSSTATUS */
__O uint32_t SWDCFG; /* !< (@ 0x00001328) Disable the SWD function on the SWD pins */
__O uint32_t FCCCMD; /* !< (@ 0x0000132C) Frequency clock counter start capture */
uint32_t RESERVED20[52];
__IO uint32_t SHUTDNSTORE0; /* !< (@ 0x00001400) Shutdown storage memory (byte 0) */
__IO uint32_t SHUTDNSTORE1; /* !< (@ 0x00001404) Shutdown storage memory (byte 1) */
__IO uint32_t SHUTDNSTORE2; /* !< (@ 0x00001408) Shutdown storage memory (byte 2) */
__IO uint32_t SHUTDNSTORE3; /* !< (@ 0x0000140C) Shutdown storage memory (byte 3) */
} SYSCTL_SOCLOCK_Regs;
/*@}*/ /* end of group SYSCTL_SOCLOCK */
/** @addtogroup SYSCTL
@{
*/
typedef struct {
uint32_t RESERVED0[1024];
SYSCTL_SOCLOCK_Regs SOCLOCK; /* !< (@ 0x00001000) SYSCTL SOCLOCK Region */
} SYSCTL_Regs;
/*@}*/ /* end of group SYSCTL */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************
* SYSCTL Register Control Bits
******************************************************************************/
/* SYSCTL_IIDX Bits */
/* SYSCTL_IIDX[STAT] Bits */
#define SYSCTL_IIDX_STAT_OFS (0) /* !< STAT Offset */
#define SYSCTL_IIDX_STAT_MASK ((uint32_t)0x00000003U) /* !< The SYSCTL interrupt index (IIDX)
register generates a value
corresponding to the highest priority
pending interrupt source. This value
may be used as an address offset for
fast, deterministic handling in the
interrupt service routine. A read of
the IIDX register will clear the
corresponding interrupt status in the
RIS and MIS registers. */
#define SYSCTL_IIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define SYSCTL_IIDX_STAT_LFOSCGOOD ((uint32_t)0x00000001U) /* !< LFOSCGOOD interrupt pending */
#define SYSCTL_IIDX_STAT_ANACLKERR ((uint32_t)0x00000002U)
/* SYSCTL_IMASK Bits */
/* SYSCTL_IMASK[LFOSCGOOD] Bits */
#define SYSCTL_IMASK_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */
#define SYSCTL_IMASK_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Enable or disable the LFOSCGOOD
interrupt. LFOSCGOOD indicates that
the LFOSC has started successfully. */
#define SYSCTL_IMASK_LFOSCGOOD_DISABLE ((uint32_t)0x00000000U) /* !< Interrupt disabled */
#define SYSCTL_IMASK_LFOSCGOOD_ENABLE ((uint32_t)0x00000001U) /* !< Interrupt enabled */
/* SYSCTL_IMASK[ANACLKERR] Bits */
#define SYSCTL_IMASK_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */
#define SYSCTL_IMASK_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */
#define SYSCTL_IMASK_ANACLKERR_DISABLE ((uint32_t)0x00000000U)
#define SYSCTL_IMASK_ANACLKERR_ENABLE ((uint32_t)0x00000002U)
/* SYSCTL_RIS Bits */
/* SYSCTL_RIS[LFOSCGOOD] Bits */
#define SYSCTL_RIS_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */
#define SYSCTL_RIS_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Raw status of the LFOSCGOOD
interrupt. */
#define SYSCTL_RIS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define SYSCTL_RIS_LFOSCGOOD_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */
/* SYSCTL_RIS[ANACLKERR] Bits */
#define SYSCTL_RIS_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */
#define SYSCTL_RIS_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */
#define SYSCTL_RIS_ANACLKERR_FALSE ((uint32_t)0x00000000U)
#define SYSCTL_RIS_ANACLKERR_TRUE ((uint32_t)0x00000002U)
/* SYSCTL_MIS Bits */
/* SYSCTL_MIS[LFOSCGOOD] Bits */
#define SYSCTL_MIS_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */
#define SYSCTL_MIS_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Masked status of the LFOSCGOOD
interrupt. */
#define SYSCTL_MIS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define SYSCTL_MIS_LFOSCGOOD_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */
/* SYSCTL_MIS[ANACLKERR] Bits */
#define SYSCTL_MIS_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */
#define SYSCTL_MIS_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */
#define SYSCTL_MIS_ANACLKERR_FALSE ((uint32_t)0x00000000U)
#define SYSCTL_MIS_ANACLKERR_TRUE ((uint32_t)0x00000002U)
/* SYSCTL_ISET Bits */
/* SYSCTL_ISET[LFOSCGOOD] Bits */
#define SYSCTL_ISET_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */
#define SYSCTL_ISET_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Set the LFOSCGOOD interrupt. */
#define SYSCTL_ISET_LFOSCGOOD_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */
#define SYSCTL_ISET_LFOSCGOOD_SET ((uint32_t)0x00000001U) /* !< Set interrupt */
/* SYSCTL_ISET[ANACLKERR] Bits */
#define SYSCTL_ISET_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */
#define SYSCTL_ISET_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */
#define SYSCTL_ISET_ANACLKERR_NO_EFFECT ((uint32_t)0x00000000U)
#define SYSCTL_ISET_ANACLKERR_SET ((uint32_t)0x00000002U)
/* SYSCTL_ICLR Bits */
/* SYSCTL_ICLR[LFOSCGOOD] Bits */
#define SYSCTL_ICLR_LFOSCGOOD_OFS (0) /* !< LFOSCGOOD Offset */
#define SYSCTL_ICLR_LFOSCGOOD_MASK ((uint32_t)0x00000001U) /* !< Clear the LFOSCGOOD interrupt. */
#define SYSCTL_ICLR_LFOSCGOOD_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h has no effect */
#define SYSCTL_ICLR_LFOSCGOOD_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */
/* SYSCTL_ICLR[ANACLKERR] Bits */
#define SYSCTL_ICLR_ANACLKERR_OFS (1) /* !< ANACLKERR Offset */
#define SYSCTL_ICLR_ANACLKERR_MASK ((uint32_t)0x00000002U) /* !< Analog Clocking Consistency Error */
#define SYSCTL_ICLR_ANACLKERR_NO_EFFECT ((uint32_t)0x00000000U)
#define SYSCTL_ICLR_ANACLKERR_CLR ((uint32_t)0x00000002U)
/* SYSCTL_NMIIIDX Bits */
/* SYSCTL_NMIIIDX[STAT] Bits */
#define SYSCTL_NMIIIDX_STAT_OFS (0) /* !< STAT Offset */
#define SYSCTL_NMIIIDX_STAT_MASK ((uint32_t)0x00000003U) /* !< The NMI interrupt index (NMIIIDX)
register generates a value
corresponding to the highest priority
pending NMI source. This value may
be used as an address offset for
fast, deterministic handling in the
NMI service routine. A read of the
NMIIIDX register will clear the
corresponding interrupt status in the
NMIRIS register. */
#define SYSCTL_NMIIIDX_STAT_NO_INTR ((uint32_t)0x00000000U) /* !< No NMI pending */
#define SYSCTL_NMIIIDX_STAT_BORLVL ((uint32_t)0x00000001U) /* !< BOR Threshold NMI pending */
#define SYSCTL_NMIIIDX_STAT_WWDT0 ((uint32_t)0x00000002U)
/* SYSCTL_NMIRIS Bits */
/* SYSCTL_NMIRIS[BORLVL] Bits */
#define SYSCTL_NMIRIS_BORLVL_OFS (0) /* !< BORLVL Offset */
#define SYSCTL_NMIRIS_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Raw status of the BORLVL NMI */
#define SYSCTL_NMIRIS_BORLVL_FALSE ((uint32_t)0x00000000U) /* !< No interrupt pending */
#define SYSCTL_NMIRIS_BORLVL_TRUE ((uint32_t)0x00000001U) /* !< Interrupt pending */
/* SYSCTL_NMIRIS[WWDT0] Bits */
#define SYSCTL_NMIRIS_WWDT0_OFS (1) /* !< WWDT0 Offset */
#define SYSCTL_NMIRIS_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */
#define SYSCTL_NMIRIS_WWDT0_FALSE ((uint32_t)0x00000000U)
#define SYSCTL_NMIRIS_WWDT0_TRUE ((uint32_t)0x00000002U)
/* SYSCTL_NMIISET Bits */
/* SYSCTL_NMIISET[BORLVL] Bits */
#define SYSCTL_NMIISET_BORLVL_OFS (0) /* !< BORLVL Offset */
#define SYSCTL_NMIISET_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Set the BORLVL NMI */
#define SYSCTL_NMIISET_BORLVL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */
#define SYSCTL_NMIISET_BORLVL_SET ((uint32_t)0x00000001U) /* !< Set interrupt */
/* SYSCTL_NMIISET[WWDT0] Bits */
#define SYSCTL_NMIISET_WWDT0_OFS (1) /* !< WWDT0 Offset */
#define SYSCTL_NMIISET_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */
#define SYSCTL_NMIISET_WWDT0_NO_EFFECT ((uint32_t)0x00000000U)
#define SYSCTL_NMIISET_WWDT0_SET ((uint32_t)0x00000002U)
/* SYSCTL_NMIICLR Bits */
/* SYSCTL_NMIICLR[BORLVL] Bits */
#define SYSCTL_NMIICLR_BORLVL_OFS (0) /* !< BORLVL Offset */
#define SYSCTL_NMIICLR_BORLVL_MASK ((uint32_t)0x00000001U) /* !< Clr the BORLVL NMI */
#define SYSCTL_NMIICLR_BORLVL_NO_EFFECT ((uint32_t)0x00000000U) /* !< Writing 0h hs no effect */
#define SYSCTL_NMIICLR_BORLVL_CLR ((uint32_t)0x00000001U) /* !< Clear interrupt */
/* SYSCTL_NMIICLR[WWDT0] Bits */
#define SYSCTL_NMIICLR_WWDT0_OFS (1) /* !< WWDT0 Offset */
#define SYSCTL_NMIICLR_WWDT0_MASK ((uint32_t)0x00000002U) /* !< Watch Dog 0 Fault */
#define SYSCTL_NMIICLR_WWDT0_NO_EFFECT ((uint32_t)0x00000000U)
#define SYSCTL_NMIICLR_WWDT0_CLR ((uint32_t)0x00000002U)
/* SYSCTL_SYSOSCCFG Bits */
/* SYSCTL_SYSOSCCFG[DISABLESTOP] Bits */
#define SYSCTL_SYSOSCCFG_DISABLESTOP_OFS (9) /* !< DISABLESTOP Offset */
#define SYSCTL_SYSOSCCFG_DISABLESTOP_MASK ((uint32_t)0x00000200U) /* !< DISABLESTOP sets the SYSOSC stop
mode enable/disable policy. When
operating in STOP mode, the SYSOSC
may be automatically disabled. When
set, ULPCLK will run from LFCLK in
STOP mode and SYSOSC will be disabled
to reduce power consumption. */
#define SYSCTL_SYSOSCCFG_DISABLESTOP_DISABLE ((uint32_t)0x00000000U) /* !< Do not disable SYSOSC in STOP mode */
#define SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE ((uint32_t)0x00000200U) /* !< Disable SYSOSC in STOP mode and
source ULPCLK from LFCLK */
/* SYSCTL_SYSOSCCFG[BLOCKASYNCALL] Bits */
#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_OFS (16) /* !< BLOCKASYNCALL Offset */
#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_MASK ((uint32_t)0x00010000U) /* !< BLOCKASYNCALL may be used to mask
block all asynchronous fast clock
requests, preventing hardware from
dynamically changing the active clock
configuration when operating in a
given mode. */
#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_DISABLE ((uint32_t)0x00000000U) /* !< Asynchronous fast clock requests
are controlled by the requesting
peripheral */
#define SYSCTL_SYSOSCCFG_BLOCKASYNCALL_ENABLE ((uint32_t)0x00010000U) /* !< All asynchronous fast clock
requests are blocked */
/* SYSCTL_SYSOSCCFG[DISABLE] Bits */
#define SYSCTL_SYSOSCCFG_DISABLE_OFS (10) /* !< DISABLE Offset */
#define SYSCTL_SYSOSCCFG_DISABLE_MASK ((uint32_t)0x00000400U) /* !< DISABLE sets the SYSOSC
enable/disable policy. SYSOSC may be
powered off in RUN, SLEEP, and STOP
modes to reduce power consumption.
When SYSOSC is disabled, MCLK and
ULPCLK are sourced from LFCLK. */
#define SYSCTL_SYSOSCCFG_DISABLE_DISABLE ((uint32_t)0x00000000U) /* !< Do not disable SYSOSC */
#define SYSCTL_SYSOSCCFG_DISABLE_ENABLE ((uint32_t)0x00000400U) /* !< Disable SYSOSC immediately and
source MCLK and ULPCLK from LFCLK */
/* SYSCTL_SYSOSCCFG[FASTCPUEVENT] Bits */
#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_OFS (17) /* !< FASTCPUEVENT Offset */
#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_MASK ((uint32_t)0x00020000U) /* !< FASTCPUEVENT may be used to assert
a fast clock request when an
interrupt is asserted to the CPU,
reducing interrupt latency. */
#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_DISABLE ((uint32_t)0x00000000U) /* !< An interrupt to the CPU will not
assert a fast clock request */
#define SYSCTL_SYSOSCCFG_FASTCPUEVENT_ENABLE ((uint32_t)0x00020000U) /* !< An interrupt to the CPU will assert
a fast clock request */
/* SYSCTL_SYSOSCCFG[FREQ] Bits */
#define SYSCTL_SYSOSCCFG_FREQ_OFS (0) /* !< FREQ Offset */
#define SYSCTL_SYSOSCCFG_FREQ_MASK ((uint32_t)0x00000003U) /* !< Target operating frequency for the
system oscillator (SYSOSC) */
#define SYSCTL_SYSOSCCFG_FREQ_SYSOSCBASE ((uint32_t)0x00000000U) /* !< Base frequency (32MHz) */
#define SYSCTL_SYSOSCCFG_FREQ_SYSOSC4M ((uint32_t)0x00000001U) /* !< Low frequency (4MHz) */
#define SYSCTL_SYSOSCCFG_FREQ_SYSOSCUSER ((uint32_t)0x00000002U) /* !< User-trimmed frequency (16 or 24
MHz) */
/* SYSCTL_MCLKCFG Bits */
/* SYSCTL_MCLKCFG[USEMFTICK] Bits */
#define SYSCTL_MCLKCFG_USEMFTICK_OFS (12) /* !< USEMFTICK Offset */
#define SYSCTL_MCLKCFG_USEMFTICK_MASK ((uint32_t)0x00001000U) /* !< USEMFTICK specifies whether the
4MHz constant-rate clock (MFCLK) to
peripherals is enabled or disabled.
When enabled, MDIV must be disabled
(set to 0h=/1). */
#define SYSCTL_MCLKCFG_USEMFTICK_DISABLE ((uint32_t)0x00000000U) /* !< The 4MHz rate MFCLK to peripherals
is enabled */
#define SYSCTL_MCLKCFG_USEMFTICK_ENABLE ((uint32_t)0x00001000U) /* !< The 4MHz rate MFCLK to peripherals
is enabled. */
/* SYSCTL_MCLKCFG[MDIV] Bits */
#define SYSCTL_MCLKCFG_MDIV_OFS (0) /* !< MDIV Offset */
#define SYSCTL_MCLKCFG_MDIV_MASK ((uint32_t)0x0000000FU) /* !< MDIV may be used to divide the MCLK
frequency when MCLK is sourced from
SYSOSC. MDIV=0h corresponds to /1
(no divider). MDIV=1h corresponds to
/2 (divide-by-2). MDIV=Fh
corresponds to /16 (divide-by-16).
MDIV may be set between /1 and /16 on
an integer basis. */
/* SYSCTL_MCLKCFG[USEHSCLK] Bits */
#define SYSCTL_MCLKCFG_USEHSCLK_OFS (16) /* !< USEHSCLK Offset */
#define SYSCTL_MCLKCFG_USEHSCLK_MASK ((uint32_t)0x00010000U) /* !< USEHSCLK, together with USELFCLK,
sets the MCLK source policy. Set
USEHSCLK to use HSCLK (HFCLK or
SYSPLL) as the MCLK source in RUN and
SLEEP modes. */
#define SYSCTL_MCLKCFG_USEHSCLK_DISABLE ((uint32_t)0x00000000U) /* !< MCLK will not use the high speed
clock (HSCLK) */
#define SYSCTL_MCLKCFG_USEHSCLK_ENABLE ((uint32_t)0x00010000U) /* !< MCLK will use the high speed clock
(HSCLK) in RUN and SLEEP mode */
/* SYSCTL_MCLKCFG[USELFCLK] Bits */
#define SYSCTL_MCLKCFG_USELFCLK_OFS (20) /* !< USELFCLK Offset */
#define SYSCTL_MCLKCFG_USELFCLK_MASK ((uint32_t)0x00100000U) /* !< USELFCLK sets the MCLK source
policy. Set USELFCLK to use LFCLK as
the MCLK source. Note that setting
USELFCLK does not disable SYSOSC, and
SYSOSC remains available for direct
use by analog modules. */
#define SYSCTL_MCLKCFG_USELFCLK_DISABLE ((uint32_t)0x00000000U) /* !< MCLK will not use the low frequency
clock (LFCLK) */
#define SYSCTL_MCLKCFG_USELFCLK_ENABLE ((uint32_t)0x00100000U) /* !< MCLK will use the low frequency
clock (LFCLK) */
/* SYSCTL_MCLKCFG[STOPCLKSTBY] Bits */
#define SYSCTL_MCLKCFG_STOPCLKSTBY_OFS (21) /* !< STOPCLKSTBY Offset */
#define SYSCTL_MCLKCFG_STOPCLKSTBY_MASK ((uint32_t)0x00200000U) /* !< STOPCLKSTBY sets the STANDBY mode
policy (STANDBY0 or STANDBY1). When
set, ULPCLK and LFCLK are disabled to
all peripherals in STANDBY mode, with
the exception of TIMG0 and TIMG1
which continue to run. Wake-up is
only possible via an asynchronous
fast clock request. */
#define SYSCTL_MCLKCFG_STOPCLKSTBY_DISABLE ((uint32_t)0x00000000U) /* !< ULPCLK/LFCLK runs to all PD0
peripherals in STANDBY mode */
#define SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE ((uint32_t)0x00200000U) /* !< ULPCLK/LFCLK is disabled to all
peripherals in STANDBY mode except
TIMG0 and TIMG1 */
/* SYSCTL_MCLKCFG[MCLKDEADCHK] Bits */
#define SYSCTL_MCLKCFG_MCLKDEADCHK_OFS (22) /* !< MCLKDEADCHK Offset */
#define SYSCTL_MCLKCFG_MCLKDEADCHK_MASK ((uint32_t)0x00400000U) /* !< MCLKDEADCHK enables or disables the
continuous MCLK dead check monitor.
LFCLK must be running before
MCLKDEADCHK is enabled. */
#define SYSCTL_MCLKCFG_MCLKDEADCHK_DISABLE ((uint32_t)0x00000000U) /* !< The MCLK dead check monitor is
disabled */
#define SYSCTL_MCLKCFG_MCLKDEADCHK_ENABLE ((uint32_t)0x00400000U) /* !< The MCLK dead check monitor is
enabled */
/* SYSCTL_HSCLKEN Bits */
/* SYSCTL_HSCLKEN[USEEXTHFCLK] Bits */
#define SYSCTL_HSCLKEN_USEEXTHFCLK_OFS (16) /* !< USEEXTHFCLK Offset */
#define SYSCTL_HSCLKEN_USEEXTHFCLK_MASK ((uint32_t)0x00010000U) /* !< USEEXTHFCLK selects the HFCLK_IN
digital clock input to be the source
for HFCLK. When disabled, HFXT is
the HFCLK source and HFXTEN may be
set. Do not set HFXTEN and
USEEXTHFCLK simultaneously. */
#define SYSCTL_HSCLKEN_USEEXTHFCLK_DISABLE ((uint32_t)0x00000000U) /* !< Use HFXT as the HFCLK source */
#define SYSCTL_HSCLKEN_USEEXTHFCLK_ENABLE ((uint32_t)0x00010000U) /* !< Use the HFCLK_IN digital clock
input as the HFCLK source */
/* SYSCTL_GENCLKCFG Bits */
/* SYSCTL_GENCLKCFG[HFCLK4MFPCLKDIV] Bits */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_OFS (12) /* !< HFCLK4MFPCLKDIV Offset */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_MASK ((uint32_t)0x0000F000U) /* !< HFCLK4MFPCLKDIV selects the divider
applied to HFCLK when HFCLK is used
as the MFPCLK source. Integer
dividers from /1 to /16 may be
selected. */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV1 ((uint32_t)0x00000000U) /* !< HFCLK is not divided before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV2 ((uint32_t)0x00001000U) /* !< HFCLK is divided by 2 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV3 ((uint32_t)0x00002000U) /* !< HFCLK is divided by 3 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV4 ((uint32_t)0x00003000U) /* !< HFCLK is divided by 4 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV5 ((uint32_t)0x00004000U) /* !< HFCLK is divided by 5 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV6 ((uint32_t)0x00005000U) /* !< HFCLK is divided by 6 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV7 ((uint32_t)0x00006000U) /* !< HFCLK is divided by 7 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV8 ((uint32_t)0x00007000U) /* !< HFCLK is divided by 8 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV9 ((uint32_t)0x00008000U) /* !< HFCLK is divided by 9 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV10 ((uint32_t)0x00009000U) /* !< HFCLK is divided by 10 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV11 ((uint32_t)0x0000A000U) /* !< HFCLK is divided by 11 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV12 ((uint32_t)0x0000B000U) /* !< HFCLK is divided by 12 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV13 ((uint32_t)0x0000C000U) /* !< HFCLK is divided by 13 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV14 ((uint32_t)0x0000D000U) /* !< HFCLK is divided by 14 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV15 ((uint32_t)0x0000E000U) /* !< HFCLK is divided by 15 before being
used for MFPCLK */
#define SYSCTL_GENCLKCFG_HFCLK4MFPCLKDIV_DIV16 ((uint32_t)0x0000F000U) /* !< HFCLK is divided by 16 before being
used for MFPCLK */
/* SYSCTL_GENCLKCFG[MFPCLKSRC] Bits */
#define SYSCTL_GENCLKCFG_MFPCLKSRC_OFS (9) /* !< MFPCLKSRC Offset */
#define SYSCTL_GENCLKCFG_MFPCLKSRC_MASK ((uint32_t)0x00000200U) /* !< MFPCLKSRC selects the MFPCLK
(middle frequency precision clock)
source. */
#define SYSCTL_GENCLKCFG_MFPCLKSRC_SYSOSC ((uint32_t)0x00000000U) /* !< MFPCLK is sourced from SYSOSC */
#define SYSCTL_GENCLKCFG_MFPCLKSRC_HFCLK ((uint32_t)0x00000200U) /* !< MFPCLK is sourced from HFCLK */
/* SYSCTL_GENCLKCFG[FCCTRIGCNT] Bits */
#define SYSCTL_GENCLKCFG_FCCTRIGCNT_OFS (24) /* !< FCCTRIGCNT Offset */
#define SYSCTL_GENCLKCFG_FCCTRIGCNT_MASK ((uint32_t)0x1F000000U) /* !< FCCTRIGCNT specifies the number of
trigger clock periods in the trigger
window. FCCTRIGCNT=0h (one trigger
clock period) up to 1Fh (32 trigger
clock periods) may be specified. */
/* SYSCTL_GENCLKCFG[ANACPUMPCFG] Bits */
#define SYSCTL_GENCLKCFG_ANACPUMPCFG_OFS (22) /* !< ANACPUMPCFG Offset */
#define SYSCTL_GENCLKCFG_ANACPUMPCFG_MASK ((uint32_t)0x00C00000U) /* !< ANACPUMPCFG selects the analog mux
charge pump (VBOOST) enable method. */
#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONDEMAND ((uint32_t)0x00000000U) /* !< VBOOST is enabled on request from a
COMP, GPAMP, or OPA */
#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONACTIVE ((uint32_t)0x00400000U) /* !< VBOOST is enabled when the device
is in RUN or SLEEP mode, or when a
COMP/GPAMP/OPA is enabled */
#define SYSCTL_GENCLKCFG_ANACPUMPCFG_ONALWAYS ((uint32_t)0x00800000U) /* !< VBOOST is always enabled */
/* SYSCTL_GENCLKCFG[FCCSELCLK] Bits */
#define SYSCTL_GENCLKCFG_FCCSELCLK_OFS (16) /* !< FCCSELCLK Offset */
#define SYSCTL_GENCLKCFG_FCCSELCLK_MASK ((uint32_t)0x000F0000U) /* !< FCCSELCLK selectes the frequency
clock counter (FCC) clock source. */
#define SYSCTL_GENCLKCFG_FCCSELCLK_MCLK ((uint32_t)0x00000000U) /* !< FCC clock is MCLK */
#define SYSCTL_GENCLKCFG_FCCSELCLK_SYSOSC ((uint32_t)0x00010000U) /* !< FCC clock is SYSOSC */
#define SYSCTL_GENCLKCFG_FCCSELCLK_HFCLK ((uint32_t)0x00020000U) /* !< FCC clock is HFCLK */
#define SYSCTL_GENCLKCFG_FCCSELCLK_EXTCLK ((uint32_t)0x00030000U) /* !< FCC clock is the CLK_OUT selection */
#define SYSCTL_GENCLKCFG_FCCSELCLK_FCCIN ((uint32_t)0x00070000U) /* !< FCC clock is the FCCIN external
input */
/* SYSCTL_GENCLKCFG[FCCTRIGSRC] Bits */
#define SYSCTL_GENCLKCFG_FCCTRIGSRC_OFS (20) /* !< FCCTRIGSRC Offset */
#define SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK ((uint32_t)0x00100000U) /* !< FCCTRIGSRC selects the frequency
clock counter (FCC) trigger source. */
#define SYSCTL_GENCLKCFG_FCCTRIGSRC_EXTPIN ((uint32_t)0x00000000U) /* !< FCC trigger is the external pin */
#define SYSCTL_GENCLKCFG_FCCTRIGSRC_LFCLK ((uint32_t)0x00100000U) /* !< FCC trigger is the LFCLK */
/* SYSCTL_GENCLKCFG[FCCLVLTRIG] Bits */
#define SYSCTL_GENCLKCFG_FCCLVLTRIG_OFS (21) /* !< FCCLVLTRIG Offset */
#define SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK ((uint32_t)0x00200000U) /* !< FCCLVLTRIG selects the frequency
clock counter (FCC) trigger mode. */
#define SYSCTL_GENCLKCFG_FCCLVLTRIG_RISE2RISE ((uint32_t)0x00000000U) /* !< Rising edge to rising edge
triggered */
#define SYSCTL_GENCLKCFG_FCCLVLTRIG_LEVEL ((uint32_t)0x00200000U) /* !< Level triggered */
/* SYSCTL_GENCLKCFG[EXCLKSRC] Bits */
#define SYSCTL_GENCLKCFG_EXCLKSRC_OFS (0) /* !< EXCLKSRC Offset */
#define SYSCTL_GENCLKCFG_EXCLKSRC_MASK ((uint32_t)0x00000007U) /* !< EXCLKSRC selects the source for the
CLK_OUT external clock output block.
ULPCLK and MFPCLK require the CLK_OUT
divider (EXCLKDIVEN) to be enabled */
#define SYSCTL_GENCLKCFG_EXCLKSRC_SYSOSC ((uint32_t)0x00000000U) /* !< CLK_OUT is SYSOSC */
#define SYSCTL_GENCLKCFG_EXCLKSRC_ULPCLK ((uint32_t)0x00000001U) /* !< CLK_OUT is ULPCLK (EXCLKDIVEN must
be enabled) */
#define SYSCTL_GENCLKCFG_EXCLKSRC_LFCLK ((uint32_t)0x00000002U) /* !< CLK_OUT is LFCLK */
#define SYSCTL_GENCLKCFG_EXCLKSRC_MFPCLK ((uint32_t)0x00000003U) /* !< CLK_OUT is MFPCLK (EXCLKDIVEN must
be enabled) */
#define SYSCTL_GENCLKCFG_EXCLKSRC_HFCLK ((uint32_t)0x00000004U) /* !< CLK_OUT is HFCLK */
/* SYSCTL_GENCLKCFG[EXCLKDIVVAL] Bits */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_OFS (4) /* !< EXCLKDIVVAL Offset */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_MASK ((uint32_t)0x00000070U) /* !< EXCLKDIVVAL selects the divider
value for the divider in the CLK_OUT
external clock output block. */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV2 ((uint32_t)0x00000000U) /* !< CLK_OUT source is divided by 2 */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV4 ((uint32_t)0x00000010U) /* !< CLK_OUT source is divided by 4 */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV6 ((uint32_t)0x00000020U) /* !< CLK_OUT source is divided by 6 */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV8 ((uint32_t)0x00000030U) /* !< CLK_OUT source is divided by 8 */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV10 ((uint32_t)0x00000040U) /* !< CLK_OUT source is divided by 10 */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV12 ((uint32_t)0x00000050U) /* !< CLK_OUT source is divided by 12 */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV14 ((uint32_t)0x00000060U) /* !< CLK_OUT source is divided by 14 */
#define SYSCTL_GENCLKCFG_EXCLKDIVVAL_DIV16 ((uint32_t)0x00000070U) /* !< CLK_OUT source is divided by 16 */
/* SYSCTL_GENCLKCFG[EXCLKDIVEN] Bits */
#define SYSCTL_GENCLKCFG_EXCLKDIVEN_OFS (7) /* !< EXCLKDIVEN Offset */
#define SYSCTL_GENCLKCFG_EXCLKDIVEN_MASK ((uint32_t)0x00000080U) /* !< EXCLKDIVEN enables or disables the
divider function of the CLK_OUT
external clock output block. */
#define SYSCTL_GENCLKCFG_EXCLKDIVEN_PASSTHRU ((uint32_t)0x00000000U) /* !< CLock divider is disabled
(passthrough, EXCLKDIVVAL is not
applied) */
#define SYSCTL_GENCLKCFG_EXCLKDIVEN_ENABLE ((uint32_t)0x00000080U) /* !< Clock divider is enabled
(EXCLKDIVVAL is applied) */
/* SYSCTL_GENCLKEN Bits */
/* SYSCTL_GENCLKEN[EXCLKEN] Bits */
#define SYSCTL_GENCLKEN_EXCLKEN_OFS (0) /* !< EXCLKEN Offset */
#define SYSCTL_GENCLKEN_EXCLKEN_MASK ((uint32_t)0x00000001U) /* !< EXCLKEN enables the CLK_OUT
external clock output block. */
#define SYSCTL_GENCLKEN_EXCLKEN_DISABLE ((uint32_t)0x00000000U) /* !< CLK_OUT block is disabled */
#define SYSCTL_GENCLKEN_EXCLKEN_ENABLE ((uint32_t)0x00000001U) /* !< CLK_OUT block is enabled */
/* SYSCTL_GENCLKEN[MFPCLKEN] Bits */
#define SYSCTL_GENCLKEN_MFPCLKEN_OFS (4) /* !< MFPCLKEN Offset */
#define SYSCTL_GENCLKEN_MFPCLKEN_MASK ((uint32_t)0x00000010U) /* !< MFPCLKEN enables the middle
frequency precision clock (MFPCLK). */
#define SYSCTL_GENCLKEN_MFPCLKEN_DISABLE ((uint32_t)0x00000000U) /* !< MFPCLK is disabled */
#define SYSCTL_GENCLKEN_MFPCLKEN_ENABLE ((uint32_t)0x00000010U) /* !< MFPCLK is enabled */
/* SYSCTL_PMODECFG Bits */
/* SYSCTL_PMODECFG[DSLEEP] Bits */
#define SYSCTL_PMODECFG_DSLEEP_OFS (0) /* !< DSLEEP Offset */
#define SYSCTL_PMODECFG_DSLEEP_MASK ((uint32_t)0x00000003U) /* !< DSLEEP selects the operating mode
to enter upon a DEEPSLEEP request
from the CPU. */
#define SYSCTL_PMODECFG_DSLEEP_STOP ((uint32_t)0x00000000U) /* !< STOP mode is entered */
#define SYSCTL_PMODECFG_DSLEEP_STANDBY ((uint32_t)0x00000001U) /* !< STANDBY mode is entered */
#define SYSCTL_PMODECFG_DSLEEP_SHUTDOWN ((uint32_t)0x00000002U) /* !< SHUTDOWN mode is entered */
/* SYSCTL_FCC Bits */
/* SYSCTL_FCC[DATA] Bits */
#define SYSCTL_FCC_DATA_OFS (0) /* !< DATA Offset */
#define SYSCTL_FCC_DATA_MASK ((uint32_t)0x003FFFFFU) /* !< Frequency clock counter (FCC) count
value. */
/* SYSCTL_SRAMBOUNDARY Bits */
/* SYSCTL_SRAMBOUNDARY[ADDR] Bits */
#define SYSCTL_SRAMBOUNDARY_ADDR_OFS (5) /* !< ADDR Offset */
#define SYSCTL_SRAMBOUNDARY_ADDR_MASK ((uint32_t)0x000FFFE0U) /* !< SRAM boundary configuration. The
value configured into this acts such
that: SRAM accesses to addresses less
than or equal value will be RW only.
SRAM accesses to addresses greater
than value will be RX only. Value of
0 is not valid (system will have no
stack). If set to 0, the system acts
as if the entire SRAM is RWX. Any
non-zero value can be configured,
including a value = SRAM size. */
/* SYSCTL_SYSTEMCFG Bits */
/* SYSCTL_SYSTEMCFG[KEY] Bits */
#define SYSCTL_SYSTEMCFG_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_SYSTEMCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 1Bh (27) must be
written to KEY together with contents
to be updated. Reads as 0 */
#define SYSCTL_SYSTEMCFG_KEY_VALUE ((uint32_t)0x1B000000U) /* !< Issue write */
/* SYSCTL_SYSTEMCFG[WWDTLP0RSTDIS] Bits */
#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_OFS (0) /* !< WWDTLP0RSTDIS Offset */
#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_MASK ((uint32_t)0x00000001U) /* !< WWDTLP0RSTDIS specifies whether a
WWDT Error Event will trigger a
BOOTRST or an NMI. */
#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_FALSE ((uint32_t)0x00000000U) /* !< WWDTLP0 Error Event will trigger a
BOOTRST */
#define SYSCTL_SYSTEMCFG_WWDTLP0RSTDIS_TRUE ((uint32_t)0x00000001U) /* !< WWDTLP0 Error Event will trigger an
NMI */
/* SYSCTL_BEEPCFG Bits */
/* SYSCTL_BEEPCFG[FREQ] Bits */
#define SYSCTL_BEEPCFG_FREQ_OFS (4) /* !< FREQ Offset */
#define SYSCTL_BEEPCFG_FREQ_MASK ((uint32_t)0x00000030U) /* !< Beeper Output Frequency
Configuration */
#define SYSCTL_BEEPCFG_FREQ_8KHZ ((uint32_t)0x00000000U) /* !< Beeper runs at 8KHz */
#define SYSCTL_BEEPCFG_FREQ_4KHZ ((uint32_t)0x00000010U) /* !< Beeper runs at 4KHz */
#define SYSCTL_BEEPCFG_FREQ_2KHZ ((uint32_t)0x00000020U) /* !< Beeper runs at 2KHz */
#define SYSCTL_BEEPCFG_FREQ_1KHZ ((uint32_t)0x00000030U) /* !< Beeper runs at 1KHz */
/* SYSCTL_BEEPCFG[EN] Bits */
#define SYSCTL_BEEPCFG_EN_OFS (0) /* !< EN Offset */
#define SYSCTL_BEEPCFG_EN_MASK ((uint32_t)0x00000001U) /* !< Beeper Output Enable */
#define SYSCTL_BEEPCFG_EN_DISABLE ((uint32_t)0x00000000U) /* !< Beeper Output Disabled */
#define SYSCTL_BEEPCFG_EN_ENABLE ((uint32_t)0x00000001U) /* !< Beeper Output Enabled */
/* SYSCTL_WRITELOCK Bits */
/* SYSCTL_WRITELOCK[ACTIVE] Bits */
#define SYSCTL_WRITELOCK_ACTIVE_OFS (0) /* !< ACTIVE Offset */
#define SYSCTL_WRITELOCK_ACTIVE_MASK ((uint32_t)0x00000001U) /* !< ACTIVE controls whether critical
SYSCTL registers are write protected
or not. */
#define SYSCTL_WRITELOCK_ACTIVE_DISABLE ((uint32_t)0x00000000U) /* !< Allow writes to lockable registers */
#define SYSCTL_WRITELOCK_ACTIVE_ENABLE ((uint32_t)0x00000001U) /* !< Disallow writes to lockable
registers */
/* SYSCTL_CLKSTATUS Bits */
/* SYSCTL_CLKSTATUS[LFOSCGOOD] Bits */
#define SYSCTL_CLKSTATUS_LFOSCGOOD_OFS (11) /* !< LFOSCGOOD Offset */
#define SYSCTL_CLKSTATUS_LFOSCGOOD_MASK ((uint32_t)0x00000800U) /* !< LFOSCGOOD indicates when the LFOSC
startup has completed and the LFOSC
is ready for use. */
#define SYSCTL_CLKSTATUS_LFOSCGOOD_FALSE ((uint32_t)0x00000000U) /* !< LFOSC is not ready */
#define SYSCTL_CLKSTATUS_LFOSCGOOD_TRUE ((uint32_t)0x00000800U) /* !< LFOSC is ready */
/* SYSCTL_CLKSTATUS[ANACLKERR] Bits */
#define SYSCTL_CLKSTATUS_ANACLKERR_OFS (31) /* !< ANACLKERR Offset */
#define SYSCTL_CLKSTATUS_ANACLKERR_MASK ((uint32_t)0x80000000U) /* !< ANACLKERR is set when the device
clock configuration does not support
an enabled analog peripheral mode and
the analog peripheral may not be
functioning as expected. */
#define SYSCTL_CLKSTATUS_ANACLKERR_FALSE ((uint32_t)0x00000000U) /* !< No analog clock errors detected */
#define SYSCTL_CLKSTATUS_ANACLKERR_TRUE ((uint32_t)0x80000000U) /* !< Analog clock error detected */
/* SYSCTL_CLKSTATUS[HSCLKMUX] Bits */
#define SYSCTL_CLKSTATUS_HSCLKMUX_OFS (4) /* !< HSCLKMUX Offset */
#define SYSCTL_CLKSTATUS_HSCLKMUX_MASK ((uint32_t)0x00000010U) /* !< HSCLKMUX indicates if MCLK is
currently sourced from the high-speed
clock (HSCLK). */
#define SYSCTL_CLKSTATUS_HSCLKMUX_SYSOSC ((uint32_t)0x00000000U) /* !< MCLK is not sourced from HSCLK */
#define SYSCTL_CLKSTATUS_HSCLKMUX_HSCLK ((uint32_t)0x00000010U) /* !< MCLK is sourced from HSCLK */
/* SYSCTL_CLKSTATUS[LFCLKMUX] Bits */
#define SYSCTL_CLKSTATUS_LFCLKMUX_OFS (6) /* !< LFCLKMUX Offset */
#define SYSCTL_CLKSTATUS_LFCLKMUX_MASK ((uint32_t)0x000000C0U) /* !< LFCLKMUX indicates if LFCLK is
sourced from the internal LFOSC, the
low frequency crystal (LFXT), or the
LFCLK_IN digital clock input. */
#define SYSCTL_CLKSTATUS_LFCLKMUX_LFOSC ((uint32_t)0x00000000U) /* !< LFCLK is sourced from the internal
LFOSC */
#define SYSCTL_CLKSTATUS_LFCLKMUX_LFXT ((uint32_t)0x00000040U) /* !< LFCLK is sourced from the LFXT
(crystal) */
#define SYSCTL_CLKSTATUS_LFCLKMUX_EXLF ((uint32_t)0x00000080U) /* !< LFCLK is sourced from LFCLK_IN
(external digital clock input) */
/* SYSCTL_CLKSTATUS[SYSOSCFREQ] Bits */
#define SYSCTL_CLKSTATUS_SYSOSCFREQ_OFS (0) /* !< SYSOSCFREQ Offset */
#define SYSCTL_CLKSTATUS_SYSOSCFREQ_MASK ((uint32_t)0x00000003U) /* !< SYSOSCFREQ indicates the current
SYSOSC operating frequency. */
#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC32M ((uint32_t)0x00000000U) /* !< SYSOSC is at base frequency (32MHz) */
#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSC4M ((uint32_t)0x00000001U) /* !< SYSOSC is at low frequency (4MHz) */
#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCUSER ((uint32_t)0x00000002U) /* !< SYSOSC is at the user-trimmed
frequency (16 or 24MHz) */
#define SYSCTL_CLKSTATUS_SYSOSCFREQ_SYSOSCTURBO ((uint32_t)0x00000003U) /* !< Reserved */
/* SYSCTL_CLKSTATUS[FCLMODE] Bits */
#define SYSCTL_CLKSTATUS_FCLMODE_OFS (24) /* !< FCLMODE Offset */
#define SYSCTL_CLKSTATUS_FCLMODE_MASK ((uint32_t)0x01000000U) /* !< FCLMODE indicates if the SYSOSC
frequency correction loop (FCL) is
enabled. */
#define SYSCTL_CLKSTATUS_FCLMODE_DISABLED ((uint32_t)0x00000000U) /* !< SYSOSC FCL is disabled */
#define SYSCTL_CLKSTATUS_FCLMODE_ENABLED ((uint32_t)0x01000000U) /* !< SYSOSC FCL is enabled */
/* SYSCTL_CLKSTATUS[CURMCLKSEL] Bits */
#define SYSCTL_CLKSTATUS_CURMCLKSEL_OFS (17) /* !< CURMCLKSEL Offset */
#define SYSCTL_CLKSTATUS_CURMCLKSEL_MASK ((uint32_t)0x00020000U) /* !< CURMCLKSEL indicates if MCLK is
currently sourced from LFCLK. */
#define SYSCTL_CLKSTATUS_CURMCLKSEL_NOTLFCLK ((uint32_t)0x00000000U) /* !< MCLK is not sourced from LFCLK */
#define SYSCTL_CLKSTATUS_CURMCLKSEL_LFCLK ((uint32_t)0x00020000U) /* !< MCLK is sourced from LFCLK */
/* SYSCTL_CLKSTATUS[FCCDONE] Bits */
#define SYSCTL_CLKSTATUS_FCCDONE_OFS (25) /* !< FCCDONE Offset */
#define SYSCTL_CLKSTATUS_FCCDONE_MASK ((uint32_t)0x02000000U) /* !< FCCDONE indicates when a frequency
clock counter capture is complete. */
#define SYSCTL_CLKSTATUS_FCCDONE_NOTDONE ((uint32_t)0x00000000U) /* !< FCC capture is not done */
#define SYSCTL_CLKSTATUS_FCCDONE_DONE ((uint32_t)0x02000000U) /* !< FCC capture is done */
/* SYSCTL_SYSSTATUS Bits */
/* SYSCTL_SYSSTATUS[SHDNIOLOCK] Bits */
#define SYSCTL_SYSSTATUS_SHDNIOLOCK_OFS (14) /* !< SHDNIOLOCK Offset */
#define SYSCTL_SYSSTATUS_SHDNIOLOCK_MASK ((uint32_t)0x00004000U) /* !< SHDNIOLOCK indicates when IO is
locked due to SHUTDOWN */
#define SYSCTL_SYSSTATUS_SHDNIOLOCK_FALSE ((uint32_t)0x00000000U) /* !< IO IS NOT Locked due to SHUTDOWN */
#define SYSCTL_SYSSTATUS_SHDNIOLOCK_TRUE ((uint32_t)0x00004000U) /* !< IO IS Locked due to SHUTDOWN */
/* SYSCTL_SYSSTATUS[EXTRSTPINDIS] Bits */
#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_OFS (12) /* !< EXTRSTPINDIS Offset */
#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_MASK ((uint32_t)0x00001000U) /* !< EXTRSTPINDIS indicates when user
has disabled the use of external
reset pin */
#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_FALSE ((uint32_t)0x00000000U) /* !< External Reset Pin Enabled */
#define SYSCTL_SYSSTATUS_EXTRSTPINDIS_TRUE ((uint32_t)0x00001000U) /* !< External Reset Pin Disabled */
/* SYSCTL_SYSSTATUS[PMUIREFGOOD] Bits */
#define SYSCTL_SYSSTATUS_PMUIREFGOOD_OFS (6) /* !< PMUIREFGOOD Offset */
#define SYSCTL_SYSSTATUS_PMUIREFGOOD_MASK ((uint32_t)0x00000040U) /* !< PMUIREFGOOD is set by hardware when
the PMU current reference is ready. */
#define SYSCTL_SYSSTATUS_PMUIREFGOOD_FALSE ((uint32_t)0x00000000U) /* !< IREF is not ready */
#define SYSCTL_SYSSTATUS_PMUIREFGOOD_TRUE ((uint32_t)0x00000040U) /* !< IREF is ready */
/* SYSCTL_SYSSTATUS[SWDCFGDIS] Bits */
#define SYSCTL_SYSSTATUS_SWDCFGDIS_OFS (13) /* !< SWDCFGDIS Offset */
#define SYSCTL_SYSSTATUS_SWDCFGDIS_MASK ((uint32_t)0x00002000U) /* !< SWDCFGDIS indicates when user has
disabled the use of SWD Port */
#define SYSCTL_SYSSTATUS_SWDCFGDIS_FALSE ((uint32_t)0x00000000U) /* !< SWD Port Enabled */
#define SYSCTL_SYSSTATUS_SWDCFGDIS_TRUE ((uint32_t)0x00002000U) /* !< SWD Port Disabled */
/* SYSCTL_SYSSTATUS[ANACPUMPGOOD] Bits */
#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_OFS (5) /* !< ANACPUMPGOOD Offset */
#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_MASK ((uint32_t)0x00000020U) /* !< ANACPUMPGOOD is set by hardware
when the VBOOST analog mux charge
pump is ready. */
#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_FALSE ((uint32_t)0x00000000U) /* !< VBOOST is not ready */
#define SYSCTL_SYSSTATUS_ANACPUMPGOOD_TRUE ((uint32_t)0x00000020U) /* !< VBOOST is ready */
/* SYSCTL_SYSSTATUS[REBOOTATTEMPTS] Bits */
#define SYSCTL_SYSSTATUS_REBOOTATTEMPTS_OFS (30) /* !< REBOOTATTEMPTS Offset */
#define SYSCTL_SYSSTATUS_REBOOTATTEMPTS_MASK ((uint32_t)0xC0000000U) /* !< REBOOTATTEMPTS indicates the number
of boot attempts taken before the
user application starts. */
/* SYSCTL_SYSSTATUS[BORLVL] Bits */
#define SYSCTL_SYSSTATUS_BORLVL_OFS (4) /* !< BORLVL Offset */
#define SYSCTL_SYSSTATUS_BORLVL_MASK ((uint32_t)0x00000010U) /* !< BORLVL indicates if a BOR event
occured and the BOR threshold was
switched to BOR0 by hardware. */
#define SYSCTL_SYSSTATUS_BORLVL_FALSE ((uint32_t)0x00000000U) /* !< No BOR violation occured */
#define SYSCTL_SYSSTATUS_BORLVL_TRUE ((uint32_t)0x00000010U) /* !< A BOR violation occured and the BOR
threshold was switched to BOR0 */
/* SYSCTL_SYSSTATUS[BORCURTHRESHOLD] Bits */
#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_OFS (2) /* !< BORCURTHRESHOLD Offset */
#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_MASK ((uint32_t)0x0000000CU) /* !< BORCURTHRESHOLD indicates the
active brown-out reset supply monitor
configuration. */
#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORMIN ((uint32_t)0x00000000U) /* !< Default minimum threshold; a BOR0-
violation triggers a BOR */
#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL1 ((uint32_t)0x00000004U) /* !< A BOR1- violation generates a
BORLVL interrupt */
#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL2 ((uint32_t)0x00000008U) /* !< A BOR2- violation generates a
BORLVL interrupt */
#define SYSCTL_SYSSTATUS_BORCURTHRESHOLD_BORLEVEL3 ((uint32_t)0x0000000CU) /* !< A BOR3- violation generates a
BORLVL interrupt */
/* SYSCTL_RSTCAUSE Bits */
/* SYSCTL_RSTCAUSE[ID] Bits */
#define SYSCTL_RSTCAUSE_ID_OFS (0) /* !< ID Offset */
#define SYSCTL_RSTCAUSE_ID_MASK ((uint32_t)0x0000001FU) /* !< ID is a read-to-clear field which
indicates the lowest level reset
cause since the last read. */
#define SYSCTL_RSTCAUSE_ID_NORST ((uint32_t)0x00000000U) /* !< No reset since last read */
#define SYSCTL_RSTCAUSE_ID_PORHWFAIL ((uint32_t)0x00000001U) /* !< POR- violation, SHUTDNSTOREx or PMU
trim parity fault */
#define SYSCTL_RSTCAUSE_ID_POREXNRST ((uint32_t)0x00000002U) /* !< NRST triggered POR (&gt;1s hold) */
#define SYSCTL_RSTCAUSE_ID_PORSW ((uint32_t)0x00000003U) /* !< Software triggered POR */
#define SYSCTL_RSTCAUSE_ID_BORSUPPLY ((uint32_t)0x00000004U) /* !< BOR0- violation */
#define SYSCTL_RSTCAUSE_ID_BORWAKESHUTDN ((uint32_t)0x00000005U) /* !< SHUTDOWN mode exit */
#define SYSCTL_RSTCAUSE_ID_BOOTNONPMUPARITY ((uint32_t)0x00000008U) /* !< Non-PMU trim parity fault */
#define SYSCTL_RSTCAUSE_ID_BOOTCLKFAIL ((uint32_t)0x00000009U) /* !< Fatal clock failure */
#define SYSCTL_RSTCAUSE_ID_BOOTEXNRST ((uint32_t)0x0000000CU) /* !< NRST triggered BOOTRST (&lt;1s
hold) */
#define SYSCTL_RSTCAUSE_ID_BOOTSW ((uint32_t)0x0000000DU) /* !< Software triggered BOOTRST */
#define SYSCTL_RSTCAUSE_ID_SYSWWDT0 ((uint32_t)0x0000000EU) /* !< WWDT0 violation */
#define SYSCTL_RSTCAUSE_ID_SYSBSLEXIT ((uint32_t)0x00000010U) /* !< BSL exit */
#define SYSCTL_RSTCAUSE_ID_SYSBSLENTRY ((uint32_t)0x00000011U) /* !< BSL entry */
#define SYSCTL_RSTCAUSE_ID_SYSWWDT1 ((uint32_t)0x00000013U) /* !< WWDT1 violation */
#define SYSCTL_RSTCAUSE_ID_SYSFLASHECC ((uint32_t)0x00000014U) /* !< Flash uncorrectable ECC error */
#define SYSCTL_RSTCAUSE_ID_SYSCPULOCK ((uint32_t)0x00000015U) /* !< CPULOCK violation */
#define SYSCTL_RSTCAUSE_ID_SYSDBG ((uint32_t)0x0000001AU) /* !< Debug triggered SYSRST */
#define SYSCTL_RSTCAUSE_ID_SYSSW ((uint32_t)0x0000001BU) /* !< Software triggered SYSRST */
#define SYSCTL_RSTCAUSE_ID_CPUDBG ((uint32_t)0x0000001CU) /* !< Debug triggered CPURST */
#define SYSCTL_RSTCAUSE_ID_CPUSW ((uint32_t)0x0000001DU) /* !< Software triggered CPURST */
/* SYSCTL_RESETLEVEL Bits */
/* SYSCTL_RESETLEVEL[LEVEL] Bits */
#define SYSCTL_RESETLEVEL_LEVEL_OFS (0) /* !< LEVEL Offset */
#define SYSCTL_RESETLEVEL_LEVEL_MASK ((uint32_t)0x00000007U) /* !< LEVEL is used to specify the type
of reset to be issued when RESETCMD
is set to generate a software
triggered reset. */
#define SYSCTL_RESETLEVEL_LEVEL_CPU ((uint32_t)0x00000000U) /* !< Issue a SYSRST (CPU plus
peripherals only) */
#define SYSCTL_RESETLEVEL_LEVEL_BOOT ((uint32_t)0x00000001U) /* !< Issue a BOOTRST (CPU, peripherals,
and boot configuration routine) */
#define SYSCTL_RESETLEVEL_LEVEL_BOOTLOADERENTRY ((uint32_t)0x00000002U) /* !< Issue a SYSRST and enter the boot
strap loader (BSL) */
#define SYSCTL_RESETLEVEL_LEVEL_POR ((uint32_t)0x00000003U) /* !< Issue a power-on reset (POR) */
#define SYSCTL_RESETLEVEL_LEVEL_BOOTLOADEREXIT ((uint32_t)0x00000004U) /* !< Issue a SYSRST and exit the boot
strap loader (BSL) */
/* SYSCTL_RESETCMD Bits */
/* SYSCTL_RESETCMD[KEY] Bits */
#define SYSCTL_RESETCMD_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_RESETCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of E4h (228) must be
written to KEY together with GO to
trigger the reset. */
#define SYSCTL_RESETCMD_KEY_VALUE ((uint32_t)0xE4000000U) /* !< Issue reset */
/* SYSCTL_RESETCMD[GO] Bits */
#define SYSCTL_RESETCMD_GO_OFS (0) /* !< GO Offset */
#define SYSCTL_RESETCMD_GO_MASK ((uint32_t)0x00000001U) /* !< Execute the reset specified in
RESETLEVEL.LEVEL. Must be written
together with the KEY. */
#define SYSCTL_RESETCMD_GO_TRUE ((uint32_t)0x00000001U) /* !< Issue reset */
/* SYSCTL_BORTHRESHOLD Bits */
/* SYSCTL_BORTHRESHOLD[LEVEL] Bits */
#define SYSCTL_BORTHRESHOLD_LEVEL_OFS (0) /* !< LEVEL Offset */
#define SYSCTL_BORTHRESHOLD_LEVEL_MASK ((uint32_t)0x00000003U) /* !< LEVEL specifies the desired BOR
threshold and BOR mode. */
#define SYSCTL_BORTHRESHOLD_LEVEL_BORMIN ((uint32_t)0x00000000U) /* !< Default minimum threshold; a BOR0-
violation triggers a BOR */
#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL1 ((uint32_t)0x00000001U) /* !< A BOR1- violation generates a
BORLVL interrupt */
#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL2 ((uint32_t)0x00000002U) /* !< A BOR2- violation generates a
BORLVL interrupt */
#define SYSCTL_BORTHRESHOLD_LEVEL_BORLEVEL3 ((uint32_t)0x00000003U) /* !< A BOR3- violation generates a
BORLVL interrupt */
/* SYSCTL_BORCLRCMD Bits */
/* SYSCTL_BORCLRCMD[KEY] Bits */
#define SYSCTL_BORCLRCMD_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_BORCLRCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of C7h (199) must be
written to KEY together with GO to
trigger the clear and BOR threshold
change. */
#define SYSCTL_BORCLRCMD_KEY_VALUE ((uint32_t)0xC7000000U) /* !< Issue clear */
/* SYSCTL_BORCLRCMD[GO] Bits */
#define SYSCTL_BORCLRCMD_GO_OFS (0) /* !< GO Offset */
#define SYSCTL_BORCLRCMD_GO_MASK ((uint32_t)0x00000001U) /* !< GO clears any prior BOR violation
status indications and attempts to
change the active BOR mode to that
specified in the LEVEL field of the
BORTHRESHOLD register. */
#define SYSCTL_BORCLRCMD_GO_TRUE ((uint32_t)0x00000001U) /* !< Issue clear */
/* SYSCTL_SYSOSCFCLCTL Bits */
/* SYSCTL_SYSOSCFCLCTL[KEY] Bits */
#define SYSCTL_SYSOSCFCLCTL_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_SYSOSCFCLCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 2Ah (42) must be
written to KEY together with
SETUSEFCL to enable the FCL. */
#define SYSCTL_SYSOSCFCLCTL_KEY_VALUE ((uint32_t)0x2A000000U) /* !< Issue Command */
/* SYSCTL_SYSOSCFCLCTL[SETUSEFCL] Bits */
#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_OFS (0) /* !< SETUSEFCL Offset */
#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_MASK ((uint32_t)0x00000001U) /* !< Set SETUSEFCL to enable the
frequency correction loop in SYSOSC.
Once enabled, this state is locked
until the next BOOTRST. */
#define SYSCTL_SYSOSCFCLCTL_SETUSEFCL_TRUE ((uint32_t)0x00000001U) /* !< Enable the SYSOSC FCL */
/* SYSCTL_EXLFCTL Bits */
/* SYSCTL_EXLFCTL[KEY] Bits */
#define SYSCTL_EXLFCTL_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_EXLFCTL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value of 36h (54) must be
written to KEY together with
SETUSEEXLF to set SETUSEEXLF. */
#define SYSCTL_EXLFCTL_KEY_VALUE ((uint32_t)0x36000000U) /* !< Issue command */
/* SYSCTL_EXLFCTL[SETUSEEXLF] Bits */
#define SYSCTL_EXLFCTL_SETUSEEXLF_OFS (0) /* !< SETUSEEXLF Offset */
#define SYSCTL_EXLFCTL_SETUSEEXLF_MASK ((uint32_t)0x00000001U) /* !< Set SETUSEEXLF to switch LFCLK to
the LFCLK_IN digital clock input.
Once set, SETUSEEXLF remains set
until the next BOOTRST. */
#define SYSCTL_EXLFCTL_SETUSEEXLF_TRUE ((uint32_t)0x00000001U) /* !< Use LFCLK_IN as the LFCLK source */
/* SYSCTL_SHDNIOREL Bits */
/* SYSCTL_SHDNIOREL[KEY] Bits */
#define SYSCTL_SHDNIOREL_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_SHDNIOREL_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 91h must be written
to KEY together with RELEASE to set
RELEASE. */
#define SYSCTL_SHDNIOREL_KEY_VALUE ((uint32_t)0x91000000U) /* !< Issue command */
/* SYSCTL_SHDNIOREL[RELEASE] Bits */
#define SYSCTL_SHDNIOREL_RELEASE_OFS (0) /* !< RELEASE Offset */
#define SYSCTL_SHDNIOREL_RELEASE_MASK ((uint32_t)0x00000001U) /* !< Set RELEASE to release the IO after
a SHUTDOWN mode exit. */
#define SYSCTL_SHDNIOREL_RELEASE_TRUE ((uint32_t)0x00000001U) /* !< Release IO */
/* SYSCTL_EXRSTPIN Bits */
/* SYSCTL_EXRSTPIN[KEY] Bits */
#define SYSCTL_EXRSTPIN_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_EXRSTPIN_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 1Eh must be written
together with DISABLE to disable the
reset function. */
#define SYSCTL_EXRSTPIN_KEY_VALUE ((uint32_t)0x1E000000U) /* !< Issue command */
/* SYSCTL_EXRSTPIN[DISABLE] Bits */
#define SYSCTL_EXRSTPIN_DISABLE_OFS (0) /* !< DISABLE Offset */
#define SYSCTL_EXRSTPIN_DISABLE_MASK ((uint32_t)0x00000001U) /* !< Set DISABLE to disable the reset
function of the NRST pin. Once set,
this configuration is locked until
the next POR. */
#define SYSCTL_EXRSTPIN_DISABLE_FALSE ((uint32_t)0x00000000U) /* !< Reset function of NRST pin is
enabled */
#define SYSCTL_EXRSTPIN_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Reset function of NRST pin is
disabled */
/* SYSCTL_SYSSTATUSCLR Bits */
/* SYSCTL_SYSSTATUSCLR[KEY] Bits */
#define SYSCTL_SYSSTATUSCLR_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_SYSSTATUSCLR_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value CEh (206) must be
written to KEY together with ALLECC
to clear the ECC state. */
#define SYSCTL_SYSSTATUSCLR_KEY_VALUE ((uint32_t)0xCE000000U) /* !< Issue command */
/* SYSCTL_SYSSTATUSCLR[ALLECC] Bits */
#define SYSCTL_SYSSTATUSCLR_ALLECC_OFS (0) /* !< ALLECC Offset */
#define SYSCTL_SYSSTATUSCLR_ALLECC_MASK ((uint32_t)0x00000001U) /* !< Set ALLECC to clear all ECC related
SYSSTATUS indicators. */
#define SYSCTL_SYSSTATUSCLR_ALLECC_CLEAR ((uint32_t)0x00000001U) /* !< Clear ECC error state */
/* SYSCTL_SWDCFG Bits */
/* SYSCTL_SWDCFG[KEY] Bits */
#define SYSCTL_SWDCFG_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_SWDCFG_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 62h (98) must be
written to KEY together with DISBALE
to disable the SWD functions. */
#define SYSCTL_SWDCFG_KEY_VALUE ((uint32_t)0x62000000U) /* !< Issue command */
/* SYSCTL_SWDCFG[DISABLE] Bits */
#define SYSCTL_SWDCFG_DISABLE_OFS (0) /* !< DISABLE Offset */
#define SYSCTL_SWDCFG_DISABLE_MASK ((uint32_t)0x00000001U) /* !< Set DISABLE to disable the SWD
function on SWD pins, allowing the
SWD pins to be used as GPIO. */
#define SYSCTL_SWDCFG_DISABLE_TRUE ((uint32_t)0x00000001U) /* !< Disable SWD function on SWD pins */
/* SYSCTL_FCCCMD Bits */
/* SYSCTL_FCCCMD[KEY] Bits */
#define SYSCTL_FCCCMD_KEY_OFS (24) /* !< KEY Offset */
#define SYSCTL_FCCCMD_KEY_MASK ((uint32_t)0xFF000000U) /* !< The key value 0Eh (14) must be
written with GO to start a capture. */
#define SYSCTL_FCCCMD_KEY_VALUE ((uint32_t)0x0E000000U) /* !< Issue command */
/* SYSCTL_FCCCMD[GO] Bits */
#define SYSCTL_FCCCMD_GO_OFS (0) /* !< GO Offset */
#define SYSCTL_FCCCMD_GO_MASK ((uint32_t)0x00000001U) /* !< Set GO to start a capture with the
frequency clock counter (FCC). */
#define SYSCTL_FCCCMD_GO_TRUE ((uint32_t)0x00000001U)
/* SYSCTL_SHUTDNSTORE0 Bits */
/* SYSCTL_SHUTDNSTORE0[DATA] Bits */
#define SYSCTL_SHUTDNSTORE0_DATA_OFS (0) /* !< DATA Offset */
#define SYSCTL_SHUTDNSTORE0_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 0 */
/* SYSCTL_SHUTDNSTORE1 Bits */
/* SYSCTL_SHUTDNSTORE1[DATA] Bits */
#define SYSCTL_SHUTDNSTORE1_DATA_OFS (0) /* !< DATA Offset */
#define SYSCTL_SHUTDNSTORE1_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 1 */
/* SYSCTL_SHUTDNSTORE2 Bits */
/* SYSCTL_SHUTDNSTORE2[DATA] Bits */
#define SYSCTL_SHUTDNSTORE2_DATA_OFS (0) /* !< DATA Offset */
#define SYSCTL_SHUTDNSTORE2_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 2 */
/* SYSCTL_SHUTDNSTORE3 Bits */
/* SYSCTL_SHUTDNSTORE3[DATA] Bits */
#define SYSCTL_SHUTDNSTORE3_DATA_OFS (0) /* !< DATA Offset */
#define SYSCTL_SHUTDNSTORE3_DATA_MASK ((uint32_t)0x000000FFU) /* !< Shutdown storage byte 3 */
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_msp_peripherals_m0p_hw_sysctl_mspm0c110x__include */
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