init:初始框架
This commit is contained in:
SkyLi
@@ -0,0 +1,65 @@
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/*
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* Copyright (c) 2020, Texas Instruments Incorporated
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* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <ti/driverlib/dl_adc12.h>
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#ifdef __MSPM0_HAS_ADC12__
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void DL_ADC12_setClockConfig(
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ADC12_Regs *adc12, const DL_ADC12_ClockConfig *config)
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{
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DL_Common_updateReg(&adc12->ULLMEM.GPRCM.CLKCFG,
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(ADC12_CLKCFG_KEY_UNLOCK_W | (uint32_t) config->clockSel),
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(ADC12_CLKCFG_KEY_MASK | ADC12_CLKCFG_SAMPCLK_MASK));
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DL_Common_updateReg(&adc12->ULLMEM.CTL0, (uint32_t) config->divideRatio,
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ADC12_CTL0_SCLKDIV_MASK);
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adc12->ULLMEM.CLKFREQ = (uint32_t) config->freqRange;
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}
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void DL_ADC12_getClockConfig(
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const ADC12_Regs *adc12, DL_ADC12_ClockConfig *config)
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{
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uint32_t clockConfig =
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adc12->ULLMEM.GPRCM.CLKCFG & ADC12_CLKCFG_SAMPCLK_MASK;
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uint32_t divideRatio = adc12->ULLMEM.CTL0 & ADC12_CTL0_SCLKDIV_MASK;
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uint32_t freqRange = adc12->ULLMEM.CLKFREQ & ADC12_CLKFREQ_FRANGE_MASK;
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config->clockSel = (DL_ADC12_CLOCK)(clockConfig);
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config->divideRatio = (DL_ADC12_CLOCK_DIVIDE)(divideRatio);
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config->freqRange = (DL_ADC12_CLOCK_FREQ_RANGE)(freqRange);
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}
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#endif /* __MSPM0_HAS_ADC12__ */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,273 @@
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/*
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* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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#include <ti/driverlib/dl_aes.h>
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#ifdef __MSPM0_HAS_AES__
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static void DL_AES_loadDataWord(
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volatile uint32_t *pReg, const uint32_t *pData, uint8_t len);
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static const uint32_t *DL_AES_checkAlignmentAndReturnPointer(
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const uint8_t *ptr);
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DL_AES_STATUS DL_AES_setKey(
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AES_Regs *aes, const uint8_t *key, DL_AES_KEY_LENGTH keyLength)
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{
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DL_AES_STATUS status = DL_AES_STATUS_SUCCESS;
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const uint32_t *keyAligned;
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keyAligned = DL_AES_checkAlignmentAndReturnPointer(key);
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if (keyAligned != NULL) {
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DL_AES_setKeyAligned(aes, keyAligned, keyLength);
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} else {
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status = DL_AES_STATUS_UNALIGNED_ACCESS;
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}
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return status;
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}
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void DL_AES_setKeyAligned(
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AES_Regs *aes, const uint32_t *keyAligned, DL_AES_KEY_LENGTH keyLength)
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{
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uint8_t numWords;
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switch (keyLength) {
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case DL_AES_KEY_LENGTH_128:
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numWords = 4U;
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break;
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case DL_AES_KEY_LENGTH_256:
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numWords = 8U;
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break;
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default:
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numWords = 0U;
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break;
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}
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DL_AES_loadDataWord(&aes->AESAKEY, keyAligned, numWords);
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}
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DL_AES_STATUS DL_AES_loadDataIn(AES_Regs *aes, const uint8_t *data)
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{
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DL_AES_STATUS status = DL_AES_STATUS_SUCCESS;
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const uint32_t *dataAligned;
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dataAligned = DL_AES_checkAlignmentAndReturnPointer(data);
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if (dataAligned != NULL) {
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DL_AES_loadDataInAligned(aes, dataAligned);
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} else {
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status = DL_AES_STATUS_UNALIGNED_ACCESS;
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}
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return status;
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}
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void DL_AES_loadDataInAligned(AES_Regs *aes, const uint32_t *dataAligned)
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{
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DL_AES_loadDataWord(&aes->AESADIN, dataAligned, 4);
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}
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DL_AES_STATUS DL_AES_getDataOut(const AES_Regs *aes, uint8_t *data)
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{
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DL_AES_STATUS status = DL_AES_STATUS_SUCCESS;
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uint32_t *dataAligned;
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uint32_t address = (uint32_t) data;
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if ((address << 30) != 0x00000000u) {
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/* Unaligned access */
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status = DL_AES_STATUS_UNALIGNED_ACCESS;
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} else {
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/* Aligned Access */
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dataAligned = (uint32_t *) address;
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DL_AES_getDataOutAligned(aes, dataAligned);
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}
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return status;
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}
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void DL_AES_getDataOutAligned(const AES_Regs *aes, uint32_t *dataAligned)
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{
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uint8_t i;
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uint32_t *pData;
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volatile uint32_t const *aesPtr;
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pData = dataAligned;
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aesPtr = (volatile uint32_t const *) &(aes->AESADOUT);
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for (i = 0U; i < 4U; i++) {
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*pData = *aesPtr;
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pData++;
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}
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}
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DL_AES_STATUS DL_AES_loadXORDataIn(AES_Regs *aes, const uint8_t *data)
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{
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DL_AES_STATUS status = DL_AES_STATUS_SUCCESS;
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const uint32_t *dataAligned;
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dataAligned = DL_AES_checkAlignmentAndReturnPointer(data);
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if (dataAligned != NULL) {
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DL_AES_loadXORDataInAligned(aes, dataAligned);
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} else {
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status = DL_AES_STATUS_UNALIGNED_ACCESS;
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}
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return status;
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}
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void DL_AES_loadXORDataInAligned(AES_Regs *aes, const uint32_t *dataAligned)
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{
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DL_AES_loadDataWord(&aes->AESAXDIN, dataAligned, 4);
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}
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DL_AES_STATUS DL_AES_loadXORDataInWithoutTrigger(
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AES_Regs *aes, const uint8_t *data)
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{
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DL_AES_STATUS status = DL_AES_STATUS_SUCCESS;
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const uint32_t *dataAligned;
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dataAligned = DL_AES_checkAlignmentAndReturnPointer(data);
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if (dataAligned != NULL) {
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DL_AES_loadXORDataInWithoutTriggerAligned(aes, dataAligned);
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} else {
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status = DL_AES_STATUS_UNALIGNED_ACCESS;
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}
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return status;
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}
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void DL_AES_loadXORDataInWithoutTriggerAligned(
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AES_Regs *aes, const uint32_t *dataAligned)
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{
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DL_AES_loadDataWord(&aes->AESAXIN, dataAligned, 4);
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}
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DL_AES_STATUS DL_AES_xorData(
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const uint8_t *data, const uint8_t *xorData, uint8_t *xorOutputData)
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{
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DL_AES_STATUS status = DL_AES_STATUS_SUCCESS;
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uint32_t *dataAligned;
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uint32_t *xorDataAligned;
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uint32_t *xorOutputDataAligned;
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uint32_t dataAddress = (uint32_t) data;
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uint32_t xorDataAddress = (uint32_t) xorData;
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uint32_t xorOutputDataAddress = (uint32_t) xorOutputData;
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if (((dataAddress << 30) != 0x00000000u) ||
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((xorDataAddress << 30) != 0x00000000u) ||
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((xorOutputDataAddress << 30) != 0x00000000u)) {
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/* Unaligned access */
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status = DL_AES_STATUS_UNALIGNED_ACCESS;
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} else {
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/* Aligned Access */
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dataAligned = (uint32_t *) dataAddress;
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xorDataAligned = (uint32_t *) xorDataAddress;
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xorOutputDataAligned = (uint32_t *) xorOutputDataAddress;
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DL_AES_xorDataAligned(
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dataAligned, xorDataAligned, xorOutputDataAligned);
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}
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return status;
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}
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void DL_AES_xorDataAligned(uint32_t *dataAligned, uint32_t *xorDataAligned,
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uint32_t *xorOutputDataAligned)
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{
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uint8_t i;
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uint32_t *tempData = dataAligned;
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uint32_t *tempXorData = xorDataAligned;
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uint32_t *tempXorOutputData = xorOutputDataAligned;
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for (i = 0U; i < 4U; i++) {
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*tempXorOutputData = *tempData ^ *tempXorData;
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tempXorOutputData++;
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tempData++;
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tempXorData++;
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}
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}
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static void DL_AES_loadDataWord(
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volatile uint32_t *pReg, const uint32_t *pData, uint8_t len)
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{
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uint8_t i;
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const uint32_t *pTemp;
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pTemp = pData;
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for (i = 0; i < len; i++) {
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*pReg = *pTemp;
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pTemp++;
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}
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}
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static const uint32_t *DL_AES_checkAlignmentAndReturnPointer(
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const uint8_t *ptr)
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{
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uint32_t address = (uint32_t) ptr;
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const uint32_t *alignedPtr;
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if ((address << 30) != 0x00000000u) {
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/* Unaligned access */
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alignedPtr = NULL;
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} else {
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/* Aligned Access */
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alignedPtr = (const uint32_t *) address;
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}
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return alignedPtr;
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}
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bool DL_AES_saveConfiguration(const AES_Regs *aes, DL_AES_backupConfig *ptr)
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{
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bool stateSaved = !ptr->backupRdy;
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if (stateSaved) {
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ptr->controlWord0 = aes->AESACTL0;
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ptr->controlWord1 = aes->AESACTL1;
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ptr->interruptMask0 = aes->CPU_INT.IMASK;
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ptr->interruptMask1 = aes->DMA_TRIG0.IMASK;
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ptr->interruptMask2 = aes->DMA_TRIG1.IMASK;
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ptr->interruptMask3 = aes->DMA_TRIG2.IMASK;
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ptr->backupRdy = true;
|
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}
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return stateSaved;
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}
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bool DL_AES_restoreConfiguration(AES_Regs *aes, DL_AES_backupConfig *ptr)
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{
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bool stateRestored = ptr->backupRdy;
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if (stateRestored) {
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aes->AESACTL0 = ptr->controlWord0;
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aes->AESACTL1 = ptr->controlWord1;
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aes->CPU_INT.IMASK = ptr->interruptMask0;
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aes->DMA_TRIG0.IMASK = ptr->interruptMask1;
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aes->DMA_TRIG1.IMASK = ptr->interruptMask2;
|
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aes->DMA_TRIG2.IMASK = ptr->interruptMask3;
|
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ptr->backupRdy = false;
|
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}
|
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return stateRestored;
|
||||
}
|
||||
|
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#endif /* __MSPM0_HAS_AES__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,558 @@
|
||||
/*
|
||||
* Copyright (c) 2023, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_aesadv.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_AESADV__
|
||||
|
||||
static void DL_AESADV_loadData(
|
||||
volatile uint32_t *destPtr, const uint32_t *srcPtr, uint8_t numWords);
|
||||
static void DL_AESADV_readData(
|
||||
uint32_t *destPtr, volatile const uint32_t *srcPtr, uint8_t numWords);
|
||||
|
||||
static const uint32_t *DL_AESADV_checkAlignmentAndReturnConstPtr(
|
||||
const uint8_t *ptr);
|
||||
|
||||
static uint32_t *DL_AESADV_checkAlignmentAndReturnPtr(const uint8_t *ptr);
|
||||
|
||||
DL_AESADV_STATUS DL_AESADV_setKey(
|
||||
AESADV_Regs *aesadv, const uint8_t *key, DL_AESADV_KEY_SIZE keySize)
|
||||
{
|
||||
DL_AESADV_STATUS status = DL_AESADV_STATUS_SUCCESS;
|
||||
const uint32_t *keyAligned;
|
||||
|
||||
keyAligned = DL_AESADV_checkAlignmentAndReturnConstPtr(key);
|
||||
if (keyAligned != NULL) {
|
||||
DL_AESADV_setKeyAligned(aesadv, keyAligned, keySize);
|
||||
} else {
|
||||
status = DL_AESADV_STATUS_UNALIGNED_ACCESS;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void DL_AESADV_setKeyAligned(AESADV_Regs *aesadv, const uint32_t *keyAligned,
|
||||
DL_AESADV_KEY_SIZE keySize)
|
||||
{
|
||||
uint8_t numWords;
|
||||
|
||||
switch (keySize) {
|
||||
case DL_AESADV_KEY_SIZE_128_BIT:
|
||||
numWords = 4U;
|
||||
break;
|
||||
case DL_AESADV_KEY_SIZE_256_BIT:
|
||||
numWords = 8U;
|
||||
break;
|
||||
default:
|
||||
/* invalid key size*/
|
||||
numWords = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
DL_Common_updateReg(
|
||||
&aesadv->CTRL, (uint32_t) keySize, AESADV_CTRL_KEYSIZE_MASK);
|
||||
|
||||
DL_AESADV_loadData(&aesadv->KEY0, keyAligned, numWords);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
DL_AESADV_STATUS DL_AESADV_setGCMHashKey(
|
||||
AESADV_Regs *aesadv, const uint8_t *hashKey)
|
||||
{
|
||||
DL_AESADV_STATUS status = DL_AESADV_STATUS_SUCCESS;
|
||||
const uint32_t *hashKeyAligned;
|
||||
|
||||
hashKeyAligned = DL_AESADV_checkAlignmentAndReturnConstPtr(hashKey);
|
||||
if (hashKeyAligned != NULL) {
|
||||
DL_AESADV_setGCMHashKeyAligned(aesadv, hashKeyAligned);
|
||||
} else {
|
||||
status = DL_AESADV_STATUS_UNALIGNED_ACCESS;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void DL_AESADV_setGCMHashKeyAligned(
|
||||
AESADV_Regs *aesadv, const uint32_t *hashKeyAligned)
|
||||
{
|
||||
uint8_t numWords = 4U;
|
||||
|
||||
DL_AESADV_loadData(&aesadv->GHASH_H0, hashKeyAligned, numWords);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
DL_AESADV_STATUS DL_AESADV_setSecondKey(
|
||||
AESADV_Regs *aesadv, const uint8_t *secondKey)
|
||||
{
|
||||
DL_AESADV_STATUS status = DL_AESADV_STATUS_SUCCESS;
|
||||
const uint32_t *secondKeyAligned;
|
||||
|
||||
secondKeyAligned = DL_AESADV_checkAlignmentAndReturnConstPtr(secondKey);
|
||||
if (secondKeyAligned != NULL) {
|
||||
DL_AESADV_setSecondKeyAligned(aesadv, secondKeyAligned);
|
||||
} else {
|
||||
status = DL_AESADV_STATUS_UNALIGNED_ACCESS;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void DL_AESADV_setSecondKeyAligned(
|
||||
AESADV_Regs *aesadv, const uint32_t *secondKeyAligned)
|
||||
{
|
||||
uint8_t numWords = 4U;
|
||||
|
||||
DL_AESADV_loadData(&aesadv->GHASH_H0, secondKeyAligned, numWords);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
DL_AESADV_STATUS DL_AESADV_setThirdKey(
|
||||
AESADV_Regs *aesadv, const uint8_t *thirdKey)
|
||||
{
|
||||
DL_AESADV_STATUS status = DL_AESADV_STATUS_SUCCESS;
|
||||
const uint32_t *thirdKeyAligned;
|
||||
|
||||
thirdKeyAligned = DL_AESADV_checkAlignmentAndReturnConstPtr(thirdKey);
|
||||
if (thirdKeyAligned != NULL) {
|
||||
DL_AESADV_setThirdKeyAligned(aesadv, thirdKeyAligned);
|
||||
} else {
|
||||
status = DL_AESADV_STATUS_UNALIGNED_ACCESS;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void DL_AESADV_setThirdKeyAligned(
|
||||
AESADV_Regs *aesadv, const uint32_t *thirdKeyAligned)
|
||||
{
|
||||
uint8_t numWords = 4U;
|
||||
|
||||
DL_AESADV_loadData(&aesadv->GCMCCM_TAG0, thirdKeyAligned, numWords);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
DL_AESADV_STATUS DL_AESADV_loadIntermediateTAG(
|
||||
AESADV_Regs *aesadv, const uint8_t *tag)
|
||||
{
|
||||
DL_AESADV_STATUS status = DL_AESADV_STATUS_SUCCESS;
|
||||
const uint32_t *tagAligned;
|
||||
|
||||
tagAligned = DL_AESADV_checkAlignmentAndReturnConstPtr(tag);
|
||||
if (tagAligned != NULL) {
|
||||
DL_AESADV_loadIntermediateTAGAligned(aesadv, tagAligned);
|
||||
} else {
|
||||
status = DL_AESADV_STATUS_UNALIGNED_ACCESS;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void DL_AESADV_loadIntermediateTAGAligned(
|
||||
AESADV_Regs *aesadv, const uint32_t *tagAligned)
|
||||
{
|
||||
uint8_t numWords = 4U;
|
||||
|
||||
DL_AESADV_loadData(&aesadv->GCMCCM_TAG0, tagAligned, numWords);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
DL_AESADV_STATUS DL_AESADV_loadInitializationVector(
|
||||
AESADV_Regs *aesadv, const uint8_t *iv)
|
||||
{
|
||||
DL_AESADV_STATUS status = DL_AESADV_STATUS_SUCCESS;
|
||||
uint32_t *ivAligned;
|
||||
|
||||
ivAligned = DL_AESADV_checkAlignmentAndReturnPtr(iv);
|
||||
if (ivAligned != NULL) {
|
||||
DL_AESADV_loadInitializationVectorAligned(aesadv, ivAligned);
|
||||
} else {
|
||||
status = DL_AESADV_STATUS_UNALIGNED_ACCESS;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void DL_AESADV_loadInitializationVectorAligned(
|
||||
AESADV_Regs *aesadv, const uint32_t *ivAligned)
|
||||
{
|
||||
uint8_t numWords = 4U;
|
||||
|
||||
DL_AESADV_loadData(&aesadv->IV0, ivAligned, numWords);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
DL_AESADV_STATUS DL_AESADV_readInitializationVector(
|
||||
AESADV_Regs *aesadv, const uint8_t *iv)
|
||||
{
|
||||
DL_AESADV_STATUS status = DL_AESADV_STATUS_SUCCESS;
|
||||
uint32_t *ivAligned;
|
||||
|
||||
ivAligned = DL_AESADV_checkAlignmentAndReturnPtr(iv);
|
||||
if (ivAligned != NULL) {
|
||||
DL_AESADV_readInitializationVectorAligned(aesadv, ivAligned);
|
||||
} else {
|
||||
status = DL_AESADV_STATUS_UNALIGNED_ACCESS;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void DL_AESADV_readInitializationVectorAligned(
|
||||
AESADV_Regs *aesadv, uint32_t *ivAligned)
|
||||
{
|
||||
uint8_t numWords = 4U;
|
||||
volatile uint32_t *sourcePtr;
|
||||
|
||||
sourcePtr = (volatile uint32_t *) &aesadv->IV0;
|
||||
|
||||
DL_AESADV_readData(ivAligned, sourcePtr, numWords);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void DL_AESADV_loadCCMNonceAndCounter(
|
||||
AESADV_Regs *aesadv, uint8_t *nonce, DL_AESADV_CCM_CTR_WIDTH ctrWidth)
|
||||
{
|
||||
uint8_t *noncePtr = nonce;
|
||||
uint8_t numWords = 4U;
|
||||
uint32_t ivArray[4];
|
||||
uint8_t *ivPtr = (uint8_t *) &ivArray[0];
|
||||
uint8_t i;
|
||||
|
||||
/* calculation of the nonce length. (Length described in table in header) */
|
||||
uint8_t ccml = (uint8_t)((uint32_t) ctrWidth >> AESADV_CTRL_CCML_OFS);
|
||||
uint8_t counterWidthInBytes = (ccml + 1U);
|
||||
|
||||
/* subtracting the counterWidth in bytes as well as the flag byte */
|
||||
uint8_t nonceWidthInBytes = 14U - ccml;
|
||||
|
||||
*ivPtr++ = ccml;
|
||||
|
||||
/* addition of the Nonce */
|
||||
for (i = 0; i < nonceWidthInBytes; i++) {
|
||||
*ivPtr++ = *noncePtr++;
|
||||
}
|
||||
|
||||
/* Counter is always initialized to zeros */
|
||||
for (i = 0; i < counterWidthInBytes; i++) {
|
||||
*ivPtr++ = 0x00;
|
||||
}
|
||||
|
||||
DL_AESADV_loadData(&aesadv->IV0, ivArray, numWords);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
DL_AESADV_STATUS DL_AESADV_loadInputData(
|
||||
AESADV_Regs *aesadv, const uint8_t *data)
|
||||
{
|
||||
DL_AESADV_STATUS status = DL_AESADV_STATUS_SUCCESS;
|
||||
uint32_t *dataAligned;
|
||||
|
||||
dataAligned = DL_AESADV_checkAlignmentAndReturnPtr(data);
|
||||
if (dataAligned != NULL) {
|
||||
DL_AESADV_loadInputDataAligned(aesadv, dataAligned);
|
||||
} else {
|
||||
status = DL_AESADV_STATUS_UNALIGNED_ACCESS;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void DL_AESADV_loadInputDataAligned(
|
||||
AESADV_Regs *aesadv, const uint32_t *dataAligned)
|
||||
{
|
||||
uint8_t numWords = 4U;
|
||||
|
||||
DL_AESADV_loadData(&aesadv->DATA0, dataAligned, numWords);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
DL_AESADV_STATUS DL_AESADV_readOutputData(
|
||||
const AESADV_Regs *aesadv, const uint8_t *data)
|
||||
{
|
||||
DL_AESADV_STATUS status = DL_AESADV_STATUS_SUCCESS;
|
||||
uint32_t *dataAligned;
|
||||
|
||||
dataAligned = DL_AESADV_checkAlignmentAndReturnPtr(data);
|
||||
if (dataAligned != NULL) {
|
||||
DL_AESADV_readOutputDataAligned(aesadv, dataAligned);
|
||||
} else {
|
||||
status = DL_AESADV_STATUS_UNALIGNED_ACCESS;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void DL_AESADV_readOutputDataAligned(
|
||||
const AESADV_Regs *aesadv, uint32_t *dataAligned)
|
||||
{
|
||||
uint8_t numWords = 4U;
|
||||
|
||||
DL_AESADV_readData(dataAligned, &aesadv->DATA0, numWords);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
DL_AESADV_STATUS DL_AESADV_readTAG(
|
||||
const AESADV_Regs *aesadv, const uint8_t *tag)
|
||||
{
|
||||
DL_AESADV_STATUS status = DL_AESADV_STATUS_SUCCESS;
|
||||
uint32_t *tagAligned;
|
||||
|
||||
tagAligned = DL_AESADV_checkAlignmentAndReturnPtr(tag);
|
||||
if (tagAligned != NULL) {
|
||||
DL_AESADV_readTAGAligned(aesadv, tagAligned);
|
||||
} else {
|
||||
status = DL_AESADV_STATUS_UNALIGNED_ACCESS;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void DL_AESADV_readTAGAligned(const AESADV_Regs *aesadv, uint32_t *tagAligned)
|
||||
{
|
||||
uint8_t numWords = 4U;
|
||||
|
||||
DL_AESADV_readData(tagAligned, &aesadv->TAG0, numWords);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void DL_AESADV_initECB(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
|
||||
{
|
||||
DL_Common_updateReg(&aesadv->CTRL,
|
||||
((uint32_t) DL_AESADV_MODE_ECB | config->direction),
|
||||
((uint32_t) DL_AESADV_MODE_MASK | AESADV_CTRL_DIR_MASK |
|
||||
AESADV_CTRL_SAVE_CNTXT_MASK));
|
||||
|
||||
DL_AESADV_setUpperCryptoLength(aesadv, config->upperCryptoLength);
|
||||
DL_AESADV_setLowerCryptoLength(aesadv, config->lowerCryptoLength);
|
||||
}
|
||||
|
||||
void DL_AESADV_initCBC(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
|
||||
{
|
||||
DL_Common_updateReg(&aesadv->CTRL,
|
||||
((uint32_t) DL_AESADV_MODE_CBC | config->direction),
|
||||
((uint32_t) DL_AESADV_MODE_MASK | AESADV_CTRL_DIR_MASK |
|
||||
AESADV_CTRL_SAVE_CNTXT_MASK));
|
||||
|
||||
DL_AESADV_loadInitializationVector(aesadv, config->iv);
|
||||
|
||||
DL_AESADV_setUpperCryptoLength(aesadv, config->upperCryptoLength);
|
||||
DL_AESADV_setLowerCryptoLength(aesadv, config->lowerCryptoLength);
|
||||
}
|
||||
|
||||
void DL_AESADV_initCFB(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
|
||||
{
|
||||
DL_Common_updateReg(&aesadv->CTRL,
|
||||
(((uint32_t) DL_AESADV_MODE_CFB) | ((uint32_t) config->direction) |
|
||||
((uint32_t) config->cfb_fbWidth)),
|
||||
(DL_AESADV_MODE_MASK | AESADV_CTRL_DIR_MASK |
|
||||
AESADV_CTRL_CTR_WIDTH_MASK | AESADV_CTRL_SAVE_CNTXT_MASK));
|
||||
|
||||
DL_AESADV_loadInitializationVector(aesadv, config->iv);
|
||||
|
||||
DL_AESADV_setUpperCryptoLength(aesadv, config->upperCryptoLength);
|
||||
DL_AESADV_setLowerCryptoLength(aesadv, config->lowerCryptoLength);
|
||||
}
|
||||
|
||||
void DL_AESADV_initOFB(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
|
||||
{
|
||||
DL_Common_updateReg(&aesadv->CTRL,
|
||||
(((uint32_t) DL_AESADV_MODE_OFB) | ((uint32_t) config->direction) |
|
||||
((uint32_t) config->cfb_fbWidth)),
|
||||
(DL_AESADV_MODE_MASK | AESADV_CTRL_DIR_MASK |
|
||||
AESADV_CTRL_CTR_WIDTH_MASK | AESADV_CTRL_SAVE_CNTXT_MASK));
|
||||
|
||||
DL_AESADV_loadInitializationVector(aesadv, config->iv);
|
||||
|
||||
DL_AESADV_setUpperCryptoLength(aesadv, config->upperCryptoLength);
|
||||
DL_AESADV_setLowerCryptoLength(aesadv, config->lowerCryptoLength);
|
||||
}
|
||||
|
||||
void DL_AESADV_initCTR(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
|
||||
{
|
||||
DL_Common_updateReg(&aesadv->CTRL,
|
||||
(((uint32_t) DL_AESADV_MODE_CTR) | ((uint32_t) config->direction) |
|
||||
((uint32_t) config->ctr_ctrWidth)),
|
||||
(DL_AESADV_MODE_MASK | AESADV_CTRL_DIR_MASK |
|
||||
AESADV_CTRL_CTR_WIDTH_MASK | AESADV_CTRL_SAVE_CNTXT_MASK));
|
||||
|
||||
DL_AESADV_loadInitializationVector(aesadv, config->iv);
|
||||
|
||||
DL_AESADV_setUpperCryptoLength(aesadv, config->upperCryptoLength);
|
||||
DL_AESADV_setLowerCryptoLength(aesadv, config->lowerCryptoLength);
|
||||
}
|
||||
|
||||
void DL_AESADV_initICM(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
|
||||
{
|
||||
DL_Common_updateReg(&aesadv->CTRL,
|
||||
((uint32_t) DL_AESADV_MODE_ICM | ((uint32_t) config->direction)),
|
||||
(DL_AESADV_MODE_MASK | AESADV_CTRL_DIR_MASK |
|
||||
AESADV_CTRL_SAVE_CNTXT_MASK));
|
||||
|
||||
DL_AESADV_loadInitializationVector(aesadv, config->iv);
|
||||
|
||||
DL_AESADV_setUpperCryptoLength(aesadv, config->upperCryptoLength);
|
||||
DL_AESADV_setLowerCryptoLength(aesadv, config->lowerCryptoLength);
|
||||
}
|
||||
|
||||
void DL_AESADV_initCMAC(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
|
||||
{
|
||||
uint32_t zeroArray[4] = {0x00000000, 0x00000000, 0x00000000, 0x00000000};
|
||||
|
||||
/* Set the second and third keys, and zero out the initialization vector */
|
||||
DL_AESADV_setSecondKey(aesadv, config->k1);
|
||||
DL_AESADV_setThirdKey(aesadv, config->k2);
|
||||
DL_AESADV_loadInitializationVectorAligned(aesadv, &zeroArray[0]);
|
||||
|
||||
DL_Common_updateReg(&aesadv->CTRL,
|
||||
((uint32_t) DL_AESADV_MODE_CMAC | ((uint32_t) DL_AESADV_DIR_ENCRYPT) |
|
||||
((uint32_t) AESADV_CTRL_SAVE_CNTXT_ENABLE)),
|
||||
(DL_AESADV_MODE_MASK | AESADV_CTRL_DIR_MASK |
|
||||
AESADV_CTRL_SAVE_CNTXT_MASK));
|
||||
|
||||
DL_AESADV_setUpperCryptoLength(aesadv, config->upperCryptoLength);
|
||||
DL_AESADV_setLowerCryptoLength(aesadv, config->lowerCryptoLength);
|
||||
}
|
||||
|
||||
void DL_AESADV_initCBCMAC(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
|
||||
{
|
||||
uint32_t zeroArray[4] = {0x00000000, 0x00000000, 0x00000000, 0x00000000};
|
||||
|
||||
/* Zero out the second and third keys and the IV for CBC-MAC as per spec */
|
||||
DL_AESADV_setSecondKeyAligned(aesadv, &zeroArray[0]);
|
||||
DL_AESADV_setThirdKeyAligned(aesadv, &zeroArray[0]);
|
||||
DL_AESADV_loadInitializationVectorAligned(aesadv, &zeroArray[0]);
|
||||
|
||||
DL_Common_updateReg(&aesadv->CTRL,
|
||||
((uint32_t) DL_AESADV_MODE_CBCMAC |
|
||||
((uint32_t) DL_AESADV_DIR_ENCRYPT) |
|
||||
((uint32_t) AESADV_CTRL_SAVE_CNTXT_ENABLE)),
|
||||
(DL_AESADV_MODE_MASK | AESADV_CTRL_DIR_MASK |
|
||||
AESADV_CTRL_SAVE_CNTXT_MASK));
|
||||
|
||||
DL_AESADV_setUpperCryptoLength(aesadv, config->upperCryptoLength);
|
||||
DL_AESADV_setLowerCryptoLength(aesadv, config->lowerCryptoLength);
|
||||
}
|
||||
|
||||
void DL_AESADV_initGCM(AESADV_Regs *aesadv, const DL_AESADV_Config *config)
|
||||
{
|
||||
uint32_t zeroArray[4] = {0x00000000, 0x00000000, 0x00000000, 0x00000000};
|
||||
|
||||
/* Zero out the intermediate TAG for GCM as per spec */
|
||||
DL_AESADV_loadIntermediateTAGAligned(aesadv, &zeroArray[0]);
|
||||
|
||||
DL_AESADV_loadInitializationVector(aesadv, config->iv);
|
||||
|
||||
DL_Common_updateReg(&aesadv->CTRL,
|
||||
(((uint32_t) config->mode) | ((uint32_t) config->direction) |
|
||||
((uint32_t) DL_AESADV_CTR_WIDTH_32_BIT |
|
||||
(uint32_t) AESADV_CTRL_SAVE_CNTXT_ENABLE)),
|
||||
((uint32_t) DL_AESADV_MODE_MASK | AESADV_CTRL_DIR_MASK |
|
||||
AESADV_CTRL_CTR_WIDTH_MASK | AESADV_CTRL_SAVE_CNTXT_MASK));
|
||||
|
||||
DL_AESADV_setUpperCryptoLength(aesadv, config->upperCryptoLength);
|
||||
DL_AESADV_setLowerCryptoLength(aesadv, config->lowerCryptoLength);
|
||||
|
||||
DL_AESADV_setAADLength(aesadv, config->aadLength);
|
||||
}
|
||||
|
||||
void DL_AESADV_initCCM(AESADV_Regs *aesadv, DL_AESADV_Config *config)
|
||||
{
|
||||
DL_AESADV_loadCCMNonceAndCounter(
|
||||
aesadv, config->nonce, config->ccm_ctrWidth);
|
||||
|
||||
DL_Common_updateReg(&aesadv->CTRL,
|
||||
(((uint32_t) DL_AESADV_MODE_CCM) | ((uint32_t) config->direction) |
|
||||
((uint32_t) config->ccm_ctrWidth) |
|
||||
((uint32_t) config->ccm_tagWidth) |
|
||||
((uint32_t) DL_AESADV_CTR_WIDTH_64_BIT) |
|
||||
((uint32_t) AESADV_CTRL_SAVE_CNTXT_ENABLE)),
|
||||
(DL_AESADV_MODE_MASK | AESADV_CTRL_DIR_MASK | AESADV_CTRL_CCML_MASK |
|
||||
AESADV_CTRL_CCMM_MASK | AESADV_CTRL_CTR_WIDTH_MASK |
|
||||
AESADV_CTRL_SAVE_CNTXT_MASK));
|
||||
|
||||
DL_AESADV_setUpperCryptoLength(aesadv, config->upperCryptoLength);
|
||||
DL_AESADV_setLowerCryptoLength(aesadv, config->lowerCryptoLength);
|
||||
|
||||
DL_AESADV_setAADLength(aesadv, config->aadLength);
|
||||
}
|
||||
|
||||
static void DL_AESADV_loadData(
|
||||
volatile uint32_t *destPtr, const uint32_t *srcPtr, uint8_t numWords)
|
||||
{
|
||||
uint8_t i;
|
||||
for (i = 0; i < numWords; i++) {
|
||||
*destPtr++ = *srcPtr++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
static void DL_AESADV_readData(
|
||||
uint32_t *destPtr, volatile const uint32_t *srcPtr, uint8_t numWords)
|
||||
{
|
||||
uint8_t i;
|
||||
for (i = 0; i < numWords; i++) {
|
||||
*destPtr++ = *srcPtr++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
static const uint32_t *DL_AESADV_checkAlignmentAndReturnConstPtr(
|
||||
const uint8_t *ptr)
|
||||
{
|
||||
uint32_t address = (uint32_t) ptr;
|
||||
const uint32_t *alignedPtr;
|
||||
if ((address << 30) != 0x00000000u) {
|
||||
/* Unaligned access */
|
||||
alignedPtr = NULL;
|
||||
} else {
|
||||
/* Aligned Access */
|
||||
alignedPtr = (const uint32_t *) address;
|
||||
}
|
||||
return alignedPtr;
|
||||
}
|
||||
|
||||
static uint32_t *DL_AESADV_checkAlignmentAndReturnPtr(const uint8_t *ptr)
|
||||
{
|
||||
uint32_t address = (uint32_t) ptr;
|
||||
uint32_t *alignedPtr;
|
||||
if ((address << 30) != 0x00000000u) {
|
||||
/* Unaligned access */
|
||||
alignedPtr = NULL;
|
||||
} else {
|
||||
/* Aligned Access */
|
||||
alignedPtr = (uint32_t *) address;
|
||||
}
|
||||
return alignedPtr;
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_AESADV__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/driverlib/dl_common.h>
|
||||
|
||||
void DL_Common_delayCycles(uint32_t cycles)
|
||||
{
|
||||
/* this is a scratch register for the compiler to use */
|
||||
uint32_t scratch;
|
||||
|
||||
/* There will be a 2 cycle delay here to fetch & decode instructions
|
||||
* if branch and linking to this function */
|
||||
|
||||
/* Subtract 2 net cycles for constant offset: +2 cycles for entry jump,
|
||||
* +2 cycles for exit, -1 cycle for a shorter loop cycle on the last loop,
|
||||
* -1 for this instruction */
|
||||
|
||||
__asm volatile(
|
||||
#ifdef __GNUC__
|
||||
".syntax unified\n\t"
|
||||
#endif
|
||||
"SUBS %0, %[numCycles], #2; \n"
|
||||
"%=: \n\t"
|
||||
"SUBS %0, %0, #4; \n\t"
|
||||
"NOP; \n\t"
|
||||
"BHS %=b;" /* branches back to the label defined above if number > 0 */
|
||||
/* Return: 2 cycles */
|
||||
: "=&r"(scratch)
|
||||
: [ numCycles ] "r"(cycles));
|
||||
}
|
||||
@@ -0,0 +1,100 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_common.h
|
||||
* @brief DriverLib Common APIs
|
||||
* @defgroup DLCommon DriverLib Common APIs
|
||||
*
|
||||
* @anchor ti_dl_dl_common_Overview
|
||||
* # Overview
|
||||
*
|
||||
* APIs used across multiple DriverLib modules
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************/
|
||||
/** @addtogroup DLCommon
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_dl_common__include
|
||||
#define ti_dl_dl_common__include
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Writes value to specified register - retaining bits unaffected by mask.
|
||||
*
|
||||
* @param[in] reg Pointer to the register overlay for the peripheral.
|
||||
* @param[in] val Value to be written to the register.
|
||||
* @param[in] mask Mask defines which bits will be altered.
|
||||
*/
|
||||
__STATIC_INLINE void DL_Common_updateReg(
|
||||
volatile uint32_t *reg, uint32_t val, uint32_t mask)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
tmp = *reg;
|
||||
tmp = tmp & ~mask;
|
||||
*reg = tmp | (val & mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Consumes the number of CPU cycles specified.
|
||||
*
|
||||
* @param[in] cycles Floor number of cycles to delay.
|
||||
* Specifying zero will result in the maximum
|
||||
* possible delay. Note that guarantees at least
|
||||
* this number of cycles will be delayed,
|
||||
* not that exactly this number of cycles will be
|
||||
* delayed. If a more precise number of cycle delay value
|
||||
* is needed, GPTimer is recommended.
|
||||
*
|
||||
* Typical variance from this function is 10 cycles or
|
||||
* less assuming that the function is located in flash and
|
||||
* that caching is enabled. Disabling caching may result in
|
||||
* wait-states when fetching from flash.
|
||||
* Other variance occurs due:
|
||||
* - Amount of register stacking/unstacking around API entry/exit
|
||||
* - Value of cycles relative to 4-cycle loop counter
|
||||
* - Placement of code on a 2- or 4-byte aligned boundary
|
||||
*/
|
||||
void DL_Common_delayCycles(uint32_t cycles);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ti_dl_dl_common__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2025, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_comp.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_COMP__
|
||||
#endif /* __MSPM0_HAS_COMP__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_crc.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_CRC__
|
||||
|
||||
uint32_t DL_CRC_calculateBlock32(
|
||||
CRC_Regs* crc, uint32_t seed, const uint32_t* ptr, uint32_t size)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
DL_CRC_setSeed32(crc, seed);
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
DL_CRC_feedData32(crc, ptr[i]);
|
||||
}
|
||||
|
||||
return (DL_CRC_getResult32(crc));
|
||||
}
|
||||
|
||||
uint32_t DL_CRC_calculateMemoryRange32(
|
||||
CRC_Regs* crc, uint32_t seed, uint32_t* ptrStart, const uint32_t* ptrEnd)
|
||||
{
|
||||
DL_CRC_setSeed32(crc, seed);
|
||||
|
||||
uint32_t* ptr = ptrStart;
|
||||
|
||||
while (ptr <= ptrEnd) {
|
||||
DL_CRC_feedData32(crc, (uint32_t) *ptr);
|
||||
ptr = ptr + 1;
|
||||
}
|
||||
|
||||
return (DL_CRC_getResult32(crc));
|
||||
}
|
||||
|
||||
uint16_t DL_CRC_calculateBlock16(
|
||||
CRC_Regs* crc, uint16_t seed, const uint16_t* ptr, uint16_t size)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
DL_CRC_setSeed16(crc, seed);
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
DL_CRC_feedData16(crc, ptr[i]);
|
||||
}
|
||||
|
||||
return ((uint16_t) DL_CRC_getResult16(crc));
|
||||
}
|
||||
|
||||
uint16_t DL_CRC_calculateMemoryRange16(
|
||||
CRC_Regs* crc, uint16_t seed, uint16_t* ptrStart, const uint16_t* ptrEnd)
|
||||
{
|
||||
DL_CRC_setSeed16(crc, seed);
|
||||
|
||||
uint16_t* ptr = ptrStart;
|
||||
|
||||
while (ptr <= ptrEnd) {
|
||||
DL_CRC_feedData16(crc, (uint16_t) *ptr);
|
||||
ptr = ptr + 1;
|
||||
}
|
||||
|
||||
return ((uint16_t) DL_CRC_getResult16(crc));
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_CRC__ */
|
||||
@@ -0,0 +1,413 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_crc.h
|
||||
* @brief Cyclic Redundancy Check (CRC) Driver Library
|
||||
* @defgroup CRC Cyclic Redundancy Check (CRC)
|
||||
*
|
||||
* @anchor ti_dl_dl_crc_Overview
|
||||
* # Overview
|
||||
*
|
||||
* The CRC DriverLib allows full configuration of the MSPM0 CRC module.
|
||||
* The cyclic redundancy check (CRC) accelerator generates signatures for a
|
||||
* given data sequence based on the CRC16-CCITT polynomial or the
|
||||
* CRC32-ISO3309 polynomial.
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_dl_crc__include
|
||||
#define ti_dl_dl_crc__include
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
#include <ti/driverlib/dl_common.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_CRC__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if (CRC_SYS_CRC32_ENABLE == 1)
|
||||
/*!
|
||||
* @brief Device has support for CRC 32-bit polynomials
|
||||
*/
|
||||
#define DEVICE_HAS_CRC_32_BIT_POLYNOMIAL
|
||||
#endif
|
||||
|
||||
/*! @enum DL_CRC_POLYNOMIAL */
|
||||
typedef enum {
|
||||
/*! Use 16-bit polynomial for calculation. Follows CRC-16-CCITT standard
|
||||
* with a polynomial value of 0x1021. */
|
||||
DL_CRC_16_POLYNOMIAL = CRC_CRCCTRL_POLYSIZE_CRC16,
|
||||
#ifdef DEVICE_HAS_CRC_32_BIT_POLYNOMIAL
|
||||
/*! Use 32-bit polynomial for calculation. Follows CRC32-ISO3309 standard
|
||||
* with a polynomial value of 0x04C11DB7.*/
|
||||
DL_CRC_32_POLYNOMIAL = CRC_CRCCTRL_POLYSIZE_CRC32
|
||||
#endif /* DEVICE_HAS_CRC_32_BIT_POLYNOMIAL */
|
||||
} DL_CRC_POLYNOMIAL;
|
||||
|
||||
/*! @enum DL_CRC_BIT */
|
||||
typedef enum {
|
||||
/*! CRC Bit Input and output are reversed */
|
||||
DL_CRC_BIT_REVERSED = CRC_CRCCTRL_BITREVERSE_REVERSED,
|
||||
/*! CRC Bit Input and output are not reversed */
|
||||
DL_CRC_BIT_NOT_REVERSED = CRC_CRCCTRL_BITREVERSE_NOT_REVERSED
|
||||
} DL_CRC_BIT;
|
||||
|
||||
/*! @enum DL_CRC_INPUT_ENDIANESS */
|
||||
typedef enum {
|
||||
/*! CRC Input is proccessed in little endian.
|
||||
* LSB is lowest memory address and first to be processed. */
|
||||
DL_CRC_INPUT_ENDIANESS_LITTLE_ENDIAN =
|
||||
CRC_CRCCTRL_INPUT_ENDIANNESS_LITTLE_ENDIAN,
|
||||
/*! CRC Input is proccessed in big endian.
|
||||
* LSB is highest memory address and last to be processed. */
|
||||
DL_CRC_INPUT_ENDIANESS_BIG_ENDIAN = CRC_CRCCTRL_INPUT_ENDIANNESS_BIG_ENDIAN
|
||||
} DL_CRC_INPUT_ENDIANESS;
|
||||
|
||||
/*! @enum DL_CRC_OUTPUT_BYTESWAP */
|
||||
typedef enum {
|
||||
/*! CRC output byteswap is enabled */
|
||||
DL_CRC_OUTPUT_BYTESWAP_ENABLED = CRC_CRCCTRL_OUTPUT_BYTESWAP_ENABLE,
|
||||
/*! CRC output byteswap is disabled */
|
||||
DL_CRC_OUTPUT_BYTESWAP_DISABLED = CRC_CRCCTRL_OUTPUT_BYTESWAP_DISABLE
|
||||
} DL_CRC_OUTPUT_BYTESWAP;
|
||||
|
||||
/**
|
||||
* @brief Enables the Peripheral Write Enable (PWREN) register for the CRC
|
||||
*
|
||||
* Before any peripheral registers can be configured by software, the
|
||||
* peripheral itself must be enabled by writing the ENABLE bit together with
|
||||
* the appropriate KEY value to the peripheral's PWREN register.
|
||||
*
|
||||
* @param crc Pointer to the register overlay for the CRC peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRC_enablePower(CRC_Regs *crc)
|
||||
{
|
||||
crc->GPRCM.PWREN = (CRC_PWREN_KEY_UNLOCK_W | CRC_PWREN_ENABLE_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Peripheral Write Enable (PWREN) register for the CRC
|
||||
*
|
||||
* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
|
||||
* accessible for read/write operations.
|
||||
*
|
||||
* @note This API does not provide large power savings.
|
||||
*
|
||||
* @param crc Pointer to the register overlay for the CRC peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRC_disablePower(CRC_Regs *crc)
|
||||
{
|
||||
crc->GPRCM.PWREN = (CRC_PWREN_KEY_UNLOCK_W | CRC_PWREN_ENABLE_DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if the Peripheral Write Enable (PWREN) register for the CRC
|
||||
* is enabled
|
||||
*
|
||||
* Before any peripheral registers can be configured by software, the
|
||||
* peripheral itself must be enabled by writing the ENABLE bit together with
|
||||
* the appropriate KEY value to the peripheral's PWREN register.
|
||||
*
|
||||
* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
|
||||
* accessible for read/write operations.
|
||||
*
|
||||
* @param crc Pointer to the register overlay for the CRC peripheral
|
||||
*
|
||||
* @return true if peripheral register access is enabled
|
||||
* @return false if peripheral register access is disabled
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE bool DL_CRC_isPowerEnabled(const CRC_Regs *crc)
|
||||
{
|
||||
return (
|
||||
(crc->GPRCM.PWREN & CRC_PWREN_ENABLE_MASK) == CRC_PWREN_ENABLE_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets crc peripheral
|
||||
*
|
||||
* @param crc Pointer to the register overlay for the CRC peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRC_reset(CRC_Regs *crc)
|
||||
{
|
||||
crc->GPRCM.RSTCTL =
|
||||
(CRC_RSTCTL_KEY_UNLOCK_W | CRC_RSTCTL_RESETSTKYCLR_CLR |
|
||||
CRC_RSTCTL_RESETASSERT_ASSERT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if crc module has been reset
|
||||
*
|
||||
* @param crc Pointer to the register overlay for the CRC peripheral\
|
||||
*
|
||||
* @return true if peripheral was reset
|
||||
* @return false if peripheral wasn't reset
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE bool DL_CRC_isReset(const CRC_Regs *crc)
|
||||
{
|
||||
return ((crc->GPRCM.STAT & CRC_STAT_RESETSTKY_MASK) ==
|
||||
CRC_STAT_RESETSTKY_RESET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes CRC
|
||||
*
|
||||
* @param crc Pointer to the register overlay for the CRC peripheral
|
||||
* @param poly Selects CRC polynomial. One of @ref DL_CRC_POLYNOMIAL.
|
||||
* @param bitOrd Selects CRC bit order. One of @ref DL_CRC_BIT.
|
||||
* @param inEndianness Selects CRC input endianess. One of
|
||||
* @ref DL_CRC_INPUT_ENDIANESS.
|
||||
* @param outByteSwap Selects CRC output byte swap mode. One of
|
||||
* @ref DL_CRC_OUTPUT_BYTESWAP.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRC_init(CRC_Regs *crc, DL_CRC_POLYNOMIAL poly,
|
||||
DL_CRC_BIT bitOrd, DL_CRC_INPUT_ENDIANESS inEndianness,
|
||||
DL_CRC_OUTPUT_BYTESWAP outByteSwap)
|
||||
{
|
||||
crc->CRCCTRL = ((uint32_t) poly | (uint32_t) bitOrd |
|
||||
(uint32_t) inEndianness | (uint32_t) outByteSwap);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Initializes the seed for a 16-bit polynomial CRC calculation
|
||||
* @note CRC seed is swapped when CRC module is configured in big-endian
|
||||
* mode. For example when calling DL_CRC_setSeed32(CRC, 0xaabb).
|
||||
* The CRC module will be initialized with 0xbbaa. Therefore, the
|
||||
* seed value should be appropriately specified taking endianness
|
||||
* into account. Please refer to the device TRM for additional
|
||||
* detail.
|
||||
*
|
||||
* @param[in] crc Pointer to the register overlay for the CRC peripheral
|
||||
* @param[in] seed The seed for the CRC to start generating a signature from
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRC_setSeed16(CRC_Regs *crc, uint16_t seed)
|
||||
{
|
||||
volatile uintptr_t addr;
|
||||
volatile uint16_t *pRef;
|
||||
|
||||
addr = (uintptr_t)((volatile uintptr_t *) &crc->CRCSEED);
|
||||
pRef = (volatile uint16_t *) addr;
|
||||
|
||||
*pRef = seed;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Initializes the seed for a 32-bit polynomial CRC calculation
|
||||
* @note CRC seed is swapped when CRC module is configured in big-endian
|
||||
* mode. For example when calling DL_CRC_setSeed32(CRC, 0xaabbccdd).
|
||||
* The CRC module will be initialized with 0xddccbbaa. Therefore, the
|
||||
* seed value should be appropriately specified taking endianness
|
||||
* into account. Please refer to the device TRM for additional
|
||||
* detail.
|
||||
*
|
||||
* @param[in] crc Pointer to the register overlay for the CRC peripheral
|
||||
* @param[in] seed The seed for the CRC to start generating a signature from
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRC_setSeed32(CRC_Regs *crc, uint32_t seed)
|
||||
{
|
||||
crc->CRCSEED = seed;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Feeds 8-bit data into the CRC calculation
|
||||
*
|
||||
* @param[in] crc Pointer to the register overlay for the CRC
|
||||
* peripheral
|
||||
* @param[in] dataIn 8-bit data value to add to the signature
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRC_feedData8(CRC_Regs *crc, uint8_t dataIn)
|
||||
{
|
||||
volatile uint8_t *pRef = (volatile uint8_t *) &crc->CRCIN;
|
||||
*pRef = dataIn;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Feeds 16-bit data into the CRC calculation
|
||||
*
|
||||
* @param[in] crc Pointer to the register overlay for the CRC
|
||||
* peripheral
|
||||
* @param[in] dataIn 16-bit data value to add to the signature
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRC_feedData16(CRC_Regs *crc, uint16_t dataIn)
|
||||
{
|
||||
volatile uintptr_t addr;
|
||||
volatile uint16_t *pRef;
|
||||
|
||||
addr = (uintptr_t)((volatile uintptr_t *) &crc->CRCIN);
|
||||
pRef = (volatile uint16_t *) addr;
|
||||
|
||||
*pRef = dataIn;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Feeds 32-bit data into the CRC calculation
|
||||
*
|
||||
* Feeds a 32-bit value into the CRC calculation. 32-bit data can only be used
|
||||
* with the 32-bit polynomial.
|
||||
*
|
||||
* @param[in] crc Pointer to the register overlay for the CRC
|
||||
* peripheral
|
||||
* @param[in] dataIn 32 bit data value to add to the signature
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRC_feedData32(CRC_Regs *crc, uint32_t dataIn)
|
||||
{
|
||||
crc->CRCIN = dataIn;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Returns the result from the 16-bit polynomial calculation
|
||||
*
|
||||
* @param[in] crc Pointer to the register overlay for the CRC peripheral
|
||||
*
|
||||
* @return The calculation result for the 16-bit polynomial
|
||||
*/
|
||||
__STATIC_INLINE uint16_t DL_CRC_getResult16(const CRC_Regs *crc)
|
||||
{
|
||||
return ((uint16_t) crc->CRCOUT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Returns the result from the 32-bit polynomial calculation
|
||||
*
|
||||
* @param[in] crc Pointer to the register overlay for the CRC peripheral
|
||||
*
|
||||
* @return The calculation result for the 32-bit polynomial
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_CRC_getResult32(const CRC_Regs *crc)
|
||||
{
|
||||
return (crc->CRCOUT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Calculates the CRC over a range of 32-bit values
|
||||
*
|
||||
* Uses the 32-bit polynomial to calculate the checksum over a block of
|
||||
* values.
|
||||
*
|
||||
* @param[in] crc Pointer to the register overlay for the CRC peripheral
|
||||
* @param[in] seed The seed for the CRC to start generating a signature from
|
||||
* @param[in] ptr A pointer to the block of code to calculate the CRC over
|
||||
* @param[in] size The size of the block of uint32_t data
|
||||
*
|
||||
* @return The calculated CRC signature value
|
||||
*/
|
||||
extern uint32_t DL_CRC_calculateBlock32(
|
||||
CRC_Regs *crc, uint32_t seed, const uint32_t *ptr, uint32_t size);
|
||||
|
||||
/*!
|
||||
* @brief Calculates the CRC over a memory range
|
||||
*
|
||||
* Calculates the checksum using the 32-bit polynomial over any memory range.
|
||||
*
|
||||
* @param[in] crc Pointer to the register overlay for the CRC
|
||||
* peripheral
|
||||
* @param[in] seed The seed used to start generating a signature from
|
||||
* @param[in] ptrStart A uint32_t pointer to the start of a block of code to
|
||||
* calculate the CRC over
|
||||
* @param[in] ptrEnd A uint32_t pointer to the end of a block of code to
|
||||
* calculate the CRC over
|
||||
*
|
||||
* @return The calculated CRC signature value
|
||||
*/
|
||||
extern uint32_t DL_CRC_calculateMemoryRange32(
|
||||
CRC_Regs *crc, uint32_t seed, uint32_t *ptrStart, const uint32_t *ptrEnd);
|
||||
|
||||
/*!
|
||||
* @brief Calculates the CRC over a range of 16-bit values
|
||||
*
|
||||
* Uses the 16-bit polynomial to calculate the checksum over a block of
|
||||
* values.
|
||||
*
|
||||
* @param[in] crc Pointer to the register overlay for the CRC peripheral
|
||||
* @param[in] seed The seed for the CRC to start generating a signature from
|
||||
* @param[in] ptr A pointer to the block of code to calculate the CRC over
|
||||
* @param[in] size The size of the block of 16-bit data
|
||||
*
|
||||
* @return The calculated CRC signature value
|
||||
*/
|
||||
extern uint16_t DL_CRC_calculateBlock16(
|
||||
CRC_Regs *crc, uint16_t seed, const uint16_t *ptr, uint16_t size);
|
||||
|
||||
/*!
|
||||
* @brief Calculates the CRC over a memory range
|
||||
*
|
||||
* Calculates the checksum using the 16-bit polynomial over any memory range.
|
||||
*
|
||||
* @param[in] crc Pointer to the register overlay for the CRC
|
||||
* peripheral
|
||||
* @param[in] seed The seed used to start generating a signature from
|
||||
* @param[in] ptrStart A uint16_t pointer to the start of a block of code to
|
||||
* calculate the CRC over
|
||||
* @param[in] ptrEnd A uint16_t pointer to the end of a block of code to
|
||||
* calculate the CRC over
|
||||
*
|
||||
* @return The calculated CRC signature value
|
||||
*/
|
||||
extern uint16_t DL_CRC_calculateMemoryRange16(
|
||||
CRC_Regs *crc, uint16_t seed, uint16_t *ptrStart, const uint16_t *ptrEnd);
|
||||
|
||||
/**
|
||||
* @brief Returns the address of the CRC input data register.
|
||||
*
|
||||
* This API can be used with @ref DL_DMA_setDestAddr to set the destination
|
||||
* address when using DMA transfers
|
||||
*
|
||||
* @param[in] crc Pointer to the register overlay for the CRC
|
||||
* peripheral
|
||||
* @return Address of the CRC input data register
|
||||
*/
|
||||
__STATIC_INLINE uintptr_t DL_CRC_getCRCINAddr(const CRC_Regs *crc)
|
||||
{
|
||||
return ((uintptr_t) &crc->CRCIN);
|
||||
}
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MSPM0_HAS_CRC__ */
|
||||
|
||||
#endif /* ti_dl_dl_crc__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Copyright (c) 2023, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_crcp.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_CRCP__
|
||||
|
||||
uint32_t DL_CRCP_calculateBlock32(
|
||||
CRCP_Regs* crcp, uint32_t seed, const uint32_t* ptr, uint32_t size)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
DL_CRCP_setSeed32(crcp, seed);
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
DL_CRCP_feedData32(crcp, ptr[i]);
|
||||
}
|
||||
|
||||
return (DL_CRCP_getResult32(crcp));
|
||||
}
|
||||
|
||||
uint32_t DL_CRCP_calculateMemoryRange32(
|
||||
CRCP_Regs* crcp, uint32_t seed, uint32_t* ptrStart, const uint32_t* ptrEnd)
|
||||
{
|
||||
DL_CRCP_setSeed32(crcp, seed);
|
||||
|
||||
uint32_t* ptr = ptrStart;
|
||||
|
||||
while (ptr <= ptrEnd) {
|
||||
DL_CRCP_feedData32(crcp, (uint32_t) *ptr);
|
||||
ptr = ptr + 1;
|
||||
}
|
||||
|
||||
return (DL_CRCP_getResult32(crcp));
|
||||
}
|
||||
|
||||
uint16_t DL_CRCP_calculateBlock16(
|
||||
CRCP_Regs* crcp, uint16_t seed, const uint16_t* ptr, uint16_t size)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
DL_CRCP_setSeed16(crcp, seed);
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
DL_CRCP_feedData16(crcp, ptr[i]);
|
||||
}
|
||||
|
||||
return ((uint16_t) DL_CRCP_getResult16(crcp));
|
||||
}
|
||||
|
||||
uint16_t DL_CRCP_calculateMemoryRange16(
|
||||
CRCP_Regs* crcp, uint16_t seed, uint16_t* ptrStart, const uint16_t* ptrEnd)
|
||||
{
|
||||
DL_CRCP_setSeed16(crcp, seed);
|
||||
|
||||
uint16_t* ptr = ptrStart;
|
||||
|
||||
while (ptr <= ptrEnd) {
|
||||
DL_CRCP_feedData16(crcp, (uint16_t) *ptr);
|
||||
ptr = ptr + 1;
|
||||
}
|
||||
|
||||
return ((uint16_t) DL_CRCP_getResult16(crcp));
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_CRCP__ */
|
||||
@@ -0,0 +1,866 @@
|
||||
/*
|
||||
* Copyright (c) 2023, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_crcp.h
|
||||
* @brief Cyclic Redundancy Check with Configurable Polynomial (CRCP) Driver Library
|
||||
* @defgroup CRCP Cyclic Redundancy Check with Configurable Polynomial (CRCP)
|
||||
*
|
||||
* @anchor ti_dl_dl_crcp_Overview
|
||||
* # Overview
|
||||
*
|
||||
* The CRCP DriverLib allows full configuration of the MSPM0 CRCP module.
|
||||
* The cyclic redundancy check (CRC) accelerator generates signatures for a
|
||||
* given data sequence based on a user-configured polynomial, allowing for
|
||||
* support of any 16-bit or 32-bit polynomial including but not limited to:
|
||||
* * CRC32-IS03309
|
||||
* * CRC16-ITT
|
||||
* * CRC-32C
|
||||
* * CRC-32K
|
||||
* * CRC-16-Profibus
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup CRCP
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_dl_crcp__include
|
||||
#define ti_dl_dl_crcp__include
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
#include <ti/driverlib/dl_common.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_CRCP__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_POLYNOMIAL_SIZE_16 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_POLYNOMIAL_SIZE_16 DL_CRCP_POLYNOMIAL_SIZE_16
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_POLYNOMIAL_SIZE_32 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_POLYNOMIAL_SIZE_32 DL_CRCP_POLYNOMIAL_SIZE_32
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_BIT_REVERSED for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_BIT_REVERSED DL_CRCP_BIT_REVERSED
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_BIT_NOT_REVERSED for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_BIT_NOT_REVERSED DL_CRCP_BIT_NOT_REVERSED
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_INPUT_ENDIANESS_LITTLE_ENDIAN for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_INPUT_ENDIANESS_LITTLE_ENDIAN \
|
||||
DL_CRCP_INPUT_ENDIANESS_LITTLE_ENDIAN
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_INPUT_ENDIANESS_BIG_ENDIAN for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_INPUT_ENDIANESS_BIG_ENDIAN DL_CRCP_INPUT_ENDIANESS_BIG_ENDIAN
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_OUTPUT_BYTESWAP_ENABLED for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_OUTPUT_BYTESWAP_ENABLED DL_CRCP_OUTPUT_BYTESWAP_ENABLED
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_OUTPUT_BYTESWAP_DISABLED for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_OUTPUT_BYTESWAP_DISABLED DL_CRCP_OUTPUT_BYTESWAP_DISABLED
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCPOLY_POLYNOMIAL_32_MPEG2 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCPOLY_POLYNOMIAL_32_MPEG2 DL_CRCP_CRCPOLY_POLYNOMIAL_32_MPEG2
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCPOLY_POLYNOMIAL_32_Q for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCPOLY_POLYNOMIAL_32_Q DL_CRCP_CRCPOLY_POLYNOMIAL_32_Q
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCPOLY_POLYNOMIAL_32_JAMCRC for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCPOLY_POLYNOMIAL_32_JAMCRC \
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_32_JAMCRC
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCPOLY_POLYNOMIAL_32_XFER for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCPOLY_POLYNOMIAL_32_XFER \
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_32_XFER
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCPOLY_POLYNOMIAL_32_MPEG2 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCPOLY_POLYNOMIAL_32_MPEG2 DL_CRCP_CRCPOLY_POLYNOMIAL_32_MPEG2
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCPOLY_POLYNOMIAL_16_CCIT_ZERO for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCPOLY_POLYNOMIAL_16_CCIT_ZERO \
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_16_CCIT_ZERO
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCPOLY_POLYNOMIAL_16_ARC for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCPOLY_POLYNOMIAL_16_ARC \
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_16_ARC
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCPOLY_POLYNOMIAL_16_AUG_CCIT for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCPOLY_POLYNOMIAL_16_AUG_CCIT \
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_16_AUG_CCIT
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCPOLY_POLYNOMIAL_16_BUYPASS for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCPOLY_POLYNOMIAL_16_BUYPASS \
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_16_BUYPASS
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCPOLY_POLYNOMIAL_16_CCIT_FALSE for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCPOLY_POLYNOMIAL_16_CCIT_FALSE \
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_16_CCIT_FALSE
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCPOLY_POLYNOMIAL_16_CDMA2000 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCPOLY_POLYNOMIAL_16_CDMA2000 \
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_16_CDMA2000
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCPOLY_POLYNOMIAL_16_MODBUS for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCPOLY_POLYNOMIAL_16_MODBUS \
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_16_MODBUS
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCSEED_SEED_32_MPEG2 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCSEED_SEED_32_MPEG2 DL_CRCP_CRCSEED_SEED_32_MPEG2
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCSEED_SEED_32_Q for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCSEED_SEED_32_Q DL_CRCP_CRCSEED_SEED_32_Q
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCSEED_SEED_32_JAMCRC for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCSEED_SEED_32_JAMCRC DL_CRCP_CRCSEED_SEED_32_JAMCRC
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCSEED_SEED_32_XFER for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCSEED_SEED_32_XFER DL_CRCP_CRCSEED_SEED_32_XFER
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCSEED_SEED_32_MPEG2 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCSEED_SEED_32_MPEG2 DL_CRCP_CRCSEED_SEED_32_MPEG2
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCSEED_SEED_16_AUG_CCIT for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCSEED_SEED_16_AUG_CCIT DL_CRCP_CRCSEED_SEED_16_AUG_CCIT
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCSEED_SEED_16_BUYPASS for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCSEED_SEED_16_BUYPASS DL_CRCP_CRCSEED_SEED_16_BUYPASS
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCSEED_SEED_16_CCIT_FALSE for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCSEED_SEED_16_CCIT_FALSE DL_CRCP_CRCSEED_SEED_16_CCIT_FALSE
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCSEED_SEED_16_CDMA2000 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCSEED_SEED_16_CDMA2000 DL_CRCP_CRCSEED_SEED_16_CDMA2000
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_CRCSEED_SEED_16_MODBUS for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_CRCSEED_SEED_16_MODBUS DL_CRCP_CRCSEED_SEED_16_MODBUS
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_enablePower for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_enablePower DL_CRCP_enablePower
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_isPowerEnabled for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_isPowerEnabled DL_CRCP_isPowerEnabled
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_reset for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_reset DL_CRCP_reset
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_isReset for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_isReset DL_CRCP_isReset
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_init for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_init DL_CRCP_init
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_setSeed16 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_setSeed16 DL_CRCP_setSeed16
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_setSeed32 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_setSeed32 DL_CRCP_setSeed32
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_feedData8 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_feedData8 DL_CRCP_feedData8
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_feedData16 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_feedData16 DL_CRCP_feedData16
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_feedData32 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_feedData32 DL_CRCP_feedData32
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_getResult16 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_getResult16 DL_CRCP_getResult16
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_getResult32 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_getResult32 DL_CRCP_getResult32
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_setPolynomial for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_setPolynomial DL_CRCP_setPolynomial
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_getPolynomial for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_getPolynomial DL_CRCP_getPolynomial
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_calculateBlock32 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_calculateBlock32 DL_CRCP_calculateBlock32
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_calculateMemoryRange32 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_calculateMemoryRange32 DL_CRCP_calculateMemoryRange32
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_calculateBlock16 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_calculateBlock16 DL_CRCP_calculateBlock16
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_calculateMemoryRange16 for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_calculateMemoryRange16 DL_CRCP_calculateMemoryRange16
|
||||
|
||||
/**
|
||||
* @brief Redirects to @ref DL_CRCP_getCRCINAddr for compatibility
|
||||
* between CRC and CRCP DriverLib modules
|
||||
*/
|
||||
#define DL_CRC_getCRCINAddr DL_CRCP_getCRCINAddr
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
/*! @enum DL_CRCP_POLYNOMIAL_SIZE */
|
||||
typedef enum {
|
||||
/*! Use lower 16-bit value of CRCPOLY as polynomial for calculation.
|
||||
* Upon reset, user will need to update polynomial value for 16-bits,
|
||||
* such as the CRC-16-CCITT standard of 0x1021. */
|
||||
DL_CRCP_POLYNOMIAL_SIZE_16 = CRCP_CRCCTRL_POLYSIZE_CRC16,
|
||||
/*! Use 32-bit polynomial value of CRCPOLY as polynomial for calculation.
|
||||
* Defaults to the CRC32-ISO3309 standard value of 0x04C11DB7. */
|
||||
DL_CRCP_POLYNOMIAL_SIZE_32 = CRCP_CRCCTRL_POLYSIZE_CRC32
|
||||
} DL_CRCP_POLYNOMIAL_SIZE;
|
||||
|
||||
/*! @enum DL_CRCP_BIT */
|
||||
typedef enum {
|
||||
/*! CRCP Bit Input and output bit orders are reversed */
|
||||
DL_CRCP_BIT_REVERSED = CRCP_CRCCTRL_BITREVERSE_REVERSED,
|
||||
/*! CRCP Bit Input and output are not reversed */
|
||||
DL_CRCP_BIT_NOT_REVERSED = CRCP_CRCCTRL_BITREVERSE_NOT_REVERSED
|
||||
} DL_CRCP_BIT;
|
||||
|
||||
/*! @enum DL_CRCP_INPUT_ENDIANESS */
|
||||
typedef enum {
|
||||
/*! CRCP Input is proccessed in little endian.
|
||||
* LSB is lowest memory address and first to be processed. */
|
||||
DL_CRCP_INPUT_ENDIANESS_LITTLE_ENDIAN =
|
||||
CRCP_CRCCTRL_INPUT_ENDIANNESS_LITTLE_ENDIAN,
|
||||
/*! CRCP Input is proccessed in big endian.
|
||||
* LSB is highest memory address and last to be processed. */
|
||||
DL_CRCP_INPUT_ENDIANESS_BIG_ENDIAN =
|
||||
CRCP_CRCCTRL_INPUT_ENDIANNESS_BIG_ENDIAN
|
||||
} DL_CRCP_INPUT_ENDIANESS;
|
||||
|
||||
/*! @enum DL_CRCP_OUTPUT_BYTESWAP */
|
||||
typedef enum {
|
||||
/*! CRCP output byteswap is enabled */
|
||||
DL_CRCP_OUTPUT_BYTESWAP_ENABLED = CRCP_CRCCTRL_OUTPUT_BYTESWAP_ENABLE,
|
||||
/*! CRCP output byteswap is disabled */
|
||||
DL_CRCP_OUTPUT_BYTESWAP_DISABLED = CRCP_CRCCTRL_OUTPUT_BYTESWAP_DISABLE
|
||||
} DL_CRCP_OUTPUT_BYTESWAP;
|
||||
|
||||
/*! @enum DL_CRCP_CRCPOLY_POLYNOMIAL
|
||||
*
|
||||
* @brief commonly used pre-defined polynomials to be used by CRCP
|
||||
* as mentioned by the website
|
||||
* http://www.sunshine2k.de/coding/javascript/crc/crc_js.html.
|
||||
* Custom polynomials can also be used in lieu of the follwoing.
|
||||
*/
|
||||
typedef enum {
|
||||
|
||||
/*! CRCP commonly used polynomial CRC32_MPEG2. To match online output,
|
||||
* seed value must be set to 0xFFFFFFFF */
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_32_MPEG2 = 0x04C11DB7,
|
||||
/*! CRCP commonly used polynomial CRC32_Q. To match online output,
|
||||
* seed value must be set to 0x00000000 */
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_32_Q = 0x814141AB,
|
||||
/*! CRCP commonly used polynomial CRC32_JAMCRC. To match online output,
|
||||
* seed value must be set to 0xFFFFFFFF and bit order reversed */
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_32_JAMCRC = 0x04C11DB7,
|
||||
/*! CRCP commonly used polynomial CRC32_XFER. To match online output,
|
||||
* seed value must be set to 0x00000000 */
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_32_XFER = 0x000000AF,
|
||||
/*! CRCP commonly used polynomial CRC16_CCIT_ZERO. To match online
|
||||
* output, seed value must be set to 0x0000 */
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_16_CCIT_ZERO = 0x00001021,
|
||||
/*! CRCP commonly used polynomial CRC16_ARC. To match online output,
|
||||
* seed value must be set to 0x0000 and bit order reversed */
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_16_ARC = 0x00001DCF,
|
||||
/*! CRCP commonly used polynomial CRC16_AUG_CCIT. To match online output,
|
||||
* seed value must be set to 0x1D0F */
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_16_AUG_CCIT = 0x00001021,
|
||||
/*! CRCP commonly used polynomial CRC16_BUYPASS. To match online output,
|
||||
* seed value must be set to 0x0000 */
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_16_BUYPASS = 0x00008005,
|
||||
/*! CRCP commonly used polynomial CRC16_CCIT_FALSE. To match online output,
|
||||
* seed value must be set to 0xFFFF */
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_16_CCIT_FALSE = 0x00001021,
|
||||
/*! CRCP commonly used polynomial CRC16_CDMA2000. To match online output,
|
||||
* seed value must be set to 0xFFFF */
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_16_CDMA2000 = 0x0000C867,
|
||||
/*! CRCP commonly used polynomial CRC16_MODBUS. To match online output,
|
||||
* seed value must be set to 0xFFFF and bit order reversed */
|
||||
DL_CRCP_CRCPOLY_POLYNOMIAL_16_MODBUS = 0x00001DCF,
|
||||
|
||||
} DL_CRCP_CRCPOLY_POLYNOMIAL;
|
||||
|
||||
/*! @enum DL_CRCP_CRCSEED_SEED
|
||||
*
|
||||
* @brief seeds for commonly used pre-defined polynomials to be used
|
||||
* by CRCP as mentioned by the website
|
||||
* http://www.sunshine2k.de/coding/javascript/crc/crc_js.html.
|
||||
* Custom polynomials can also be used in lieu of the follwoing.
|
||||
*/
|
||||
typedef enum {
|
||||
|
||||
/*! CRCP commonly used polynomial CRC32_MPEG2. To match online output,
|
||||
* polynomial must be set to 0x04C11DB7 */
|
||||
DL_CRCP_CRCSEED_SEED_32_MPEG2 = 0xFFFFFFFF,
|
||||
/*! CRCP commonly used polynomial CRC32_Q. To match online output,
|
||||
* polynomial must be set to 0x814141AB */
|
||||
DL_CRCP_CRCSEED_SEED_32_Q = 0x00000000,
|
||||
/*! CRCP commonly used polynomial CRC32_JAMCRC. To match online output,
|
||||
* polynomial must be set to 0x04C11DB7 and bit order reversed */
|
||||
DL_CRCP_CRCSEED_SEED_32_JAMCRC = 0xFFFFFFFF,
|
||||
/*! CRCP commonly used polynomial CRC32_XFER. To match online output,
|
||||
* polynomial must be set to 0x000000AF */
|
||||
DL_CRCP_CRCSEED_SEED_32_XFER = 0x00000000,
|
||||
/*! CRCP commonly used polynomial CRC16_CCIT_ZERO. To match online
|
||||
* output, polynomial must be set to 0x00001021 */
|
||||
DL_CRCP_CRCSEED_SEED_16_CCIT_ZERO = 0x0000,
|
||||
/*! CRCP commonly used polynomial CRC16_ARC. To match online output,
|
||||
* polynomial must be set to 0x00001DCF and bit order reversed */
|
||||
DL_CRCP_CRCSEED_SEED_16_ARC = 0x0000,
|
||||
/*! CRCP commonly used polynomial CRC16_AUG_CCIT. To match online output,
|
||||
* polynomial must be set to 0x00001021 */
|
||||
DL_CRCP_CRCSEED_SEED_16_AUG_CCIT = 0x1D0F,
|
||||
/*! CRCP commonly used polynomial CRC16_BUYPASS. To match online output,
|
||||
* polynomial must be set to 0x00008005 */
|
||||
DL_CRCP_CRCSEED_SEED_16_BUYPASS = 0x0000,
|
||||
/*! CRCP commonly used polynomial CRC16_CCIT_FALSE. To match online output,
|
||||
* polynomial must be set to 0x00001021 */
|
||||
DL_CRCP_CRCSEED_SEED_16_CCIT_FALSE = 0xFFFF,
|
||||
/*! CRCP commonly used polynomial CRC16_CDMA2000. To match online output,
|
||||
* polynomial must be set to 0x0000C867 */
|
||||
DL_CRCP_CRCSEED_SEED_16_CDMA2000 = 0xFFFF,
|
||||
/*! CRCP commonly used polynomial CRC16_MODBUS. To match online output,
|
||||
* polynomial must be set to 0x00001DCF and bit order reversed */
|
||||
DL_CRCP_CRCSEED_SEED_16_MODBUS = 0xFFFF,
|
||||
|
||||
} DL_CRCP_CRCSEED_SEED;
|
||||
|
||||
/**
|
||||
* @brief Enables the Peripheral Write Enable (PWREN) register for the CRCP
|
||||
*
|
||||
* Before any peripheral registers can be configured by software, the
|
||||
* peripheral itself must be enabled by writing the ENABLE bit together with
|
||||
* the appropriate KEY value to the peripheral's PWREN register.
|
||||
*
|
||||
* @param crcp Pointer to the register overlay for the CRCP peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRCP_enablePower(CRCP_Regs *crcp)
|
||||
{
|
||||
crcp->GPRCM.PWREN = (CRCP_PWREN_KEY_UNLOCK_W | CRCP_PWREN_ENABLE_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Peripheral Write Enable (PWREN) register for the CRCP
|
||||
*
|
||||
* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
|
||||
* accessible for read/write operations.
|
||||
*
|
||||
* @note This API does not provide large power savings.
|
||||
*
|
||||
* @param crcp Pointer to the register overlay for the CRCP peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRCP_disablePower(CRCP_Regs *crcp)
|
||||
{
|
||||
crcp->GPRCM.PWREN = (CRCP_PWREN_KEY_UNLOCK_W | CRCP_PWREN_ENABLE_DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if the Peripheral Write Enable (PWREN) register for the CRCP
|
||||
* is enabled
|
||||
*
|
||||
* Before any peripheral registers can be configured by software, the
|
||||
* peripheral itself must be enabled by writing the ENABLE bit together with
|
||||
* the appropriate KEY value to the peripheral's PWREN register.
|
||||
*
|
||||
* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
|
||||
* accessible for read/write operations.
|
||||
*
|
||||
* @param crcp Pointer to the register overlay for the CRCP peripheral
|
||||
*
|
||||
* @return true if peripheral register access is enabled
|
||||
* @return false if peripheral register access is disabled
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE bool DL_CRCP_isPowerEnabled(const CRCP_Regs *crcp)
|
||||
{
|
||||
return ((crcp->GPRCM.PWREN & CRCP_PWREN_ENABLE_MASK) ==
|
||||
CRCP_PWREN_ENABLE_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets CRCP peripheral
|
||||
*
|
||||
* @param crcp Pointer to the register overlay for the CRCP peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRCP_reset(CRCP_Regs *crcp)
|
||||
{
|
||||
crcp->GPRCM.RSTCTL =
|
||||
(CRCP_RSTCTL_KEY_UNLOCK_W | CRCP_RSTCTL_RESETSTKYCLR_CLR |
|
||||
CRCP_RSTCTL_RESETASSERT_ASSERT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if CRCP module has been reset
|
||||
*
|
||||
* @param crcp Pointer to the register overlay for the CRCP peripheral
|
||||
*
|
||||
* @return true if peripheral was reset
|
||||
* @return false if peripheral wasn't reset
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE bool DL_CRCP_isReset(const CRCP_Regs *crcp)
|
||||
{
|
||||
return ((crcp->GPRCM.STAT & CRCP_STAT_RESETSTKY_MASK) ==
|
||||
CRCP_STAT_RESETSTKY_RESET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the CRCP peripheral
|
||||
*
|
||||
* @param crcp Pointer to the register overlay for the CRCP peripheral.
|
||||
* @param polySize Selects CRC polynomial size. One of
|
||||
* @ref DL_CRCP_POLYNOMIAL_SIZE.
|
||||
* @param bitOrd Selects CRC bit order. One of @ref DL_CRCP_BIT.
|
||||
* @param inEndianness Selects CRC input endianess. One of
|
||||
* @ref DL_CRCP_INPUT_ENDIANESS.
|
||||
* @param outByteSwap Selects CRC output byte swap mode. One of
|
||||
* @ref DL_CRCP_OUTPUT_BYTESWAP.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRCP_init(CRCP_Regs *crcp,
|
||||
DL_CRCP_POLYNOMIAL_SIZE polySize, DL_CRCP_BIT bitOrd,
|
||||
DL_CRCP_INPUT_ENDIANESS inEndianness, DL_CRCP_OUTPUT_BYTESWAP outByteSwap)
|
||||
{
|
||||
crcp->CRCCTRL = ((uint32_t) polySize | (uint32_t) bitOrd |
|
||||
(uint32_t) inEndianness | (uint32_t) outByteSwap);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Initializes the seed for a 16-bit polynomial CRC calculation
|
||||
* @note CRC seed is swapped when CRCP module is configured in big-endian
|
||||
* mode. For example when calling DL_CRCP_setSeed32(CRC, 0xaabb).
|
||||
* The CRCP module will be initialized with 0xbbaa. Therefore, the
|
||||
* seed value should be appropriately specified taking endianness
|
||||
* into account. Please refer to the device TRM for additional
|
||||
* detail.
|
||||
*
|
||||
* Sets the inital seed for a 16-bit CRC calculation. can be any value,
|
||||
* or cast one of the common seeds in @ref DL_CRCP_CRCSEED_SEED.
|
||||
*
|
||||
* @param[in] crcp Pointer to the register overlay for the CRCP peripheral
|
||||
* @param[in] seed The seed from which to start generating a signature
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRCP_setSeed16(CRCP_Regs *crcp, uint16_t seed)
|
||||
{
|
||||
volatile uintptr_t addr;
|
||||
volatile uint16_t *pRef;
|
||||
|
||||
addr = (uintptr_t)((volatile uintptr_t *) &crcp->CRCSEED);
|
||||
pRef = (volatile uint16_t *) addr;
|
||||
|
||||
*pRef = seed;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Initializes the seed for a 32-bit polynomial CRC calculation
|
||||
* @note CRC seed is swapped when CRCP module is configured in big-endian
|
||||
* mode. For example when calling DL_CRCP_setSeed32(CRC, 0xaabbccdd).
|
||||
* The CRCP module will be initialized with 0xddccbbaa. Therefore,
|
||||
* the seed value should be appropriately specified taking endianness
|
||||
* into account. Please refer to the device TRM for additional
|
||||
* detail.
|
||||
*
|
||||
* Sets the inital seed for a 32-bit CRC calculation. can be any value,
|
||||
* or cast one of the common seeds in @ref DL_CRCP_CRCSEED_SEED.
|
||||
*
|
||||
* @param[in] crcp Pointer to the register overlay for the CRCP peripheral
|
||||
* @param[in] seed The seed from which to start generating a signature
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRCP_setSeed32(CRCP_Regs *crcp, uint32_t seed)
|
||||
{
|
||||
crcp->CRCSEED = seed;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Feeds 8-bit data into the CRC calculation
|
||||
*
|
||||
* @param[in] crcp Pointer to the register overlay for the CRCP
|
||||
* peripheral
|
||||
* @param[in] dataIn 8-bit data value to add to the signature
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRCP_feedData8(CRCP_Regs *crcp, uint8_t dataIn)
|
||||
{
|
||||
volatile uint8_t *pRef = (volatile uint8_t *) &crcp->CRCIN;
|
||||
*pRef = dataIn;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Feeds 16-bit data into the CRC calculation
|
||||
*
|
||||
* @param[in] crcp Pointer to the register overlay for the CRCP
|
||||
* peripheral
|
||||
* @param[in] dataIn 16-bit data value to add to the signature
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRCP_feedData16(CRCP_Regs *crcp, uint16_t dataIn)
|
||||
{
|
||||
volatile uintptr_t addr;
|
||||
volatile uint16_t *pRef;
|
||||
|
||||
addr = (uintptr_t)((volatile uintptr_t *) &crcp->CRCIN);
|
||||
pRef = (volatile uint16_t *) addr;
|
||||
|
||||
*pRef = dataIn;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Feeds 32-bit data into the CRC calculation
|
||||
*
|
||||
* Feeds a 32-bit value into the CRC calculation. 32-bit data can only be used
|
||||
* with the 32-bit polynomial.
|
||||
*
|
||||
* @param[in] crcp Pointer to the register overlay for the CRCP
|
||||
* peripheral
|
||||
* @param[in] dataIn 32 bit data value to add to the signature
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRCP_feedData32(CRCP_Regs *crcp, uint32_t dataIn)
|
||||
{
|
||||
crcp->CRCIN = dataIn;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Returns the result from the 16-bit polynomial calculation
|
||||
*
|
||||
* @note CRC Output will be swapped if the CRCP module is configured
|
||||
* in byte-swap mode. For example, if enabled and CRCOUT register
|
||||
* has the value 0xaabbccdd, DL_CRCP_getResult16 would return
|
||||
* 0xddcc. Please refer to the TRM for more information.
|
||||
*
|
||||
* @param[in] crcp Pointer to the register overlay for the CRCP peripheral
|
||||
*
|
||||
* @return The calculation result for the 16-bit polynomial
|
||||
*/
|
||||
__STATIC_INLINE uint16_t DL_CRCP_getResult16(const CRCP_Regs *crcp)
|
||||
{
|
||||
return ((uint16_t) crcp->CRCOUT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Returns the result from the 32-bit polynomial calculation
|
||||
*
|
||||
* @note CRC Output will be swapped if the CRCP module is configured
|
||||
* in byte-swap mode. For example, if enabled and CRCOUT register
|
||||
* has value 0xaabbccdd, DL_CRCP_getResult32 would return
|
||||
* 0xddccbbaa in the 32-bit case, and 0x0000ddcc. In the 16-bit
|
||||
* case. Additionally, if byte-swap is disabled, the 16-bit size
|
||||
* would return 0x0000ccdd. Please refer to the TRM for more
|
||||
* information.
|
||||
*
|
||||
* @param[in] crcp Pointer to the register overlay for the CRCP peripheral
|
||||
*
|
||||
* @return The calculation result for the 32-bit polynomial
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_CRCP_getResult32(const CRCP_Regs *crcp)
|
||||
{
|
||||
return (crcp->CRCOUT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the active polynomial terms for the CRC calculation
|
||||
*
|
||||
* The polynomial can be any value represented with MSB first. Thus, in a
|
||||
* 16-bit polynomial (where the 16th power is always present), the nth bit
|
||||
* corresponds to the inclusion of the nth term of the polynomial. For example,
|
||||
* The 16-bit polynomial CCIT x^16 + x^12 + x^5 + 1 is represented as 0x1021.
|
||||
* One can craft a custom polynomial, use an existing polynomial,
|
||||
* or cast one of the common polynomials in @ref DL_CRCP_CRCPOLY_POLYNOMIAL. If
|
||||
* the polynomial size is configured as 16-bit, the upper 16-bits are ignored.
|
||||
*
|
||||
* @param[in] crcp Pointer to the register overlay for the CRCP peripheral
|
||||
* @param[in] poly Polynomial to implement (normal representation)
|
||||
*/
|
||||
__STATIC_INLINE void DL_CRCP_setPolynomial(CRCP_Regs *crcp, uint32_t poly)
|
||||
{
|
||||
crcp->CRCPOLY = poly;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the active polynomial terms for the CRC calculation
|
||||
*
|
||||
* The polynomial can be any value represented as with MSB first. Thus, in a
|
||||
* 16-bit polynomial (where the 16th power is always present), the nth bit
|
||||
* corresponds to the inclusion of the nth term of the polynomial. For example,
|
||||
* The 16-bit polynomial CCIT x^16 + x^12 + x^5 + 1 is represented as 0x1021.
|
||||
* If the polynomial size is configured as 16-bit, the upper 16-bits are ignored.
|
||||
*
|
||||
* @param[in] crcp Pointer to the register overlay for the CRCP peripheral
|
||||
*
|
||||
* @returns Active polynomial (normal representation)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_CRCP_getPolynomial(const CRCP_Regs *crcp)
|
||||
{
|
||||
return (crcp->CRCPOLY);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Calculates the CRC over a range of 32-bit values
|
||||
*
|
||||
* Uses the 32-bit polynomial to calculate the checksum over a block of
|
||||
* values.
|
||||
*
|
||||
* @param[in] crcp Pointer to the register overlay for the CRCP peripheral
|
||||
* @param[in] seed The seed for the CRC to start generating a signature from
|
||||
* @param[in] ptr A pointer to the block of code to calculate the CRC over
|
||||
* @param[in] size The size of the block of uint32_t data
|
||||
*
|
||||
* @return The calculated CRC signature value
|
||||
*/
|
||||
extern uint32_t DL_CRCP_calculateBlock32(
|
||||
CRCP_Regs *crcp, uint32_t seed, const uint32_t *ptr, uint32_t size);
|
||||
|
||||
/*!
|
||||
* @brief Calculates the CRC over a memory range
|
||||
*
|
||||
* Calculates the checksum using the 32-bit polynomial over any memory range.
|
||||
*
|
||||
* @param[in] crcp Pointer to the register overlay for the CRC
|
||||
* peripheral
|
||||
* @param[in] seed The seed used to start generating a signature from
|
||||
* @param[in] ptrStart A uint32_t pointer to the start of a block of code to
|
||||
* calculate the CRC over
|
||||
* @param[in] ptrEnd A uint32_t pointer to the end of a block of code to
|
||||
* calculate the CRC over
|
||||
*
|
||||
* @return The calculated CRC signature value
|
||||
*/
|
||||
extern uint32_t DL_CRCP_calculateMemoryRange32(CRCP_Regs *crcp, uint32_t seed,
|
||||
uint32_t *ptrStart, const uint32_t *ptrEnd);
|
||||
|
||||
/*!
|
||||
* @brief Calculates the CRC over a range of 16-bit values
|
||||
*
|
||||
* Uses the 16-bit polynomial to calculate the checksum over a block of
|
||||
* values.
|
||||
*
|
||||
* @param[in] crcp Pointer to the register overlay for the CRCP peripheral
|
||||
* @param[in] seed The seed for the CRCP to start generating a signature from
|
||||
* @param[in] ptr A pointer to the block of code to calculate the CRC over
|
||||
* @param[in] size The size of the block of 16-bit data
|
||||
*
|
||||
* @return The calculated CRC signature value
|
||||
*/
|
||||
extern uint16_t DL_CRCP_calculateBlock16(
|
||||
CRCP_Regs *crcp, uint16_t seed, const uint16_t *ptr, uint16_t size);
|
||||
|
||||
/*!
|
||||
* @brief Calculates the CRC over a memory range
|
||||
*
|
||||
* Calculates the checksum using the 16-bit polynomial over any memory range.
|
||||
*
|
||||
* @param[in] crcp Pointer to the register overlay for the CRC
|
||||
* peripheral
|
||||
* @param[in] seed The seed used to start generating a signature from
|
||||
* @param[in] ptrStart A uint16_t pointer to the start of a block of code to
|
||||
* calculate the CRC over
|
||||
* @param[in] ptrEnd A uint16_t pointer to the end of a block of code to
|
||||
* calculate the CRC over
|
||||
*
|
||||
* @return The calculated CRC signature value
|
||||
*/
|
||||
extern uint16_t DL_CRCP_calculateMemoryRange16(CRCP_Regs *crcp, uint16_t seed,
|
||||
uint16_t *ptrStart, const uint16_t *ptrEnd);
|
||||
|
||||
/**
|
||||
* @brief Returns the address of the CRC input data register.
|
||||
*
|
||||
* This API can be used with @ref DL_DMA_setDestAddr to set the destination
|
||||
* address when using DMA transfers
|
||||
*
|
||||
* @param[in] crcp Pointer to the register overlay for the CRC
|
||||
* peripheral
|
||||
* @return Address of the CRC input data register
|
||||
*/
|
||||
__STATIC_INLINE uintptr_t DL_CRCP_getCRCINAddr(const CRCP_Regs *crcp)
|
||||
{
|
||||
return ((uintptr_t) &crcp->CRCIN);
|
||||
}
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MSPM0_HAS_CRCP__ */
|
||||
|
||||
#endif /* ti_dl_DL_CRCP__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,126 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_dac12.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_DAC12__
|
||||
|
||||
void DL_DAC12_init(DAC12_Regs *dac12, const DL_DAC12_Config *config)
|
||||
{
|
||||
/* CTL 0 - Input Data Formatting */
|
||||
DL_DAC12_configDataFormat(
|
||||
dac12, config->representation, config->resolution);
|
||||
|
||||
/* CTL 1 - DAC Module */
|
||||
DL_Common_updateReg(&dac12->CTL1,
|
||||
(uint32_t) config->outputEnable |
|
||||
(uint32_t) config->voltageReferenceSource |
|
||||
(uint32_t) config->amplifierSetting,
|
||||
DAC12_CTL1_OPS_MASK | DAC12_CTL1_REFSP_MASK | DAC12_CTL1_REFSN_MASK |
|
||||
DAC12_CTL1_AMPEN_MASK | DAC12_CTL1_AMPHIZ_MASK);
|
||||
|
||||
/* CTL 2 - FIFO */
|
||||
DL_Common_updateReg(&dac12->CTL2,
|
||||
((uint32_t) config->fifoEnable | (uint32_t) config->fifoTriggerSource |
|
||||
(uint32_t) config->dmaTriggerEnable |
|
||||
(uint32_t) config->dmaTriggerThreshold),
|
||||
DAC12_CTL2_DMATRIGEN_MASK | DAC12_CTL2_FIFOTH_MASK |
|
||||
DAC12_CTL2_FIFOEN_MASK | DAC12_CTL2_FIFOTRIGSEL_MASK);
|
||||
|
||||
/* CTL3 Register - Sample Time Generator */
|
||||
DL_Common_updateReg(&dac12->CTL3,
|
||||
((uint32_t) config->sampleTimeGeneratorEnable |
|
||||
(uint32_t) config->sampleRate),
|
||||
DAC12_CTL3_STIMCONFIG_MASK | DAC12_CTL3_STIMEN_MASK);
|
||||
}
|
||||
|
||||
void DL_DAC12_outputBlocking8(DAC12_Regs *dac12, uint8_t data)
|
||||
{
|
||||
while (DL_DAC12_isFIFOFull(dac12)) {
|
||||
;
|
||||
}
|
||||
|
||||
DL_DAC12_output8(dac12, data);
|
||||
}
|
||||
|
||||
void DL_DAC12_outputBlocking12(DAC12_Regs *dac12, uint16_t data)
|
||||
{
|
||||
while (DL_DAC12_isFIFOFull(dac12)) {
|
||||
;
|
||||
}
|
||||
|
||||
DL_DAC12_output12(dac12, data);
|
||||
}
|
||||
|
||||
uint32_t DL_DAC12_fillFIFO8(
|
||||
DAC12_Regs *dac12, const uint8_t *buffer, uint32_t count)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0; i < count; i++) {
|
||||
if (!DL_DAC12_isFIFOFull(dac12)) {
|
||||
DL_DAC12_output8(dac12, buffer[i]);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
uint32_t DL_DAC12_fillFIFO12(
|
||||
DAC12_Regs *dac12, const uint16_t *buffer, uint32_t count)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0; i < count; i++) {
|
||||
if (!DL_DAC12_isFIFOFull(dac12)) {
|
||||
DL_DAC12_output12(dac12, buffer[i]);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
void DL_DAC12_performSelfCalibrationBlocking(DAC12_Regs *dac12)
|
||||
{
|
||||
DL_DAC12_startCalibration(dac12);
|
||||
/*
|
||||
* Tri-stated during calibration, and CALON will continue to be set
|
||||
* Prevents the function from exiting until the calibration is finished.
|
||||
*/
|
||||
while (DL_DAC12_isCalibrationRunning(dac12)) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_DAC12__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_dma.h>
|
||||
|
||||
void DL_DMA_initChannel(
|
||||
DMA_Regs *dma, uint8_t channelNum, const DL_DMA_Config *config)
|
||||
{
|
||||
DL_DMA_configTransfer(dma, channelNum, config->transferMode,
|
||||
config->extendedMode, config->srcWidth, config->destWidth,
|
||||
config->srcIncrement, config->destIncrement);
|
||||
|
||||
DL_DMA_setTrigger(dma, channelNum, config->trigger, config->triggerType);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2025, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_gpamp.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_GPAMP__
|
||||
#endif /* __MSPM0_HAS_GPAMP__ */
|
||||
@@ -0,0 +1,365 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_gpamp.h
|
||||
* @brief General Purpose Amplifier (GPAMP)
|
||||
* @defgroup GPAMP General Purpose Amplifier (GPAMP)
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup GPAMP
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_m0p_dl_gpamp__include
|
||||
#define ti_dl_m0p_dl_gpamp__include
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
#include <ti/driverlib/dl_common.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_GPAMP__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*! @enum DL_GPAMP_NSEL */
|
||||
typedef enum {
|
||||
/*! Inverting input channel is the output pin */
|
||||
DL_GPAMP_NSEL_OUTPUT_PIN = SYSCTL_PMUOPAMP_NSEL_SEL0,
|
||||
/*! Inverting input channel is the IN- pin */
|
||||
DL_GPAMP_NSEL_IN_NEG = SYSCTL_PMUOPAMP_NSEL_SEL1,
|
||||
/*! Inverting input channel is internal GPAMP output */
|
||||
DL_GPAMP_NSEL_INTERNAL_OUTPUT = SYSCTL_PMUOPAMP_NSEL_SEL2,
|
||||
/*! No channel selected for the inverting input channel */
|
||||
DL_GPAMP_NSEL_OPEN = SYSCTL_PMUOPAMP_NSEL_SEL3,
|
||||
} DL_GPAMP_NSEL;
|
||||
|
||||
/*! @enum DL_GPAMP_PSEL */
|
||||
typedef enum {
|
||||
/*! Non-Inverting input channel is disabled */
|
||||
DL_GPAMP_PSEL_OPEN = SYSCTL_PMUOPAMP_PCHENABLE_FALSE,
|
||||
/*! Non-Inverting input channel is enabled */
|
||||
DL_GPAMP_PSEL_IN_POS = SYSCTL_PMUOPAMP_PCHENABLE_TRUE,
|
||||
} DL_GPAMP_PSEL;
|
||||
|
||||
/*! @enum DL_GPAMP_OUTPUT_PIN_STATE */
|
||||
typedef enum {
|
||||
/*! Output pin is disabled */
|
||||
DL_GPAMP_OUTPUT_PIN_STATE_DISABLED = SYSCTL_PMUOPAMP_OUTENABLE_FALSE,
|
||||
/*! Output pin is enabled */
|
||||
DL_GPAMP_OUTPUT_PIN_STATE_ENABLED = SYSCTL_PMUOPAMP_OUTENABLE_TRUE,
|
||||
} DL_GPAMP_OUTPUT_PIN_STATE;
|
||||
|
||||
/*! @enum DL_GPAMP_RRI_MODE */
|
||||
typedef enum {
|
||||
/*! RRI mode is PMOS input pairs mode */
|
||||
DL_GPAMP_RRI_MODE_PMOS_INPUT = SYSCTL_PMUOPAMP_RRI_MODE0,
|
||||
/*! RRI mode is NMOS input pairs */
|
||||
DL_GPAMP_RRI_MODE_NMOS_INPUT = SYSCTL_PMUOPAMP_RRI_MODE1,
|
||||
/*! RRI mode is rail to rail*/
|
||||
DL_GPAMP_RRI_MODE_RAIL_TO_RAIL = SYSCTL_PMUOPAMP_RRI_MODE2,
|
||||
/*! RRI mode is sample channel 0*/
|
||||
DL_GPAMP_RRI_MODE_SAMPLE_CHANNEL_0 = SYSCTL_PMUOPAMP_RRI_MODE3,
|
||||
|
||||
} DL_GPAMP_RRI_MODE;
|
||||
|
||||
/*! @enum DL_GPAMP_CHOPPING_FREQ */
|
||||
typedef enum {
|
||||
/*! Chopping clock frequency is 16KHZ */
|
||||
DL_GPAMP_CHOPPING_FREQ_16KHZ = SYSCTL_PMUOPAMP_CHOPCLKFREQ_CLK16KHZ,
|
||||
/*! Chopping clock frequency is 8KHZ */
|
||||
DL_GPAMP_CHOPPING_FREQ_8KHZ = SYSCTL_PMUOPAMP_CHOPCLKFREQ_CLK8KHZ,
|
||||
/*! Chopping clock frequency is 4KHZ */
|
||||
DL_GPAMP_CHOPPING_FREQ_4KHZ = SYSCTL_PMUOPAMP_CHOPCLKFREQ_CLK4KHZ,
|
||||
/*! Chopping clock frequency is 2KHZ */
|
||||
DL_GPAMP_CHOPPING_FREQ_2KHZ = SYSCTL_PMUOPAMP_CHOPCLKFREQ_CLK2KHZ,
|
||||
} DL_GPAMP_CHOPPING_FREQ;
|
||||
|
||||
/*! @enum DL_GPAMP_CHOPPING_MODE */
|
||||
typedef enum {
|
||||
/*! Chopping is disabled */
|
||||
DL_GPAMP_CHOPPING_MODE_DISABLED = SYSCTL_PMUOPAMP_CHOPCLKMODE_CHOPDISABLED,
|
||||
/*! Chopping mode is standard chop */
|
||||
DL_GPAMP_CHOPPING_MODE_STANDARD = SYSCTL_PMUOPAMP_CHOPCLKMODE_REGCHOP,
|
||||
/*! Chopping mode is ADC assisted chop */
|
||||
DL_GPAMP_CHOPPING_MODE_ADC_ASSISTED =
|
||||
SYSCTL_PMUOPAMP_CHOPCLKMODE_ADCASSIST,
|
||||
} DL_GPAMP_CHOPPING_MODE;
|
||||
|
||||
/*!
|
||||
* @brief Configuration struct for @ref DL_GPAMP_init
|
||||
*/
|
||||
typedef struct {
|
||||
/*! The chopping mode to set. One of @ref DL_GPAMP_CHOPPING_MODE */
|
||||
DL_GPAMP_CHOPPING_MODE choppingMode;
|
||||
/*! The chopping frequency to set. One of @ref DL_GPAMP_CHOPPING_FREQ */
|
||||
DL_GPAMP_CHOPPING_FREQ choppingFreq;
|
||||
/*! The state of the output pin. One of @ref DL_GPAMP_OUTPUT_PIN_STATE. */
|
||||
DL_GPAMP_OUTPUT_PIN_STATE outputPinState;
|
||||
/*! The non-inverting input channel to set. One of @ref DL_GPAMP_PSEL */
|
||||
DL_GPAMP_PSEL pselChannel;
|
||||
/*! The inverting input channel to set. One of @ref DL_GPAMP_NSEL */
|
||||
DL_GPAMP_NSEL nselChannel;
|
||||
} DL_GPAMP_Config;
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
/**
|
||||
* @brief Enable the GPAMP peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_GPAMP_enable(void)
|
||||
{
|
||||
SYSCTL->SOCLOCK.PMUOPAMP |= SYSCTL_PMUOPAMP_ENABLE_TRUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if the GPAMP peripheral is enabled
|
||||
*
|
||||
* @return Returns the enabled status of the GPAMP
|
||||
*
|
||||
* @retval true The GPAMP peripheral is enabled
|
||||
* @retval false The GPAMP peripheral is disabled
|
||||
*/
|
||||
__STATIC_INLINE bool DL_GPAMP_isEnabled(void)
|
||||
{
|
||||
return ((SYSCTL->SOCLOCK.PMUOPAMP & SYSCTL_PMUOPAMP_ENABLE_MASK) ==
|
||||
SYSCTL_PMUOPAMP_ENABLE_TRUE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the GPAMP peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_GPAMP_disable(void)
|
||||
{
|
||||
SYSCTL->SOCLOCK.PMUOPAMP &= ~(SYSCTL_PMUOPAMP_ENABLE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the GPAmp peripheral
|
||||
*
|
||||
* Initializes all the common configurable options for the GPAmp peripheral.
|
||||
* Any other custom configuration can be done after calling this API.
|
||||
* The GPAmp is not enabled in this API.
|
||||
*
|
||||
* @param[in] config Configuration for gpamp peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_GPAMP_init(DL_GPAMP_Config *config)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.PMUOPAMP,
|
||||
(uint32_t) config->choppingMode | (uint32_t) config->choppingFreq |
|
||||
(uint32_t) config->outputPinState |
|
||||
(uint32_t) config->pselChannel | (uint32_t) config->nselChannel,
|
||||
SYSCTL_PMUOPAMP_CHOPCLKMODE_MASK | SYSCTL_PMUOPAMP_CHOPCLKFREQ_MASK |
|
||||
SYSCTL_PMUOPAMP_OUTENABLE_MASK | SYSCTL_PMUOPAMP_PCHENABLE_MASK |
|
||||
SYSCTL_PMUOPAMP_NSEL_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the non-inverting input channel
|
||||
*/
|
||||
__STATIC_INLINE void DL_GPAMP_enableNonInvertingInputChannel(void)
|
||||
{
|
||||
SYSCTL->SOCLOCK.PMUOPAMP |= SYSCTL_PMUOPAMP_PCHENABLE_TRUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if the non-inverting input channel is enabled
|
||||
*
|
||||
* @return Returns the enabled status of the GPAMP
|
||||
*
|
||||
* @retval true The non-inverting input channel is enabled
|
||||
* @retval false The non-inverting input channel is disabled
|
||||
*/
|
||||
__STATIC_INLINE bool DL_GPAMP_isNonInvertingInputChannelEnabled(void)
|
||||
{
|
||||
return ((SYSCTL->SOCLOCK.PMUOPAMP & SYSCTL_PMUOPAMP_PCHENABLE_MASK) ==
|
||||
SYSCTL_PMUOPAMP_PCHENABLE_TRUE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the non-inverting input channel
|
||||
*/
|
||||
__STATIC_INLINE void DL_GPAMP_disableNonInvertingInputChannel(void)
|
||||
{
|
||||
SYSCTL->SOCLOCK.PMUOPAMP &= ~(SYSCTL_PMUOPAMP_PCHENABLE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the inverting input channel
|
||||
*
|
||||
* @param[in] inputChannel The inverting input channel to set.
|
||||
* One of @ref DL_GPAMP_NSEL.
|
||||
*/
|
||||
__STATIC_INLINE void DL_GPAMP_setInvertingInputChannel(
|
||||
DL_GPAMP_NSEL inputChannel)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.PMUOPAMP, (uint32_t) inputChannel,
|
||||
SYSCTL_PMUOPAMP_NSEL_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the inverting input channel
|
||||
*
|
||||
* @return The current inverting input channel
|
||||
*
|
||||
* @retval One of @ref DL_GPAMP_NSEL
|
||||
*/
|
||||
__STATIC_INLINE DL_GPAMP_NSEL DL_GPAMP_getInvertingInputChannel(void)
|
||||
{
|
||||
uint32_t nsel = (SYSCTL->SOCLOCK.PMUOPAMP & SYSCTL_PMUOPAMP_NSEL_MASK);
|
||||
|
||||
return (DL_GPAMP_NSEL)(nsel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the rail-to-rail input (RRI) mode
|
||||
*
|
||||
* @param[in] mode The RRI mode to set. One of @ref DL_GPAMP_RRI_MODE.
|
||||
*/
|
||||
__STATIC_INLINE void DL_GPAMP_setRailToRailInputMode(DL_GPAMP_RRI_MODE mode)
|
||||
{
|
||||
DL_Common_updateReg(
|
||||
&SYSCTL->SOCLOCK.PMUOPAMP, (uint32_t) mode, SYSCTL_PMUOPAMP_RRI_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the rail-to-rail input (RRI) mode
|
||||
*
|
||||
* @return The current RRI mode
|
||||
*
|
||||
* @retval One of @ref DL_GPAMP_RRI_MODE
|
||||
*/
|
||||
__STATIC_INLINE DL_GPAMP_RRI_MODE DL_GPAMP_getRailToRailInputMode(void)
|
||||
{
|
||||
uint32_t mode = (SYSCTL->SOCLOCK.PMUOPAMP & SYSCTL_PMUOPAMP_RRI_MASK);
|
||||
|
||||
return (DL_GPAMP_RRI_MODE)(mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable output to pad
|
||||
*/
|
||||
__STATIC_INLINE void DL_GPAMP_enableOutputToPad(void)
|
||||
{
|
||||
SYSCTL->SOCLOCK.PMUOPAMP |= SYSCTL_PMUOPAMP_OUTENABLE_TRUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if output to pad is enabled
|
||||
*
|
||||
* @return Returns if output to pad is enabled
|
||||
*
|
||||
* @retval true Output to pad is enabled
|
||||
* @retval false Output to pad is disabled
|
||||
*/
|
||||
__STATIC_INLINE bool DL_GPAMP_isOutputToPadEnabled(void)
|
||||
{
|
||||
return ((SYSCTL->SOCLOCK.PMUOPAMP & SYSCTL_PMUOPAMP_OUTENABLE_MASK) ==
|
||||
SYSCTL_PMUOPAMP_OUTENABLE_TRUE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable output to pad
|
||||
*/
|
||||
__STATIC_INLINE void DL_GPAMP_disableOutputToPad(void)
|
||||
{
|
||||
SYSCTL->SOCLOCK.PMUOPAMP &= ~(SYSCTL_PMUOPAMP_OUTENABLE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the chopping clock frequency
|
||||
*
|
||||
* @param[in] frequency The chopping frequency to set.
|
||||
* One of @ref DL_GPAMP_CHOPPING_FREQ
|
||||
*/
|
||||
__STATIC_INLINE void DL_GPAMP_setChoppingFrequency(
|
||||
DL_GPAMP_CHOPPING_FREQ frequency)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.PMUOPAMP, (uint32_t) frequency,
|
||||
SYSCTL_PMUOPAMP_CHOPCLKFREQ_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the chopping clock frequency
|
||||
*
|
||||
* @return The current chopping frequency
|
||||
*
|
||||
* @retval One of @ref DL_GPAMP_CHOPPING_FREQ
|
||||
*/
|
||||
__STATIC_INLINE DL_GPAMP_CHOPPING_FREQ DL_GPAMP_getChoppingFrequency(void)
|
||||
{
|
||||
uint32_t freq =
|
||||
(SYSCTL->SOCLOCK.PMUOPAMP & SYSCTL_PMUOPAMP_CHOPCLKFREQ_MASK);
|
||||
|
||||
return (DL_GPAMP_CHOPPING_FREQ)(freq);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the chopping mode
|
||||
*
|
||||
* @param[in] mode The chopping mode to set.
|
||||
* One of @ref DL_GPAMP_CHOPPING_MODE
|
||||
*/
|
||||
__STATIC_INLINE void DL_GPAMP_setChoppingMode(DL_GPAMP_CHOPPING_MODE mode)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.PMUOPAMP, (uint32_t) mode,
|
||||
SYSCTL_PMUOPAMP_CHOPCLKMODE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the chopping mode
|
||||
*
|
||||
* @return The current chopping mode
|
||||
*
|
||||
* @retval One of @ref DL_GPAMP_CHOPPING_MODE
|
||||
*/
|
||||
__STATIC_INLINE DL_GPAMP_CHOPPING_MODE DL_GPAMP_getChoppingMode(void)
|
||||
{
|
||||
uint32_t mode =
|
||||
(SYSCTL->SOCLOCK.PMUOPAMP & SYSCTL_PMUOPAMP_CHOPCLKMODE_MASK);
|
||||
|
||||
return (DL_GPAMP_CHOPPING_MODE)(mode);
|
||||
}
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MSPM0_HAS_GPAMP__ */
|
||||
|
||||
#endif /* ti_dl_m0p_dl_gpamp__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (c) 2025, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_gpio.h>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,171 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_i2c.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_I2C__
|
||||
|
||||
/**
|
||||
* @brief I2C Controller APIs
|
||||
*/
|
||||
|
||||
void DL_I2C_setClockConfig(I2C_Regs *i2c, const DL_I2C_ClockConfig *config)
|
||||
{
|
||||
DL_Common_updateReg(&i2c->CLKSEL, (uint32_t) config->clockSel,
|
||||
I2C_CLKSEL_BUSCLK_SEL_MASK | I2C_CLKSEL_MFCLK_SEL_MASK);
|
||||
|
||||
DL_Common_updateReg(
|
||||
&i2c->CLKDIV, (uint32_t) config->divideRatio, I2C_CLKDIV_RATIO_MASK);
|
||||
}
|
||||
|
||||
void DL_I2C_getClockConfig(const I2C_Regs *i2c, DL_I2C_ClockConfig *config)
|
||||
{
|
||||
uint32_t clockSel =
|
||||
i2c->CLKSEL & (I2C_CLKSEL_BUSCLK_SEL_MASK | I2C_CLKSEL_MFCLK_SEL_MASK);
|
||||
config->clockSel = (DL_I2C_CLOCK)(clockSel);
|
||||
|
||||
uint32_t divideRatio = i2c->CLKDIV & I2C_CLKDIV_RATIO_MASK;
|
||||
config->divideRatio = (DL_I2C_CLOCK_DIVIDE)(divideRatio);
|
||||
}
|
||||
|
||||
uint16_t DL_I2C_fillControllerTXFIFO(
|
||||
I2C_Regs *i2c, const uint8_t *buffer, uint16_t count)
|
||||
{
|
||||
uint16_t i;
|
||||
for (i = (uint16_t) 0; i < count; i++) {
|
||||
if (DL_I2C_isControllerTXFIFOFull(i2c) == false) {
|
||||
DL_I2C_transmitControllerData(i2c, buffer[i]);
|
||||
} else { // Controller TX FIFO is full
|
||||
break;
|
||||
}
|
||||
}
|
||||
return i;
|
||||
}
|
||||
|
||||
void DL_I2C_flushControllerTXFIFO(I2C_Regs *i2c)
|
||||
{
|
||||
DL_I2C_startFlushControllerTXFIFO(i2c);
|
||||
while (DL_I2C_isControllerTXFIFOEmpty(i2c) == false) {
|
||||
;
|
||||
}
|
||||
DL_I2C_stopFlushControllerTXFIFO(i2c);
|
||||
}
|
||||
|
||||
void DL_I2C_flushControllerRXFIFO(I2C_Regs *i2c)
|
||||
{
|
||||
DL_I2C_startFlushControllerRXFIFO(i2c);
|
||||
while (DL_I2C_isControllerRXFIFOEmpty(i2c) == false) {
|
||||
;
|
||||
}
|
||||
DL_I2C_stopFlushControllerRXFIFO(i2c);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief I2C Target APIs
|
||||
*/
|
||||
uint8_t DL_I2C_fillTargetTXFIFO(
|
||||
I2C_Regs *i2c, const uint8_t *buffer, uint8_t count)
|
||||
{
|
||||
uint8_t i;
|
||||
for (i = (uint8_t) 0; i < count; i++) {
|
||||
if (DL_I2C_isTargetTXFIFOFull(i2c) == false) {
|
||||
DL_I2C_transmitTargetData(i2c, buffer[i]);
|
||||
} else { // Target TX FIFO is full
|
||||
break;
|
||||
}
|
||||
}
|
||||
return i;
|
||||
}
|
||||
|
||||
void DL_I2C_flushTargetTXFIFO(I2C_Regs *i2c)
|
||||
{
|
||||
DL_I2C_startFlushTargetTXFIFO(i2c);
|
||||
while (DL_I2C_isTargetTXFIFOEmpty(i2c) == false) {
|
||||
;
|
||||
}
|
||||
DL_I2C_stopFlushTargetTXFIFO(i2c);
|
||||
}
|
||||
|
||||
void DL_I2C_flushTargetRXFIFO(I2C_Regs *i2c)
|
||||
{
|
||||
DL_I2C_startFlushTargetRXFIFO(i2c);
|
||||
while (DL_I2C_isTargetRXFIFOEmpty(i2c) == false) {
|
||||
;
|
||||
}
|
||||
DL_I2C_stopFlushTargetRXFIFO(i2c);
|
||||
}
|
||||
|
||||
void DL_I2C_transmitTargetDataBlocking(I2C_Regs *i2c, uint8_t data)
|
||||
{
|
||||
while ((DL_I2C_getTargetStatus(i2c) &
|
||||
DL_I2C_TARGET_STATUS_TRANSMIT_REQUEST) !=
|
||||
DL_I2C_TARGET_STATUS_TRANSMIT_REQUEST) {
|
||||
;
|
||||
}
|
||||
DL_I2C_transmitTargetData(i2c, data);
|
||||
}
|
||||
|
||||
bool DL_I2C_transmitTargetDataCheck(I2C_Regs *i2c, uint8_t data)
|
||||
{
|
||||
bool status;
|
||||
if (DL_I2C_isTargetTXFIFOFull(i2c)) {
|
||||
status = false;
|
||||
} else {
|
||||
DL_I2C_transmitTargetData(i2c, data);
|
||||
status = true;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
uint8_t DL_I2C_receiveTargetDataBlocking(const I2C_Regs *i2c)
|
||||
{
|
||||
while (
|
||||
(DL_I2C_getTargetStatus(i2c) & DL_I2C_TARGET_STATUS_RECEIVE_REQUEST) !=
|
||||
DL_I2C_TARGET_STATUS_RECEIVE_REQUEST) {
|
||||
;
|
||||
}
|
||||
return DL_I2C_receiveTargetData(i2c);
|
||||
}
|
||||
|
||||
bool DL_I2C_receiveTargetDataCheck(const I2C_Regs *i2c, uint8_t *buffer)
|
||||
{
|
||||
bool status;
|
||||
if (DL_I2C_isTargetRXFIFOEmpty(i2c)) {
|
||||
status = false;
|
||||
} else {
|
||||
*buffer = DL_I2C_receiveTargetData(i2c);
|
||||
status = true;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_I2C__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2025, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_comp.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_IWDT__
|
||||
#endif /* __MSPM0_HAS_IWDT__ */
|
||||
@@ -0,0 +1,237 @@
|
||||
/*
|
||||
* Copyright (c) 2023, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_iwdt.h
|
||||
* @brief Independent Watchdog Timer (iWDT) Driver Library
|
||||
* @defgroup iWDT Independent Watchdog Timer (iWDT)
|
||||
*
|
||||
* @anchor ti_dl_dl_iwdt_Overview
|
||||
* # Overview
|
||||
*
|
||||
* The Independent Watchdog Timer Driver Library allows full configuration of
|
||||
* the MSPM0 iWDT module.
|
||||
* The independent window watchdog timer (iWDT) in the LFSS IP is an SoC independent supervisor
|
||||
* which monitors code execution and overall hang up scenarios of the SoC. Due to
|
||||
* the nature of the LFSS IP, this iWDT has its own system independent power and clock source.
|
||||
* If the application software does not successfully reset the watchdog within the programmed time,
|
||||
* the watchdog generates a POR reset to the SoC
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup IWDT
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_dl_iwdt__include
|
||||
#define ti_dl_dl_iwdt__include
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/driverlib/dl_lfss.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_IWDT__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_CLOCK_DIVIDE_1
|
||||
*/
|
||||
#define DL_IWDT_CLOCK_DIVIDE_1 DL_LFSS_IWDT_CLOCK_DIVIDE_1
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_CLOCK_DIVIDE_2
|
||||
*/
|
||||
#define DL_IWDT_CLOCK_DIVIDE_2 DL_LFSS_IWDT_CLOCK_DIVIDE_2
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_CLOCK_DIVIDE_3
|
||||
*/
|
||||
#define DL_IWDT_CLOCK_DIVIDE_3 DL_LFSS_IWDT_CLOCK_DIVIDE_3
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_CLOCK_DIVIDE_4
|
||||
*/
|
||||
#define DL_IWDT_CLOCK_DIVIDE_4 DL_LFSS_IWDT_CLOCK_DIVIDE_4
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_CLOCK_DIVIDE_5
|
||||
*/
|
||||
#define DL_IWDT_CLOCK_DIVIDE_5 DL_LFSS_IWDT_CLOCK_DIVIDE_5
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_CLOCK_DIVIDE_6
|
||||
*/
|
||||
#define DL_IWDT_CLOCK_DIVIDE_6 DL_LFSS_IWDT_CLOCK_DIVIDE_6
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_CLOCK_DIVIDE_7
|
||||
*/
|
||||
#define DL_IWDT_CLOCK_DIVIDE_7 DL_LFSS_IWDT_CLOCK_DIVIDE_7
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_CLOCK_DIVIDE_8
|
||||
*/
|
||||
#define DL_IWDT_CLOCK_DIVIDE_8 DL_LFSS_IWDT_CLOCK_DIVIDE_8
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_TIMER_PERIOD_6_BITS
|
||||
*/
|
||||
#define DL_IWDT_TIMER_PERIOD_6_BITS DL_LFSS_IWDT_TIMER_PERIOD_6_BITS
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_TIMER_PERIOD_8_BITS
|
||||
*/
|
||||
#define DL_IWDT_TIMER_PERIOD_8_BITS DL_LFSS_IWDT_TIMER_PERIOD_8_BITS
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_TIMER_PERIOD_10_BITS
|
||||
*/
|
||||
#define DL_IWDT_TIMER_PERIOD_10_BITS DL_LFSS_IWDT_TIMER_PERIOD_10_BITS
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_TIMER_PERIOD_12_BITS
|
||||
*/
|
||||
#define DL_IWDT_TIMER_PERIOD_12_BITS DL_LFSS_IWDT_TIMER_PERIOD_12_BITS
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_TIMER_PERIOD_15_BITS
|
||||
*/
|
||||
#define DL_IWDT_TIMER_PERIOD_15_BITS DL_LFSS_IWDT_TIMER_PERIOD_15_BITS
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_TIMER_PERIOD_18_BITS
|
||||
*/
|
||||
#define DL_IWDT_TIMER_PERIOD_18_BITS DL_LFSS_IWDT_TIMER_PERIOD_18_BITS
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_TIMER_PERIOD_21_BITS
|
||||
*/
|
||||
#define DL_IWDT_TIMER_PERIOD_21_BITS DL_LFSS_IWDT_TIMER_PERIOD_21_BITS
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_TIMER_PERIOD_25_BITS
|
||||
*/
|
||||
#define DL_IWDT_TIMER_PERIOD_25_BITS DL_LFSS_IWDT_TIMER_PERIOD_25_BITS
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_enableModule
|
||||
*/
|
||||
#define DL_IWDT_enableModule DL_LFSS_IWDT_enableModule
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_disableModule
|
||||
*/
|
||||
#define DL_IWDT_disableModule DL_LFSS_IWDT_disableModule
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_isModuleEnabled
|
||||
*/
|
||||
#define DL_IWDT_isModuleEnabled DL_LFSS_IWDT_isModuleEnabled
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_enableFreeRun
|
||||
*/
|
||||
#define DL_IWDT_enableFreeRun DL_LFSS_IWDT_enableFreeRun
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_disableFreeRun
|
||||
*/
|
||||
#define DL_IWDT_disableFreeRun DL_LFSS_IWDT_disableFreeRun
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_isFreeRunEnabled
|
||||
*/
|
||||
#define DL_IWDT_isFreeRunEnabled DL_LFSS_IWDT_isFreeRunEnabled
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_setClockDivider
|
||||
*/
|
||||
#define DL_IWDT_setClockDivider DL_LFSS_IWDT_setClockDivider
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_getClockDivider
|
||||
*/
|
||||
#define DL_IWDT_getClockDivider DL_LFSS_IWDT_getClockDivider
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_setTimerPeriod
|
||||
*/
|
||||
#define DL_IWDT_setTimerPeriod DL_LFSS_IWDT_setTimerPeriod
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_getTimerPeriod
|
||||
*/
|
||||
#define DL_IWDT_getTimerPeriod DL_LFSS_IWDT_getTimerPeriod
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_restart
|
||||
*/
|
||||
#define DL_IWDT_restart DL_LFSS_IWDT_restart
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_isWatchdogRunning
|
||||
*/
|
||||
#define DL_IWDT_isWatchDogRunning DL_LFSS_IWDT_isWatchdogRunning
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_enableWriteProtect
|
||||
*/
|
||||
#define DL_IWDT_enableWriteProtect DL_LFSS_IWDT_enableWriteProtect
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_isWriteProtectEnabled
|
||||
*/
|
||||
#define DL_IWDT_isWriteProtectEnabled DL_LFSS_IWDT_isWriteProtectEnabled
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_IWDT_disableWriteProtect
|
||||
*/
|
||||
#define DL_IWDT_disableWriteProtect DL_LFSS_IWDT_disableWriteProtect
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MSPM0_HAS_IWDT__ */
|
||||
|
||||
#endif /* ti_dl_dl_iwdt__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,164 @@
|
||||
/*
|
||||
* Copyright (c) 2023, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_keystorectl.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_KEYSTORE_CTL__
|
||||
|
||||
static void DL_KEYSTORECTL_loadData(
|
||||
volatile uint32_t *pDest, uint32_t *pSrc, uint8_t len);
|
||||
static uint8_t DL_KEYSTORECTL_getWordsFromSize(
|
||||
DL_KEYSTORECTL_KEY_SIZE keySize);
|
||||
|
||||
void DL_KEYSTORECTL_loadKey(KEYSTORECTL_Regs *keystorectl, uint32_t *key)
|
||||
{
|
||||
DL_KEYSTORECTL_KEY_SIZE keySize;
|
||||
uint8_t numWords;
|
||||
volatile uint32_t *destPtr = (volatile uint32_t *) &keystorectl->KEYIN;
|
||||
uint32_t *srcPtr = (uint32_t *) key;
|
||||
|
||||
keySize = DL_KEYSTORECTL_getDestinationKeySize(keystorectl);
|
||||
numWords = DL_KEYSTORECTL_getWordsFromSize(keySize);
|
||||
|
||||
DL_KEYSTORECTL_loadData(destPtr, srcPtr, numWords);
|
||||
}
|
||||
|
||||
DL_KEYSTORECTL_STATUS DL_KEYSTORECTL_writeKey(
|
||||
KEYSTORECTL_Regs *keystorectl, DL_KEYSTORECTL_KeyWrConfig *keyWrConfig)
|
||||
{
|
||||
DL_KEYSTORECTL_STATUS status = DL_KEYSTORECTL_STATUS_VALID;
|
||||
uint32_t validSlot;
|
||||
uint32_t slotNum;
|
||||
uint8_t numWords;
|
||||
volatile uint32_t *destPtr = (volatile uint32_t *) &keystorectl->KEYIN;
|
||||
|
||||
/* 1. Configure the key write by writing size and slot */
|
||||
|
||||
DL_Common_updateReg(&keystorectl->KEYWR,
|
||||
(((uint32_t) keyWrConfig->keySize) |
|
||||
((uint32_t) keyWrConfig->keySlot)),
|
||||
(KEYSTORECTL_KEYWR_KEYSZSEL_MASK | KEYSTORECTL_KEYWR_KEYSLOTSEL_MASK));
|
||||
|
||||
/* 2. Confirm a valid write configuration (pre-existing condition may)
|
||||
* not have been valid so we only check after writing the intended
|
||||
* config
|
||||
*/
|
||||
status = DL_KEYSTORECTL_getStatus(keystorectl);
|
||||
|
||||
/* 3. Write key to the input buffer*/
|
||||
if (status == DL_KEYSTORECTL_STATUS_VALID) {
|
||||
numWords = DL_KEYSTORECTL_getWordsFromSize(keyWrConfig->keySize);
|
||||
|
||||
DL_KEYSTORECTL_loadData(destPtr, keyWrConfig->key, numWords);
|
||||
|
||||
/* 4. Loop until status is back to valid (no longer busy) */
|
||||
status = DL_KEYSTORECTL_getStatus(keystorectl);
|
||||
while (status == DL_KEYSTORECTL_STATUS_BUSY_RX) {
|
||||
status = DL_KEYSTORECTL_getStatus(keystorectl);
|
||||
}
|
||||
}
|
||||
|
||||
/* 5. Confirm key slots were successfully written */
|
||||
slotNum = (keyWrConfig->keySlot >> KEYSTORECTL_KEYWR_KEYSLOTSEL_OFS);
|
||||
validSlot = (1 << (slotNum + KEYSTORECTL_STATUS_VALID_OFS));
|
||||
if (status == DL_KEYSTORECTL_STATUS_VALID) {
|
||||
validSlot = (validSlot & DL_KEYSTORECTL_getValidKeySlots(keystorectl));
|
||||
if (validSlot == 0) {
|
||||
status = DL_KEYSTORECTL_STATUS_WRITE_FAILED;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
DL_KEYSTORECTL_STATUS DL_KEYSTORECTL_transferKey(
|
||||
KEYSTORECTL_Regs *keystorectl, const DL_KEYSTORECTL_Config *config)
|
||||
{
|
||||
DL_KEYSTORECTL_STATUS status = DL_KEYSTORECTL_STATUS_VALID;
|
||||
|
||||
/* 1. Confirm valid status on the KEYSTORECTL */
|
||||
status = DL_KEYSTORECTL_getStatus(keystorectl);
|
||||
|
||||
/* 2. Configure the read transfer by writing size, slot, and recipient */
|
||||
if (status == DL_KEYSTORECTL_STATUS_VALID) {
|
||||
DL_Common_updateReg(&keystorectl->KEYRD,
|
||||
(((uint32_t) config->keySize) | ((uint32_t) config->cryptoSel) |
|
||||
((uint32_t) config->keySlot)),
|
||||
(KEYSTORECTL_KEYRD_KEYSZSEL_MASK |
|
||||
KEYSTORECTL_KEYRD_CRYPTOSEL_MASK |
|
||||
KEYSTORECTL_KEYRD_KEYSLOTSEL_MASK));
|
||||
|
||||
/* 3. Confirm a valid status and transfer configuration */
|
||||
status = DL_KEYSTORECTL_getStatus(keystorectl);
|
||||
|
||||
/* 4. Loop until status is back to valid */
|
||||
while (status == DL_KEYSTORECTL_STATUS_BUSY_TX) {
|
||||
status = DL_KEYSTORECTL_getStatus(keystorectl);
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static void DL_KEYSTORECTL_loadData(
|
||||
volatile uint32_t *pDest, uint32_t *pSrc, uint8_t len)
|
||||
{
|
||||
uint8_t i;
|
||||
uint32_t *pTemp;
|
||||
|
||||
pTemp = pSrc;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
*pDest = *pTemp++;
|
||||
}
|
||||
}
|
||||
|
||||
static uint8_t DL_KEYSTORECTL_getWordsFromSize(DL_KEYSTORECTL_KEY_SIZE keySize)
|
||||
{
|
||||
uint8_t numWords;
|
||||
|
||||
switch (keySize) {
|
||||
case DL_KEYSTORECTL_KEY_SIZE_128_BITS:
|
||||
numWords = 4;
|
||||
break;
|
||||
case DL_KEYSTORECTL_KEY_SIZE_256_BITS:
|
||||
numWords = 8;
|
||||
break;
|
||||
default:
|
||||
numWords = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return numWords;
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_KEYSTORE_CTL__ */
|
||||
@@ -0,0 +1,563 @@
|
||||
/*
|
||||
* Copyright (c) 2023, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_keystorectl.h
|
||||
* @brief KEYSTORECTL (Keystore Controller) Driver Library
|
||||
* @defgroup KEYSTORECTL Keystore Controller (KEYSTORECTL)
|
||||
*
|
||||
* @anchor ti_dl_dl_keystorectl_Overview
|
||||
* # Overview
|
||||
*
|
||||
* The Keystore Controller (KEYSTORECTL) DriverLib allows full configuration
|
||||
* of the MSPM0 KEYSTORECTL Module.
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************/
|
||||
/** @addtogroup KEYSTORECTL
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_dl_keystorectl__include
|
||||
#define ti_dl_dl_keystorectl__include
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
#include <ti/driverlib/dl_common.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_KEYSTORE_CTL__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/** @addtogroup DL_KEYSTORECTL_KEY_SLOT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @brief Keystore Controller Key Slot 0 */
|
||||
#define DL_KEYSTORECTL_KEY_SLOT_0 (KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT0)
|
||||
|
||||
/*! @brief Keystore Controller Key Slot 1 */
|
||||
#define DL_KEYSTORECTL_KEY_SLOT_1 (KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT1)
|
||||
|
||||
/*! @brief Keystore Controller Key Slot 2 */
|
||||
#define DL_KEYSTORECTL_KEY_SLOT_2 (KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT2)
|
||||
|
||||
/*! @brief Keystore Controller Key Slot 3 */
|
||||
#define DL_KEYSTORECTL_KEY_SLOT_3 (KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT3)
|
||||
|
||||
/*! @brief Keystore Controller Key Slot 4 */
|
||||
#define DL_KEYSTORECTL_KEY_SLOT_4 (KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT4)
|
||||
|
||||
/*! @brief Keystore Controller Key Slot 5 */
|
||||
#define DL_KEYSTORECTL_KEY_SLOT_5 (KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT5)
|
||||
|
||||
/*! @brief Keystore Controller Key Slot 6 */
|
||||
#define DL_KEYSTORECTL_KEY_SLOT_6 (KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT6)
|
||||
|
||||
/*! @brief Keystore Controller Key Slot 7 */
|
||||
#define DL_KEYSTORECTL_KEY_SLOT_7 (KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT7)
|
||||
|
||||
|
||||
/*! @brief Keystore Controller Key Combined Slot 0 and 1 */
|
||||
#define DL_KEYSTORECTL_KEY_SLOT_0_AND_1 ((KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT0) | \
|
||||
(KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT1))
|
||||
|
||||
/*! @brief Keystore Controller Key Combined Slot 2 and 3 */
|
||||
#define DL_KEYSTORECTL_KEY_SLOT_2_AND_3 ((KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT2) | \
|
||||
(KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT3))
|
||||
|
||||
/*! @brief Keystore Controller Key Combined Slot 4 and 5 */
|
||||
#define DL_KEYSTORECTL_KEY_SLOT_4_AND_5 ((KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT4) | \
|
||||
(KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT5))
|
||||
|
||||
/*! @brief Keystore Controller Key Combined Slot 6 and 7 */
|
||||
#define DL_KEYSTORECTL_KEY_SLOT_6_AND_7 ((KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT6) | \
|
||||
(KEYSTORECTL_KEYWR_KEYSLOTSEL_SLOT7))
|
||||
|
||||
/** @}*/
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
/*! @enum DL_KEYSTORECTL_NUM_256_KEYS */
|
||||
typedef enum {
|
||||
/*! No 256-bit keys */
|
||||
DL_KEYSTORECTL_NUM_256_KEYS_ZERO = KEYSTORECTL_CFG_NK256_ZERO,
|
||||
/*! One 256-bit keys */
|
||||
DL_KEYSTORECTL_NUM_256_KEYS_ONE = KEYSTORECTL_CFG_NK256_ONE,
|
||||
/*! Two 256-bit keys */
|
||||
DL_KEYSTORECTL_NUM_256_KEYS_TWO = KEYSTORECTL_CFG_NK256_TWO,
|
||||
/*! Three 256-bit keys */
|
||||
DL_KEYSTORECTL_NUM_256_KEYS_THREE = KEYSTORECTL_CFG_NK256_THREE,
|
||||
/*! Four 256-bit keys */
|
||||
DL_KEYSTORECTL_NUM_256_KEYS_FOUR = KEYSTORECTL_CFG_NK256_FOUR,
|
||||
} DL_KEYSTORECTL_NUM_256_KEYS;
|
||||
|
||||
/*! @enum DL_KEYSTORECTL_KEY_SIZE */
|
||||
typedef enum {
|
||||
/*! Key size set to 128 */
|
||||
DL_KEYSTORECTL_KEY_SIZE_128_BITS = KEYSTORECTL_KEYWR_KEYSZSEL_K128,
|
||||
/*! Key size set to 256 */
|
||||
DL_KEYSTORECTL_KEY_SIZE_256_BITS = KEYSTORECTL_KEYWR_KEYSZSEL_K256,
|
||||
} DL_KEYSTORECTL_KEY_SIZE;
|
||||
|
||||
/*! @enum DL_KEYSTORECTL_NUM_SLOTS */
|
||||
typedef enum {
|
||||
/*! Two 128-bit key slots present on device */
|
||||
DL_KEYSTORECTL_NUM_SLOTS_TWO = KEYSTORECTL_STATUS_NKEYSLOTS_TWO,
|
||||
/*! Three 128-bit key slots present on device */
|
||||
DL_KEYSTORECTL_NUM_SLOTS_THREE = KEYSTORECTL_STATUS_NKEYSLOTS_THREE,
|
||||
/*! Four 128-bit key slots present on device */
|
||||
DL_KEYSTORECTL_NUM_SLOTS_FOUR = KEYSTORECTL_STATUS_NKEYSLOTS_FOUR,
|
||||
} DL_KEYSTORECTL_NUM_SLOTS;
|
||||
|
||||
/*! @enum DL_KEYSTORECTL_CRYPTO_SEL */
|
||||
typedef enum {
|
||||
/*! Transfer the key from keystore KEYSTORECTL to the AES engine */
|
||||
DL_KEYSTORECTL_CRYPTO_SEL_AES = KEYSTORECTL_KEYRD_CRYPTOSEL_AES,
|
||||
} DL_KEYSTORECTL_CRYPTO_SEL;
|
||||
|
||||
/*! @enum DL_KEYSTORECTL_STATUS */
|
||||
typedef enum {
|
||||
/*! Valid status bit. Configuration is valid or operation completed. */
|
||||
DL_KEYSTORECTL_STATUS_VALID = KEYSTORECTL_STATUS_STAT_VALID,
|
||||
/*! No Configuration Status bit, no number of 256 keys has been identified.
|
||||
* The user must call @ref DL_KEYSTORECTL_setNumberOf256Keys. */
|
||||
DL_KEYSTORECTL_STATUS_NO_CONFIG = KEYSTORECTL_STATUS_STAT_NO_CFG,
|
||||
/*! Invalid number set during @ref DL_KEYSTORECTL_setNumberOf256Keys */
|
||||
DL_KEYSTORECTL_STATUS_INVALID_NUM_KEYS =
|
||||
KEYSTORECTL_STATUS_STAT_INVALID_NK256,
|
||||
/*! Busy RX status bit. The engine is busy receiving a key deposit. */
|
||||
DL_KEYSTORECTL_STATUS_BUSY_RX = KEYSTORECTL_STATUS_STAT_BUSY_RECEIVE,
|
||||
/*! Busy TX status bit. The engine is busy transmitting a key to a crypto engine */
|
||||
DL_KEYSTORECTL_STATUS_BUSY_TX = KEYSTORECTL_STATUS_STAT_BUSY_TRANSMIT,
|
||||
/*! Invalid key write configuration. This means one or more of the
|
||||
* following: the selected slot exceeds available slots, the selected slot
|
||||
* already contains a valid programmed key, the selected slot has a
|
||||
* mismatched key size compared to the KEYSTORECTL configuration. */
|
||||
DL_KEYSTORECTL_STATUS_INVALID_SLOT_WR =
|
||||
KEYSTORECTL_STATUS_STAT_INVALID_KEYSLOTSELW,
|
||||
/*! Invalid key read configuration (transmitting a key). This means one or
|
||||
* more of the following: the selected slot exceeds available slots, the
|
||||
* selected slot does not contain a valid programmed key, the selected slot
|
||||
* has a mismatched key size */
|
||||
DL_KEYSTORECTL_STATUS_INVALID_SLOT_RD =
|
||||
KEYSTORECTL_STATUS_STAT_INVALID_KEYSLOTSELR,
|
||||
/*! Key slots are not valid after a write. Write failed during the
|
||||
@ref DL_KEYSTORECTL_writeKey (driver library specific). */
|
||||
DL_KEYSTORECTL_STATUS_WRITE_FAILED = 0x0BAD,
|
||||
} DL_KEYSTORECTL_STATUS;
|
||||
|
||||
/*!
|
||||
* @brief Configuration struct for @ref DL_KEYSTORECTL_writeKey
|
||||
*/
|
||||
typedef struct {
|
||||
/*! The key slot (or slots in the case of 256-bit keys) to be written.
|
||||
* One of @ref DL_KEYSTORECTL_KEY_SLOT */
|
||||
uint32_t keySlot;
|
||||
/*! The size of the key (128-bit or 256-bit).
|
||||
* One of @ref DL_KEYSTORECTL_KEY_SIZE */
|
||||
DL_KEYSTORECTL_KEY_SIZE keySize;
|
||||
/*! uint32_t pointer to the current key in memory */
|
||||
uint32_t *key;
|
||||
} DL_KEYSTORECTL_KeyWrConfig;
|
||||
|
||||
/*!
|
||||
* @brief Configuration struct for @ref DL_KEYSTORECTL_transferKey
|
||||
*/
|
||||
typedef struct {
|
||||
/*! The key slot (or slots in the case of 256-bit keys) to be transferred.
|
||||
* One of @ref DL_KEYSTORECTL_KEY_SLOT */
|
||||
uint32_t keySlot;
|
||||
/*! The size of the key (128-bit or 256-bit).
|
||||
* One of @ref DL_KEYSTORECTL_KEY_SIZE */
|
||||
DL_KEYSTORECTL_KEY_SIZE keySize;
|
||||
/*! The intended crypto recipient. One of @ref DL_KEYSTORECTL_CRYPTO_SEL */
|
||||
DL_KEYSTORECTL_CRYPTO_SEL cryptoSel;
|
||||
} DL_KEYSTORECTL_Config;
|
||||
|
||||
/**
|
||||
* @brief Sets the number of combined 256 key slots
|
||||
*
|
||||
* For a given number of 128-bit key slots n, there can be up to n/2 slots
|
||||
* combined to work as one 256-bit key slot. These larger slots are added to
|
||||
* earlier slots first. Thus, a 4-slot device with one 256-key slot will have
|
||||
* slots 0 and 1 combined, and slot 2 and 3 will remain 128-bit key slots.
|
||||
* Refer to the device datasheet for the specific number of key slots.
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
* @param[in] numKeys Number of 256-bit keys, one of
|
||||
* @ref DL_KEYSTORECTL_NUM_256_KEYS. Must be less than
|
||||
* the total key slots on the device divided by two
|
||||
*
|
||||
* @note this function can only be written in a secure operating state before
|
||||
* the INITDONE signal is asserted.
|
||||
*/
|
||||
__STATIC_INLINE void DL_KEYSTORECTL_setNumberOf256Keys(
|
||||
KEYSTORECTL_Regs *keystorectl, DL_KEYSTORECTL_NUM_256_KEYS numKeys)
|
||||
{
|
||||
DL_Common_updateReg(
|
||||
&keystorectl->CFG, (uint32_t) numKeys, KEYSTORECTL_CFG_NK256_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the current number of combined 256 key slots
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return number of 256-bit keys. One of @ref DL_KEYSTORECTL_NUM_256_KEYS
|
||||
*
|
||||
* @sa DL_KEYSTORECTL_setNumberOf256Keys
|
||||
*/
|
||||
__STATIC_INLINE DL_KEYSTORECTL_NUM_256_KEYS DL_KEYSTORECTL_getNumberOf256Keys(
|
||||
const KEYSTORECTL_Regs *keystorectl)
|
||||
{
|
||||
uint32_t numKeys = (keystorectl->CFG & KEYSTORECTL_CFG_NK256_MASK);
|
||||
|
||||
return (DL_KEYSTORECTL_NUM_256_KEYS)(numKeys);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the intended destination key slot for the next write
|
||||
*
|
||||
* Sets the destination key slot for a data write to that region. In the case
|
||||
* of 128-bit key slot, only one slot should be selected. In the case of a 256-
|
||||
* bit key slot, both registers should be selected and the key size should also
|
||||
* reflect this change. If 256- it keys are desired, they should be configured
|
||||
* using @ref DL_KEYSTORECTL_NUM_256_KEYS.
|
||||
* Refer to the device datasheet for the specific number of key slots.
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
* @param[in] keySlot The intended key slot. Can be 128-bit or a 256-bit.
|
||||
* One of @ref DL_KEYSTORECTL_KEY_SLOT
|
||||
*
|
||||
* @note this function can only be written in a secure operating state before
|
||||
* the INITDONE signal is asserted.
|
||||
*
|
||||
* @sa DL_KEYSTORECTL_setNumberOf256Keys
|
||||
* @sa DL_KEYSTORECTL_setDestinationKeySize
|
||||
*/
|
||||
__STATIC_INLINE void DL_KEYSTORECTL_setDestinationKeySlot(
|
||||
KEYSTORECTL_Regs *keystorectl, uint32_t keySlot)
|
||||
{
|
||||
DL_Common_updateReg(
|
||||
&keystorectl->KEYWR, keySlot, KEYSTORECTL_KEYWR_KEYSLOTSEL_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the intended destination key slot for the next write
|
||||
*
|
||||
* Refer to the device datasheet for the specific number of key slots.
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @returns The intended key slot. Can be 128-bit or a 256-bit. One of
|
||||
* @ref DL_KEYSTORECTL_KEY_SLOT
|
||||
*
|
||||
* @note this function can only be read in a secure operating state before
|
||||
* the INITDONE signal is asserted.
|
||||
*
|
||||
* @sa DL_KEYSTORECTL_setDestinationKeySlot
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_KEYSTORECTL_getDestinationKeySlot(
|
||||
const KEYSTORECTL_Regs *keystorectl)
|
||||
{
|
||||
return (keystorectl->KEYWR & KEYSTORECTL_KEYWR_KEYSLOTSEL_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the intended destination key slot size for next write
|
||||
*
|
||||
* Sets the destination key slot size for a data write to that region. If 256-
|
||||
* bit keys are desired, they should be configured using
|
||||
* @ref DL_KEYSTORECTL_NUM_256_KEYS.
|
||||
* Refer to the device datasheet for the specific number of key slots.
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
* @param[in] keySize The intended key size. One of
|
||||
* @ref DL_KEYSTORECTL_KEY_SIZE
|
||||
*
|
||||
* @note this function can only be written in a secure operating state before
|
||||
* the INITDONE signal is asserted.
|
||||
*
|
||||
* @sa DL_KEYSTORECTL_setNumberOf256Keys
|
||||
* @sa DL_KEYSTORECTL_setDestinationKeySlot
|
||||
*/
|
||||
__STATIC_INLINE void DL_KEYSTORECTL_setDestinationKeySize(
|
||||
KEYSTORECTL_Regs *keystorectl, DL_KEYSTORECTL_KEY_SIZE keySize)
|
||||
{
|
||||
DL_Common_updateReg(&keystorectl->KEYWR, (uint32_t) keySize,
|
||||
KEYSTORECTL_KEYWR_KEYSZSEL_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the intended destination key size for the next write
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @returns The intended key size. One of @ref DL_KEYSTORECTL_KEY_SIZE
|
||||
*
|
||||
* @note this function can only be read in a secure operating state before
|
||||
* the INITDONE signal is asserted.
|
||||
*
|
||||
* @sa DL_KEYSTORECTL_setDestinationKeySize
|
||||
*/
|
||||
__STATIC_INLINE DL_KEYSTORECTL_KEY_SIZE DL_KEYSTORECTL_getDestinationKeySize(
|
||||
const KEYSTORECTL_Regs *keystorectl)
|
||||
{
|
||||
uint32_t keySize = (keystorectl->KEYWR & KEYSTORECTL_KEYWR_KEYSZSEL_MASK);
|
||||
|
||||
return (DL_KEYSTORECTL_KEY_SIZE)(keySize);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the intended destination key slot size for next write
|
||||
*
|
||||
* Loads a key of the provided size into the KEYSTORECTL provided there is a
|
||||
* valid bit set. The specific intended slot and size should already be set by
|
||||
* the user before using this.
|
||||
* Refer to the device datasheet for the specific number of key slots.
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
* @param[in] key Pointer to an uint32_t array containing the key.
|
||||
*
|
||||
* @note this function can only be written in a secure operating state before
|
||||
* the INITDONE signal is asserted.
|
||||
*
|
||||
* @sa DL_KEYSTORECTL_setDestinationKeySlot
|
||||
* @sa DL_KEYSTORECTL_setDestinationKeySize
|
||||
*/
|
||||
void DL_KEYSTORECTL_loadKey(KEYSTORECTL_Regs *keystorectl, uint32_t *key);
|
||||
|
||||
/**
|
||||
* @brief Gets the intended source key slot for the next transfer
|
||||
*
|
||||
* Sets the source key slot for a data transfer to another crypto peripheral.
|
||||
* In the case of 128-bit key slot, only one slot should be selected. In the
|
||||
* case of a 256-bit key slot, both registers should be selected and the key
|
||||
* size should also reflect this change. If 256- it keys are desired, they
|
||||
* can be accessed using @ref DL_KEYSTORECTL_getNumberOf256Keys.
|
||||
* Refer to the device datasheet for the specific number of key slots.
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
* @param[in] keySlot The intended key slot. Can be 128-bit or a 256-bit.
|
||||
* One of @ref DL_KEYSTORECTL_KEY_SLOT
|
||||
*
|
||||
* @sa DL_KEYSTORECTL_getNumOf256Keys
|
||||
* @sa DL_KEYSTORECTL_setSourceKeySize
|
||||
*/
|
||||
__STATIC_INLINE void DL_KEYSTORECTL_setSourceKeySlot(
|
||||
KEYSTORECTL_Regs *keystorectl, uint32_t keySlot)
|
||||
{
|
||||
DL_Common_updateReg(
|
||||
&keystorectl->KEYRD, keySlot, KEYSTORECTL_KEYRD_KEYSLOTSEL_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the intended source key slot for the next transfer
|
||||
*
|
||||
* Refer to the device datasheet for the specific number of key slots.
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @returns The intended key slot. Can be 128-bit or a 256-bit. One of
|
||||
* @ref DL_KEYSTORECTL_KEY_SLOT
|
||||
*
|
||||
* @sa DL_KEYSTORECTL_setSourceKeySlot
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_KEYSTORECTL_getSourceKeySlot(
|
||||
const KEYSTORECTL_Regs *keystorectl)
|
||||
{
|
||||
return (keystorectl->KEYRD & KEYSTORECTL_KEYRD_KEYSLOTSEL_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the intended source key slot size for next transfer
|
||||
*
|
||||
* Sets the source key slot size for a data transfer to that region. If 256-
|
||||
* bit keys are desired, they should be configured using
|
||||
* @ref DL_KEYSTORECTL_NUM_256_KEYS.
|
||||
* Refer to the device datasheet for the specific number of key slots.
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
* @param[in] keySize The intended key size. One of
|
||||
* @ref DL_KEYSTORECTL_KEY_SIZE
|
||||
*
|
||||
* @sa DL_KEYSTORECTL_setNumberOf256Keys
|
||||
* @sa DL_KEYSTORECTL_setSourceKeySlot
|
||||
*/
|
||||
__STATIC_INLINE void DL_KEYSTORECTL_setSourceKeySize(
|
||||
KEYSTORECTL_Regs *keystorectl, DL_KEYSTORECTL_KEY_SIZE keySize)
|
||||
{
|
||||
DL_Common_updateReg(&keystorectl->KEYRD, (uint32_t) keySize,
|
||||
KEYSTORECTL_KEYRD_KEYSZSEL_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the intended source key size for the next transfer
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @returns The intended key size. One of @ref DL_KEYSTORECTL_KEY_SIZE
|
||||
*
|
||||
* @sa DL_KEYSTORECTL_setSourceKeySize
|
||||
*/
|
||||
__STATIC_INLINE DL_KEYSTORECTL_KEY_SIZE DL_KEYSTORECTL_getSourceKeySize(
|
||||
const KEYSTORECTL_Regs *keystorectl)
|
||||
{
|
||||
uint32_t keySize = (keystorectl->KEYRD & KEYSTORECTL_KEYRD_KEYSZSEL_MASK);
|
||||
|
||||
return (DL_KEYSTORECTL_KEY_SIZE)(keySize);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the current status of the KEYSTORECTL module
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The status of the keystorectl. One of @ref DL_KEYSTORECTL_STATUS
|
||||
*/
|
||||
__STATIC_INLINE DL_KEYSTORECTL_STATUS DL_KEYSTORECTL_getStatus(
|
||||
const KEYSTORECTL_Regs *keystorectl)
|
||||
{
|
||||
uint32_t status = (keystorectl->STATUS & KEYSTORECTL_STATUS_STAT_MASK);
|
||||
|
||||
return (DL_KEYSTORECTL_STATUS)(status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets currently written key slots
|
||||
*
|
||||
* To understand the key slot configuration, consider the configuration of the
|
||||
* keys including the number of 256-bit keys, and the number of available key
|
||||
* slots
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return Bitwise OR of all valid slots, corresponding to
|
||||
* @ref DL_KEYSTORECTL_KEY_SLOT values.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_KEYSTORECTL_getValidKeySlots(
|
||||
const KEYSTORECTL_Regs *keystorectl)
|
||||
{
|
||||
return (keystorectl->STATUS & KEYSTORECTL_STATUS_VALID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the total number of 128-bit key slots in HW on the device
|
||||
*
|
||||
* This is the number of key slots that the KEYSTORECTL module has in HW on the
|
||||
* device. It does not reflect the configuration or the number of 256-bit keys,
|
||||
* only the total number of slots. This also governs the valid configurations,
|
||||
* and the number of 256-bit keys must be less than or equal to half the value.
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The number of 128-bit slots on the device. One of
|
||||
* @ref DL_KEYSTORECTL_NUM_SLOTS
|
||||
*/
|
||||
__STATIC_INLINE DL_KEYSTORECTL_NUM_SLOTS DL_KEYSTORECTL_getNumSlots(
|
||||
const KEYSTORECTL_Regs *keystorectl)
|
||||
{
|
||||
uint32_t numSlots =
|
||||
(keystorectl->STATUS & KEYSTORECTL_STATUS_NKEYSLOTS_MASK);
|
||||
|
||||
return (DL_KEYSTORECTL_NUM_SLOTS)(numSlots);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes a key into the KEYSTORE
|
||||
*
|
||||
* The sequence this function will follow:
|
||||
*
|
||||
* 1. Confirm valid status on the KEYSTORECTL
|
||||
* 2. Configure the key write by writing size and slot to the key that is to be
|
||||
* written. Passed in via @ref DL_KEYSTORECTL_KeyWrConfig
|
||||
* 3. Confirm a valid write configuration
|
||||
* 4. Write key to the input buffer
|
||||
* 5. Loop until status is back to valid
|
||||
* 6. Confirm key slots are successfully written
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @param[in] keyWrConfig Pointer to the write key configuration struct
|
||||
* @ref DL_KEYSTORECTL_KeyWrConfig
|
||||
*
|
||||
* @return Status of the operation of type @ref DL_KEYSTORECTL_STATUS. Type
|
||||
* will be DL_KEYSTORECTL_STATUS_VALID if successful, or return the
|
||||
* error status.
|
||||
*
|
||||
* @note The function @ref DL_KEYSTORECTL_setNumberOf256Keys must be run
|
||||
* before this can be executed.
|
||||
* @note It is not possible to overwrite a previously configured key. A full
|
||||
* BOOTRST must be executed before the KEYSTORECTL is erased and can be
|
||||
* re-initialized and written.
|
||||
* @note this function can only be written in a secure operating state before
|
||||
* the INITDONE signal is asserted.
|
||||
*/
|
||||
DL_KEYSTORECTL_STATUS DL_KEYSTORECTL_writeKey(
|
||||
KEYSTORECTL_Regs *keystorectl, DL_KEYSTORECTL_KeyWrConfig *keyWrConfig);
|
||||
|
||||
/**
|
||||
* @brief Transfers key loaded in KEYSTORE into intended crypto
|
||||
*
|
||||
* Combination of previous functions in order to give the entire operation.
|
||||
* Expected runtime sequence:
|
||||
*
|
||||
* 1. Confirm valid status on the KEYSTORECTL
|
||||
* 2. Configure the read transfer by writing size, slot, and recipient
|
||||
* This is passed in via the struct @ref DL_KEYSTORECTL_Config
|
||||
* 3. Confirm a valid status and transfer configuration of the KEYSTORECTL
|
||||
* 4. Loop until status is back to valid
|
||||
*
|
||||
* @param[in] keystorectl Pointer to the register overlay for the peripheral
|
||||
* @param[in] config Pointer to a filled out config struct of type
|
||||
* @ref DL_KEYSTORECTL_Config
|
||||
*
|
||||
* @return Status of the operation of type @ref DL_KEYSTORECTL_STATUS. Type
|
||||
* will be DL_KEYSTORECTL_STATUS_VALID if successful, or return the
|
||||
* error status.
|
||||
*/
|
||||
DL_KEYSTORECTL_STATUS DL_KEYSTORECTL_transferKey(
|
||||
KEYSTORECTL_Regs *keystorectl, const DL_KEYSTORECTL_Config *config);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MSPM0_HAS_KEYSTORE_CTL__ */
|
||||
|
||||
#endif /* ti_dl_dl_KEYSTORECTL__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,172 @@
|
||||
/*
|
||||
* Copyright (c) 2023, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include <ti/driverlib/dl_lcd.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_LCD__
|
||||
|
||||
/**
|
||||
* @brief LCD APIs
|
||||
*/
|
||||
|
||||
void DL_LCD_init(LCD_Regs *lcd, const DL_LCD_Config *config)
|
||||
{
|
||||
DL_Common_updateReg(&lcd->LCDCTL0,
|
||||
(uint32_t) config->frequencyDivider | (uint32_t) config->muxRate |
|
||||
(uint32_t) config->lowPowerWaveform,
|
||||
LCD_LCDCTL0_LCDDIVX_MASK | LCD_LCDCTL0_LCDMXX_MASK |
|
||||
LCD_LCDCTL0_LCDLP_MASK);
|
||||
}
|
||||
|
||||
void DL_LCD_setPinAsLCDFunction(LCD_Regs *lcd, uint32_t pin)
|
||||
{
|
||||
lcd->LCDCTL0 &= ~(LCD_LCDCTL0_LCDON_MASK); /* turn off LCD module */
|
||||
|
||||
uint8_t idx = pin >> 4; /* get index in corresponding port control reg */
|
||||
uint16_t val = 1 << (pin & 0x0F); /* get mask to set that specific bit */
|
||||
|
||||
switch (idx) {
|
||||
case 0:
|
||||
lcd->LCDPCTL0 |= val;
|
||||
break;
|
||||
case 1:
|
||||
lcd->LCDPCTL1 |= val;
|
||||
break;
|
||||
case 2:
|
||||
lcd->LCDPCTL2 |= val;
|
||||
break;
|
||||
case 3:
|
||||
lcd->LCDPCTL3 |= val;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_LCD_setPinAsPortFunction(LCD_Regs *lcd, uint8_t pin)
|
||||
{
|
||||
lcd->LCDCTL0 &= ~(LCD_LCDCTL0_LCDON_MASK); /* turn off LCD module */
|
||||
|
||||
uint8_t idx = pin >> 4; /* get index in corresponding port control reg */
|
||||
uint16_t val = 1 << (pin & 0x0F); /* get mask to set that specific bit */
|
||||
|
||||
switch (idx) {
|
||||
case 0:
|
||||
lcd->LCDPCTL0 &= ~(val);
|
||||
break;
|
||||
case 1:
|
||||
lcd->LCDPCTL1 &= ~(val);
|
||||
break;
|
||||
case 2:
|
||||
lcd->LCDPCTL2 &= ~(val);
|
||||
break;
|
||||
case 3:
|
||||
lcd->LCDPCTL3 &= ~(val);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_LCD_setPinAsCommon(LCD_Regs *lcd, uint8_t pin, uint32_t com)
|
||||
{
|
||||
lcd->LCDCTL0 &= ~(LCD_LCDCTL0_LCDON_MASK);
|
||||
|
||||
/* If pin value is > 64, then exit function*/
|
||||
if (pin > 64) {
|
||||
return;
|
||||
}
|
||||
|
||||
uint8_t idx = pin >> 4; /* 0-15 -> 0, 16-31 -> 1, etc. */
|
||||
uint16_t val = 1 << (pin & 0x0F); /* getting mask for val based on pin */
|
||||
uint8_t muxRate = lcd->LCDCTL0 & (LCD_LCDCTL0_LCDMXX_MASK);
|
||||
|
||||
switch (idx) {
|
||||
case 0:
|
||||
lcd->LCDCSSEL0 |= val;
|
||||
break;
|
||||
case 1:
|
||||
lcd->LCDCSSEL1 |= val;
|
||||
break;
|
||||
case 2:
|
||||
lcd->LCDCSSEL2 |= val;
|
||||
break;
|
||||
case 3:
|
||||
lcd->LCDCSSEL3 |= val;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Set LCDMem to COM as well for corresponding pins */
|
||||
if ((muxRate == LCD_LCDCTL0_LCDMXX_MX_STATIC) ||
|
||||
(muxRate == LCD_LCDCTL0_LCDMXX_MX_2) ||
|
||||
(muxRate == LCD_LCDCTL0_LCDMXX_MX_3) ||
|
||||
(muxRate == LCD_LCDCTL0_LCDMXX_MX_4)) {
|
||||
if (pin & 1) {
|
||||
/* upper nibble */
|
||||
lcd->LCDM[pin / 2] |= (com & 0xF) << 4;
|
||||
} else {
|
||||
/* lower nibble */
|
||||
lcd->LCDM[pin / 2] |= (com & 0xF);
|
||||
}
|
||||
} else {
|
||||
/* 5-mux, 6-mux, 7-mux, 8-mux, whole byte per segment pin */
|
||||
lcd->LCDM[pin] |= com;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_LCD_setPinAsSegment(LCD_Regs *lcd, uint8_t pin)
|
||||
{
|
||||
lcd->LCDCTL0 &= ~(LCD_LCDCTL0_LCDON_MASK);
|
||||
|
||||
uint8_t idx = pin >> 4; /* 0-15 -> 0, 16-31 -> 1, etc. */
|
||||
uint16_t val = 1 << (pin & 0x0F); /* getting mask for val based on pin */
|
||||
|
||||
switch (idx) {
|
||||
case 0:
|
||||
lcd->LCDCSSEL0 &= ~val;
|
||||
break;
|
||||
case 1:
|
||||
lcd->LCDCSSEL1 &= ~val;
|
||||
break;
|
||||
case 2:
|
||||
lcd->LCDCSSEL2 &= ~val;
|
||||
break;
|
||||
case 3:
|
||||
lcd->LCDCSSEL3 &= ~val;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_LCD__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_lfss.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_LFSS__
|
||||
#endif /* __MSPM0_HAS_LFSS__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_mathacl.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_MATHACL__
|
||||
|
||||
void DL_MathACL_configOperation(MATHACL_Regs *mathacl,
|
||||
const DL_MathACL_operationConfig *opConfig, uint32_t op1, uint32_t op2)
|
||||
{
|
||||
mathacl->CTL =
|
||||
(uint32_t) opConfig->opType | (uint32_t) opConfig->opSign |
|
||||
(uint32_t) opConfig->qType |
|
||||
((uint32_t) opConfig->iterations << MATHACL_CTL_NUMITER_OFS) |
|
||||
((uint32_t) opConfig->scaleFactor << MATHACL_CTL_SFACTOR_OFS);
|
||||
|
||||
DL_MathACL_setOperandTwo(mathacl, op2);
|
||||
DL_MathACL_setOperandOne(mathacl, op1);
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_MATHACL__ */
|
||||
@@ -0,0 +1,576 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_mathacl.h
|
||||
* @brief Math Accelerator Driver Library
|
||||
* @defgroup MATHACL Math Accelerator (MATHACL)
|
||||
*
|
||||
* @anchor ti_dl_dl_m0p_mathacl_Overview
|
||||
* # Overview
|
||||
*
|
||||
* The Math Accelerator Driver Library provides software to control the
|
||||
* onboard Math Accelerator hardware.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup MATHACL
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_dl_mathacl__include
|
||||
#define ti_dl_dl_mathacl__include
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
#include <ti/driverlib/dl_common.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_MATHACL__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/** @addtogroup DL_MATHACL_STATUS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief MATHACL operation underflow status
|
||||
*/
|
||||
#define DL_MATHACL_STATUS_UNDERFLOW (MATHACL_STATUS_UF_UNDERFLOW)
|
||||
|
||||
/*!
|
||||
* @brief MATHACL generic underflow bitmask for MATHACL Status register comparison
|
||||
*/
|
||||
#define DL_MATHACL_STATUS_UF_MASK (MATHACL_STATUS_UF_MASK)
|
||||
|
||||
/*!
|
||||
* @brief MATHACL operation overflow status
|
||||
*/
|
||||
#define DL_MATHACL_STATUS_OVERFLOW (MATHACL_STATUS_OVF_OVERFLOW)
|
||||
|
||||
/*!
|
||||
* @brief MATHACL generic overflow bitmask for MATHACL Status register comparison
|
||||
*/
|
||||
#define DL_MATHACL_STATUS_OVF_MASK (MATHACL_STATUS_OVF_MASK)
|
||||
|
||||
/*!
|
||||
* @brief MATHACL divide by error status
|
||||
*/
|
||||
#define DL_MATHACL_STATUS_ERR_DIVBY0 (MATHACL_STATUS_ERR_DIVBY0)
|
||||
|
||||
/*!
|
||||
* @brief MATHACL generic error bits mask
|
||||
*/
|
||||
#define DL_MATHACL_STATUS_ERR_MASK (MATHACL_STATUS_ERR_MASK)
|
||||
|
||||
/*!
|
||||
* @brief Alias for one-shot sin/cos operation
|
||||
*/
|
||||
#define DL_MathACL_startSinCosOperation(MATHACL, config, op) DL_MathACL_configOperation(MATHACL, config, op, 0)
|
||||
|
||||
/*!
|
||||
* @brief Alias for one-shot inverse 4-quadrant arctan operation
|
||||
*/
|
||||
#define DL_MathACL_startArcTan2Operation(MATHACL, config, x, y) DL_MathACL_configOperation(MATHACL, config, x, y)
|
||||
|
||||
/*!
|
||||
* @brief Alias for one-shot arctan operation
|
||||
*/
|
||||
#define DL_MathACL_startArcTanOperation(MATHACL, config, x) DL_MathACL_configOperation(MATHACL, config, x, 0)
|
||||
|
||||
/*!
|
||||
* @brief Alias for one-shot divide
|
||||
*/
|
||||
#define DL_MathACL_startDivOperation(MATHACL, config, num, den) DL_MathACL_configOperation(MATHACL, config, num, den)
|
||||
|
||||
/*!
|
||||
* @brief Alias for one-shot square root operation
|
||||
*/
|
||||
#define DL_MathACL_startSqrtOperation(MATHACL, config, sqrt) DL_MathACL_configOperation(MATHACL, config, sqrt, 0)
|
||||
|
||||
/*!
|
||||
* @brief Alias for one-shot multiply operation
|
||||
*/
|
||||
#define DL_MathACL_startMpyOperation(MATHACL, config, multicand, multiplier) DL_MathACL_configOperation(MATHACL, config, multicand, multiplier)
|
||||
|
||||
/** @}*/
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
/*! @enum DL_MATHACL_OP_TYPE */
|
||||
typedef enum {
|
||||
/*! Sin or cosine operation */
|
||||
DL_MATHACL_OP_TYPE_SINCOS = MATHACL_CTL_FUNC_SINCOS,
|
||||
/*! Arc tangent 2 operation -- takes in X, Y values */
|
||||
DL_MATHACL_OP_TYPE_ARCTAN2 = MATHACL_CTL_FUNC_ATAN2,
|
||||
/*! Divide operation -- takes in numerator, denominator, division type */
|
||||
DL_MATHACL_OP_TYPE_DIV = MATHACL_CTL_FUNC_DIV,
|
||||
/*! Square root operation -- requires that a scaling factor be provided as well */
|
||||
DL_MATHACL_OP_TYPE_SQRT = MATHACL_CTL_FUNC_SQRT,
|
||||
/*! Multiply operation returns 32-bit result -- takes in two operands */
|
||||
DL_MATHACL_OP_TYPE_MPY_32 = MATHACL_CTL_FUNC_MPY32,
|
||||
/*! Square operation returns 32-bit result -- takes in one operand. Supports
|
||||
* Q and int data formats. Enable saturation with @ref
|
||||
* DL_MathACL_enableSaturation and check @ref DL_MATHACL_STATUS_OVERFLOW
|
||||
* for overflow. */
|
||||
DL_MATHACL_OP_TYPE_SQUARE_32 = MATHACL_CTL_FUNC_SQUARE32,
|
||||
/*! Multiply operation returns 64-bit result -- takes in two operands */
|
||||
DL_MATHACL_OP_TYPE_MPY_64 = MATHACL_CTL_FUNC_MPY64,
|
||||
/*! Square operation returns 64-bit result -- takes in one operand */
|
||||
DL_MATHACL_OP_TYPE_SQUARE_64 = MATHACL_CTL_FUNC_SQUARE64,
|
||||
/*! Multiply and Accumulate operation -- takes in two operands. Supports Q
|
||||
* and int data formats. Enable saturation with @ref
|
||||
* DL_MathACL_enableSaturation and check @ref DL_MATHACL_STATUS_OVERFLOW
|
||||
* for overflow. */
|
||||
DL_MATHACL_OP_TYPE_MAC = MATHACL_CTL_FUNC_MAC,
|
||||
/*! Square and Accumulate operation -- takes in one operand. Supports Q and
|
||||
* int data formats. Enable saturation with @ref
|
||||
* DL_MathACL_enableSaturation and check @ref DL_MATHACL_STATUS_OVERFLOW
|
||||
* for overflow. */
|
||||
DL_MATHACL_OP_TYPE_SAC = MATHACL_CTL_FUNC_SAC,
|
||||
} DL_MATHACL_OP_TYPE;
|
||||
|
||||
/*! @enum DL_MATHACL_Q_TYPE */
|
||||
typedef enum {
|
||||
/*! Q0 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q0 = MATHACL_CTL_QVAL_Q0,
|
||||
/*! Q1 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q1 = MATHACL_CTL_QVAL_Q1,
|
||||
/*! Q2 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q2 = MATHACL_CTL_QVAL_Q2,
|
||||
/*! Q3 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q3 = MATHACL_CTL_QVAL_Q3,
|
||||
/*! Q4 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q4 = MATHACL_CTL_QVAL_Q4,
|
||||
/*! Q5 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q5 = MATHACL_CTL_QVAL_Q5,
|
||||
/*! Q6 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q6 = MATHACL_CTL_QVAL_Q6,
|
||||
/*! Q7 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q7 = MATHACL_CTL_QVAL_Q7,
|
||||
/*! Q8 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q8 = MATHACL_CTL_QVAL_Q8,
|
||||
/*! Q9 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q9 = MATHACL_CTL_QVAL_Q9,
|
||||
/*! Q10 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q10 = MATHACL_CTL_QVAL_Q10,
|
||||
/*! Q11 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q11 = MATHACL_CTL_QVAL_Q11,
|
||||
/*! Q12 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q12 = MATHACL_CTL_QVAL_Q12,
|
||||
/*! Q13 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q13 = MATHACL_CTL_QVAL_Q13,
|
||||
/*! Q14 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q14 = MATHACL_CTL_QVAL_Q14,
|
||||
/*! Q15 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q15 = MATHACL_CTL_QVAL_Q15,
|
||||
/*! Q16 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q16 = MATHACL_CTL_QVAL_Q16,
|
||||
/*! Q17 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q17 = MATHACL_CTL_QVAL_Q17,
|
||||
/*! Q18 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q18 = MATHACL_CTL_QVAL_Q18,
|
||||
/*! Q19 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q19 = MATHACL_CTL_QVAL_Q19,
|
||||
/*! Q20 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q20 = MATHACL_CTL_QVAL_Q20,
|
||||
/*! Q21 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q21 = MATHACL_CTL_QVAL_Q21,
|
||||
/*! Q22 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q22 = MATHACL_CTL_QVAL_Q22,
|
||||
/*! Q23 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q23 = MATHACL_CTL_QVAL_Q23,
|
||||
/*! Q24 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q24 = MATHACL_CTL_QVAL_Q24,
|
||||
/*! Q25 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q25 = MATHACL_CTL_QVAL_Q25,
|
||||
/*! Q26 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q26 = MATHACL_CTL_QVAL_Q26,
|
||||
/*! Q27 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q27 = MATHACL_CTL_QVAL_Q27,
|
||||
/*! Q28 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q28 = MATHACL_CTL_QVAL_Q28,
|
||||
/*! Q29 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q29 = MATHACL_CTL_QVAL_Q29,
|
||||
/*! Q30 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q30 = MATHACL_CTL_QVAL_Q30,
|
||||
/*! Q31 Operand Type */
|
||||
DL_MATHACL_Q_TYPE_Q31 = MATHACL_CTL_QVAL_Q31,
|
||||
} DL_MATHACL_Q_TYPE;
|
||||
|
||||
/*! @enum DL_MATHACL_OPSIGN */
|
||||
typedef enum {
|
||||
/*! Unsigned operation type */
|
||||
DL_MATHACL_OPSIGN_UNSIGNED = MATHACL_CTL_OPTYPE_UNSIGNED,
|
||||
/*! Signed operation type */
|
||||
DL_MATHACL_OPSIGN_SIGNED = MATHACL_CTL_OPTYPE_SIGNED,
|
||||
} DL_MATHACL_OPSIGN;
|
||||
|
||||
/**
|
||||
* @brief Configuration struct for @ref DL_MathACL_configOperation.
|
||||
*/
|
||||
typedef struct {
|
||||
/*! Operation type. Set to one of @ref DL_MATHACL_OP_TYPE */
|
||||
DL_MATHACL_OP_TYPE opType;
|
||||
/*! Operation sign type. One of @ref DL_MATHACL_OPSIGN */
|
||||
DL_MATHACL_OPSIGN opSign;
|
||||
/*! Number of iterations, for applicable operation types. Supported types
|
||||
include trigonometric operations and square root. */
|
||||
uint32_t iterations;
|
||||
/*! Scaling factor on the input in division operations. Leave as 0
|
||||
for non-division operations. */
|
||||
uint32_t scaleFactor;
|
||||
/*! Q value for the operand inputs for the operation */
|
||||
DL_MATHACL_Q_TYPE qType;
|
||||
} DL_MathACL_operationConfig;
|
||||
|
||||
/**
|
||||
* @brief Enables the Peripheral Write Enable (PWREN) register for the MATHACL
|
||||
*
|
||||
* Before any peripheral registers can be configured by software, the
|
||||
* peripheral itself must be enabled by writing the ENABLE bit together with
|
||||
* the appropriate KEY value to the peripheral's PWREN register.
|
||||
*
|
||||
* @param mathacl Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_MathACL_enablePower(MATHACL_Regs *mathacl)
|
||||
{
|
||||
mathacl->GPRCM.PWREN =
|
||||
MATHACL_PWREN_KEY_UNLOCK_W | MATHACL_PWREN_ENABLE_ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Peripheral Write Enable (PWREN) register for the MATHACL
|
||||
*
|
||||
* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
|
||||
* accessible for read/write operations.
|
||||
*
|
||||
* @note This API does not provide large power savings.
|
||||
*
|
||||
* @param mathacl Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_MathACL_disablePower(MATHACL_Regs *mathacl)
|
||||
{
|
||||
mathacl->GPRCM.PWREN =
|
||||
MATHACL_PWREN_KEY_UNLOCK_W | MATHACL_PWREN_ENABLE_DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if the Peripheral Write Enable (PWREN) register for the MATHACL
|
||||
* is enabled
|
||||
*
|
||||
* Before any peripheral registers can be configured by software, the
|
||||
* peripheral itself must be enabled by writing the ENABLE bit together with
|
||||
* the appropriate KEY value to the peripheral's PWREN register.
|
||||
*
|
||||
* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
|
||||
* accessible for read/write operations.
|
||||
*
|
||||
* @param mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return true if peripheral register access is enabled
|
||||
* @return false if peripheral register access is disabled
|
||||
*/
|
||||
__STATIC_INLINE bool DL_MathACL_isPowerEnabled(MATHACL_Regs *mathacl)
|
||||
{
|
||||
return ((mathacl->GPRCM.PWREN & MATHACL_PWREN_ENABLE_MASK) ==
|
||||
MATHACL_PWREN_ENABLE_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets the MATHACL module
|
||||
*
|
||||
* @param mathacl Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_MathACL_reset(MATHACL_Regs *mathacl)
|
||||
{
|
||||
mathacl->GPRCM.RSTCTL =
|
||||
MATHACL_RSTCTL_RESETASSERT_ASSERT | MATHACL_RSTCTL_KEY_UNLOCK_W;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if MATHACL peripheral was reset
|
||||
*
|
||||
* @param mathacl Pointer to the register overlay for the MATHACL peripheral
|
||||
*
|
||||
* @return true if peripheral was reset
|
||||
* @return false if peripheral wasn't reset
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE bool DL_MathACL_isReset(const MATHACL_Regs *mathacl)
|
||||
{
|
||||
return (mathacl->GPRCM.STAT & MATHACL_STAT_RESETSTKY_MASK) ==
|
||||
MATHACL_STAT_RESETSTKY_RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable saturation
|
||||
*
|
||||
* This bit is shared among @ref DL_MATHACL_OP_TYPE_DIV, @ref
|
||||
* DL_MATHACL_OP_TYPE_SQUARE_32, @ref DL_MATHACL_OP_TYPE_MPY_32, @ref
|
||||
* DL_MATHACL_OP_TYPE_MAC, and @ref DL_MATHACL_OP_TYPE_SAC operations.
|
||||
* When saturation is enabled, if there is an overflow event during an
|
||||
* operation, then the result will saturate to the maximum value.
|
||||
*
|
||||
* @param mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @sa DL_MATHACL_STATUS_OVERFLOW
|
||||
*/
|
||||
__STATIC_INLINE void DL_MathACL_enableSaturation(MATHACL_Regs *mathacl)
|
||||
{
|
||||
mathacl->CTL |= MATHACL_CTL_SATEN_ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable saturation
|
||||
*
|
||||
* When saturation is disabled, if there is an overflow event during an
|
||||
* operation, then the result will overflow to an unknown value.
|
||||
*
|
||||
* @param mathacl Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_MathACL_disableSaturation(MATHACL_Regs *mathacl)
|
||||
{
|
||||
mathacl->CTL &= ~(MATHACL_CTL_SATEN_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if saturation is enabled
|
||||
*
|
||||
* @param mathacl Pointer to the register overlay for the MATHACL peripheral
|
||||
*
|
||||
* @return true if saturation is enabled
|
||||
* @return false if saturation is not enabled
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE bool DL_MathACL_isSaturationEnabled(
|
||||
const MATHACL_Regs *mathacl)
|
||||
{
|
||||
return (
|
||||
(mathacl->CTL & MATHACL_CTL_SATEN_MASK) == MATHACL_CTL_SATEN_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Load Operand one into the math accelerator
|
||||
|
||||
* @param[in] mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @param[in] op Operand one to load into the Math Accelerator
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_MathACL_setOperandOne(
|
||||
MATHACL_Regs *mathacl, uint32_t op)
|
||||
{
|
||||
mathacl->OP1 = op;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Load Operand two into the math accelerator
|
||||
*
|
||||
* @param[in] mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @param[in] op Operand two to load into the Math Accelerator
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_MathACL_setOperandTwo(
|
||||
MATHACL_Regs *mathacl, uint32_t op)
|
||||
{
|
||||
mathacl->OP2 = op;
|
||||
}
|
||||
|
||||
/**
|
||||
* @param[in] mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @brief Returns MATHACL result one register
|
||||
*
|
||||
* @return Value stored in MATHACUL Result 1 status
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_MathACL_getResultOne(const MATHACL_Regs *mathacl)
|
||||
{
|
||||
return mathacl->RES1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @param[in] mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @brief Returns MATHACL result two register
|
||||
*
|
||||
* @return Value stored in MATHACUL Result 2 status
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_MathACL_getResultTwo(const MATHACL_Regs *mathacl)
|
||||
{
|
||||
return mathacl->RES2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @param[in] mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @brief Returns MATHACL operation status
|
||||
*
|
||||
* @return One of @ref DL_MATHACL_STATUS
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_MathACL_getStatus(const MATHACL_Regs *mathacl)
|
||||
{
|
||||
return mathacl->STATUS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the overflow status bit
|
||||
*
|
||||
* Calling this API clears @ref DL_MATHACL_STATUS_OVERFLOW
|
||||
*
|
||||
* @param[in] mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @sa DL_MATHACL_STATUS_OVERFLOW
|
||||
*/
|
||||
__STATIC_INLINE void DL_MathACL_clearOverflowStatus(MATHACL_Regs *mathacl)
|
||||
{
|
||||
mathacl->STATUSCLR |= MATHACL_STATUSCLR_CLR_OVF_CLR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the underflow status bit
|
||||
*
|
||||
* Calling this API clears @ref DL_MATHACL_STATUS_UNDERFLOW
|
||||
*
|
||||
* @param[in] mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @sa DL_MATHACL_STATUS_UNDERFLOW
|
||||
*/
|
||||
__STATIC_INLINE void DL_MathACL_clearUnderflowStatus(MATHACL_Regs *mathacl)
|
||||
{
|
||||
mathacl->STATUSCLR |= MATHACL_STATUSCLR_CLR_UF_CLR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the error status bit
|
||||
*
|
||||
* Calling this API clears @ref DL_MATHACL_STATUS_ERR_MASK
|
||||
*
|
||||
* @param[in] mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @sa DL_MATHACL_STATUS_ERR_MASK
|
||||
*/
|
||||
__STATIC_INLINE void DL_MathACL_clearErrorStatus(MATHACL_Regs *mathacl)
|
||||
{
|
||||
mathacl->STATUSCLR |= MATHACL_STATUSCLR_CLR_ERR_CLR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Block until MATHACL_STATUS_BUSY_DONE is active in MATHACL
|
||||
*
|
||||
* @param[in] mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_MathACL_waitForOperation(const MATHACL_Regs *mathacl)
|
||||
{
|
||||
while ((mathacl->STATUS & MATHACL_STATUS_BUSY_MASK) ==
|
||||
MATHACL_STATUS_BUSY_NOTDONE) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure and execute a Math accelerator operation
|
||||
*
|
||||
* @pre Call @ref DL_MathACL_clearResults when configuring the MATHACL
|
||||
* for performing @ref DL_MATHACL_OP_TYPE_MAC and
|
||||
* @ref DL_MATHACL_OP_TYPE_SAC operations.
|
||||
*
|
||||
* @param[in] mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @param[in] opConfig Pointer to the configuration structure for the
|
||||
* operation
|
||||
*
|
||||
* @param[in] op1 Operand one for the operation
|
||||
*
|
||||
* @param[in] op2 Operand two for the operation. May be left as 0
|
||||
* if unused
|
||||
*
|
||||
*/
|
||||
void DL_MathACL_configOperation(MATHACL_Regs *mathacl,
|
||||
const DL_MathACL_operationConfig *opConfig, uint32_t op1, uint32_t op2);
|
||||
|
||||
/**
|
||||
* @brief Clears the RES1 register
|
||||
*
|
||||
* Clears the Result 1 (RES1) register
|
||||
*
|
||||
* @param[in] mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_MathACL_clearResultOne(MATHACL_Regs *mathacl)
|
||||
{
|
||||
mathacl->RES1 = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the RES2 register
|
||||
*
|
||||
* Clears the Result 2 (RES2) register
|
||||
*
|
||||
* @param[in] mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_MathACL_clearResultTwo(MATHACL_Regs *mathacl)
|
||||
{
|
||||
mathacl->RES2 = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the RES1 and RES2 registers
|
||||
*
|
||||
* Clears the Result 1 (RES1) and Result 2 (RES2) registers
|
||||
*
|
||||
* @param[in] mathacl Pointer to the register overlay for the peripheral
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_MathACL_clearResults(MATHACL_Regs *mathacl)
|
||||
{
|
||||
mathacl->RES1 = 0;
|
||||
mathacl->RES2 = 0;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MSPM0_HAS_MATHACL__ */
|
||||
|
||||
#endif /* ti_dl_mathacl__include */
|
||||
/** @}*/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* Copyright (c) 2022, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_opa.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_OA__
|
||||
|
||||
DL_OPA_GAIN DL_OPA_increaseGain(OA_Regs *opa)
|
||||
{
|
||||
DL_OPA_GAIN currentGain = DL_OPA_getGain(opa);
|
||||
|
||||
/* if CFG.GAIN 0x5 do nothing */
|
||||
if (currentGain == DL_OPA_GAIN_N31_P32) {
|
||||
return DL_OPA_GAIN_N31_P32;
|
||||
} else {
|
||||
DL_OPA_setGain(opa,
|
||||
(uint32_t)(currentGain + (((uint32_t) 0x1) << OA_CFG_GAIN_OFS)));
|
||||
return DL_OPA_getGain(opa);
|
||||
}
|
||||
}
|
||||
|
||||
DL_OPA_GAIN DL_OPA_decreaseGain(OA_Regs *opa)
|
||||
{
|
||||
DL_OPA_GAIN currentGain = DL_OPA_getGain(opa);
|
||||
|
||||
/* if CFG.GAIN is 0x1 do nothing */
|
||||
if (currentGain == DL_OPA_GAIN_N1_P2) {
|
||||
return DL_OPA_GAIN_N1_P2;
|
||||
} else {
|
||||
DL_OPA_setGain(opa,
|
||||
(uint32_t)(currentGain - (((uint32_t) 0x1) << OA_CFG_GAIN_OFS)));
|
||||
return DL_OPA_getGain(opa);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_OA__ */
|
||||
@@ -0,0 +1,673 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_opa.h
|
||||
* @brief Op-Amp (OPA) Driver Library
|
||||
* @defgroup OPA Op-Amp (OPA)
|
||||
*
|
||||
* @anchor ti_dl_dl_opa_Overview
|
||||
* # Overview
|
||||
*
|
||||
* The OP-Amp Driver Library allows full configuration of the MSPM0 OPA module.
|
||||
* The OPA is a zero-drift chopper stabilized operational amplifier with a
|
||||
* programmable gain stage.
|
||||
*
|
||||
* <hr>
|
||||
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup OPA
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_dl_opa__include
|
||||
#define ti_dl_dl_opa__include
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
#include <ti/driverlib/dl_common.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_OA__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*! @enum DL_OPA_CHOPPING_MODE */
|
||||
typedef enum {
|
||||
/*! Disable chopping mode */
|
||||
DL_OPA_CHOPPING_MODE_DISABLE = OA_CFG_CHOP_OFF,
|
||||
/*! Enable standard chopping mode */
|
||||
DL_OPA_CHOPPING_MODE_STANDARD = OA_CFG_CHOP_ON,
|
||||
/*! Enable ADC assisted chopping mode. Requires OPA output to be
|
||||
connected to an ADC input with hardware averaging. */
|
||||
DL_OPA_CHOPPING_MODE_ADC_AVERAGING = OA_CFG_CHOP_AVGON,
|
||||
} DL_OPA_CHOPPING_MODE;
|
||||
|
||||
/*! @enum DL_OPA_OUTPUT_PIN_STATE */
|
||||
typedef enum {
|
||||
|
||||
/*! Output pin is enabled */
|
||||
DL_OPA_OUTPUT_PIN_ENABLED = OA_CFG_OUTPIN_ENABLED,
|
||||
/*! Outpin pin is disabled */
|
||||
DL_OPA_OUTPUT_PIN_DISABLED = OA_CFG_OUTPIN_DISABLED,
|
||||
|
||||
} DL_OPA_OUTPUT_PIN_STATE;
|
||||
|
||||
/*! @enum DL_OPA_PSEL */
|
||||
typedef enum {
|
||||
/*! Non-inverting input channel is Open */
|
||||
DL_OPA_PSEL_OPEN = OA_CFG_PSEL_NC,
|
||||
/*! Non-inverting input is OPAx_IN0+ */
|
||||
DL_OPA_PSEL_IN0_POS = OA_CFG_PSEL_EXTPIN0,
|
||||
/*! Non-inverting input is OPAx_IN1+ */
|
||||
DL_OPA_PSEL_IN1_POS = OA_CFG_PSEL_EXTPIN1,
|
||||
/*! Non-inverting input is DAC_OUT */
|
||||
DL_OPA_PSEL_DAC_OUT = OA_CFG_PSEL_DAC12OUT,
|
||||
/*! Non-inverting input is DAC8.x_OUT */
|
||||
DL_OPA_PSEL_DAC8_OUT = OA_CFG_PSEL_DAC8OUT,
|
||||
/*! Non-inverting input is VREF */
|
||||
DL_OPA_PSEL_VREF = OA_CFG_PSEL_VREF,
|
||||
/*! Non-inverting input is OPA[x-1]_RTOP */
|
||||
DL_OPA_PSEL_RTOP = OA_CFG_PSEL_OANM1RTOP,
|
||||
|
||||
/*! Non-inverting input is GPAMP OUT*/
|
||||
DL_OPA_PSEL_GPAMP_OUT = OA_CFG_PSEL_GPAMP_OUT_INT,
|
||||
/*! Non-inverting input is GND */
|
||||
DL_OPA_PSEL_GND = OA_CFG_PSEL_VSS,
|
||||
|
||||
} DL_OPA_PSEL;
|
||||
|
||||
/*! @enum DL_OPA_NSEL */
|
||||
typedef enum {
|
||||
/*! Inverting input channel is Open */
|
||||
DL_OPA_NSEL_OPEN = OA_CFG_NSEL_NC,
|
||||
/*! Inverting input channel is OPAx_IN0- */
|
||||
DL_OPA_NSEL_IN0_NEG = OA_CFG_NSEL_EXTPIN0,
|
||||
/*! Inverting input channel is OPAx_IN1- */
|
||||
DL_OPA_NSEL_IN1_NEG = OA_CFG_NSEL_EXTPIN1,
|
||||
/*! Inverting input channel is OPA[x-1]_RBOT */
|
||||
DL_OPA_NSEL_RBOT = OA_CFG_NSEL_OANP1RBOT,
|
||||
/*! Inverting input channel is RTAP */
|
||||
DL_OPA_NSEL_RTAP = OA_CFG_NSEL_OANRTAP,
|
||||
/*! Inverting input channel is RTOP */
|
||||
DL_OPA_NSEL_RTOP = OA_CFG_NSEL_OANRTOP,
|
||||
/*! Spare input for inverting channel */
|
||||
DL_OPA_NSEL_SPARE = OA_CFG_NSEL_SPARE,
|
||||
} DL_OPA_NSEL;
|
||||
|
||||
/*! @enum DL_OPA_MSEL */
|
||||
typedef enum {
|
||||
/*! M-MUX input channel is Open */
|
||||
DL_OPA_MSEL_OPEN = OA_CFG_MSEL_NC,
|
||||
/*! M-MUX input channel is OPAx_IN1- */
|
||||
DL_OPA_MSEL_IN1_NEG = OA_CFG_MSEL_EXTNPIN1,
|
||||
/*! M-MUX input channel is GND */
|
||||
DL_OPA_MSEL_GND = OA_CFG_MSEL_VSS,
|
||||
/*! M-MUX input channel is DAC_OUT */
|
||||
DL_OPA_MSEL_DAC_OUT = OA_CFG_MSEL_DAC12OUT,
|
||||
/*! M-MUX input channel is OPA[x-1]_RTOP */
|
||||
DL_OPA_MSEL_RTOP = OA_CFG_MSEL_OANM1RTOP,
|
||||
} DL_OPA_MSEL;
|
||||
|
||||
/*! @enum DL_OPA_GBW */
|
||||
typedef enum {
|
||||
/*! High gain bandwidth (GBW). See device specific datasheet for values. */
|
||||
DL_OPA_GBW_HIGH = OA_CFGBASE_GBW_HIGHGAIN,
|
||||
/*! Low gain bandwidth (GBW). See device specific datasheet for values. */
|
||||
DL_OPA_GBW_LOW = OA_CFGBASE_GBW_LOWGAIN,
|
||||
} DL_OPA_GBW;
|
||||
|
||||
/*! @enum DL_OPA_GAIN */
|
||||
typedef enum {
|
||||
/*! Gain value is Not Valid in Non-inverting and inverting PGA modes */
|
||||
DL_OPA_GAIN_N0_P1 = (((uint32_t) 0x0) << OA_CFG_GAIN_OFS),
|
||||
/*! Gain value is -1x in Inverting PGA mode, and 2x in Non-inverting
|
||||
* PGA mode */
|
||||
DL_OPA_GAIN_N1_P2 = (((uint32_t) 0x1) << OA_CFG_GAIN_OFS),
|
||||
/*! Gain value is -3x in Inverting PGA mode, and 4x in Non-inverting
|
||||
* PGA mode */
|
||||
DL_OPA_GAIN_N3_P4 = (((uint32_t) 0x2) << OA_CFG_GAIN_OFS),
|
||||
/*! Gain value is -7x in Inverting PGA mode, and 8x in Non-inverting
|
||||
* PGA mode */
|
||||
DL_OPA_GAIN_N7_P8 = (((uint32_t) 0x3) << OA_CFG_GAIN_OFS),
|
||||
/*! Gain value is -15x in Inverting PGA mode, and 16x in Non-inverting
|
||||
* PGA mode */
|
||||
DL_OPA_GAIN_N15_P16 = (((uint32_t) 0x4) << OA_CFG_GAIN_OFS),
|
||||
/*! Gain value is -31x in Inverting PGA mode, and 32x in Non-inverting
|
||||
* PGA mode */
|
||||
DL_OPA_GAIN_N31_P32 = (((uint32_t) 0x5) << OA_CFG_GAIN_OFS),
|
||||
} DL_OPA_GAIN;
|
||||
|
||||
/*!
|
||||
* @brief Configuration struct for @ref DL_OPA_init
|
||||
*/
|
||||
typedef struct {
|
||||
/*! The chopping mode to set. One of @ref DL_OPA_CHOPPING_MODE */
|
||||
DL_OPA_CHOPPING_MODE choppingMode;
|
||||
/*! The state of the output pin. One of @ref DL_OPA_OUTPUT_PIN_STATE. */
|
||||
DL_OPA_OUTPUT_PIN_STATE outputPinState;
|
||||
/*! The non-inverting input channel to set. One of @ref DL_OPA_PSEL */
|
||||
DL_OPA_PSEL pselChannel;
|
||||
/*! The inverting input channel to set. One of @ref DL_OPA_NSEL */
|
||||
DL_OPA_NSEL nselChannel;
|
||||
/*! The M-MUX input channel to set. One of @ref DL_OPA_MSEL */
|
||||
DL_OPA_MSEL mselChannel;
|
||||
/*! The gain to set. Value between 0-7. */
|
||||
DL_OPA_GAIN gain;
|
||||
} DL_OPA_Config;
|
||||
|
||||
/**
|
||||
* @brief Enables the Peripheral Write Enable (PWREN) register for the OPA
|
||||
*
|
||||
* Before any peripheral registers can be configured by software, the
|
||||
* peripheral itself must be enabled by writing the ENABLE bit together with
|
||||
* the appropriate KEY value to the peripheral's PWREN register.
|
||||
*
|
||||
* @note For power savings, please refer to @ref DL_OPA_enable
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_enablePower(OA_Regs *opa)
|
||||
{
|
||||
opa->GPRCM.PWREN = (OA_PWREN_KEY_UNLOCK_W | OA_PWREN_ENABLE_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Peripheral Write Enable (PWREN) register for the OPA
|
||||
*
|
||||
* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
|
||||
* accessible for read/write operations.
|
||||
*
|
||||
* @note This API does not provide large power savings. For power savings,
|
||||
* please refer to @ref DL_OPA_enable
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_disablePower(OA_Regs *opa)
|
||||
{
|
||||
opa->GPRCM.PWREN = (OA_PWREN_KEY_UNLOCK_W | OA_PWREN_ENABLE_DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if the Peripheral Write Enable (PWREN) register for the OPA
|
||||
* is enabled
|
||||
*
|
||||
* Before any peripheral registers can be configured by software, the
|
||||
* peripheral itself must be enabled by writing the ENABLE bit together with
|
||||
* the appropriate KEY value to the peripheral's PWREN register.
|
||||
*
|
||||
* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
|
||||
* accessible for read/write operations.
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return true if peripheral register access is enabled
|
||||
* @return false if peripheral register access is disabled
|
||||
*/
|
||||
__STATIC_INLINE bool DL_OPA_isPowerEnabled(const OA_Regs *opa)
|
||||
{
|
||||
return (
|
||||
(opa->GPRCM.PWREN & OA_PWREN_ENABLE_MASK) == OA_PWREN_ENABLE_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets OPA peripheral
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_reset(OA_Regs *opa)
|
||||
{
|
||||
opa->GPRCM.RSTCTL = (OA_RSTCTL_KEY_UNLOCK_W | OA_RSTCTL_RESETSTKYCLR_CLR |
|
||||
OA_RSTCTL_RESETASSERT_ASSERT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if OPA peripheral was reset
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return true if peripheral was reset
|
||||
* @return false if peripheral wasn't reset
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE bool DL_OPA_isReset(const OA_Regs *opa)
|
||||
{
|
||||
return ((opa->GPRCM.STAT & OA_GPRCM_STAT_RESETSTKY_MASK) ==
|
||||
OA_GPRCM_STAT_RESETSTKY_RESET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the OPA peripheral
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_enable(OA_Regs *opa)
|
||||
{
|
||||
opa->CTL |= OA_CTL_ENABLE_ON;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if the OPA peripheral is enabled
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return Returns the enabled status of the OPA
|
||||
*
|
||||
* @retval true The OPA peripheral is enabled
|
||||
* @retval false The OPA peripheral is disabled
|
||||
|
||||
*/
|
||||
__STATIC_INLINE bool DL_OPA_isEnabled(const OA_Regs *opa)
|
||||
{
|
||||
return ((opa->CTL & OA_CTL_ENABLE_MASK) == OA_CTL_ENABLE_ON);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the OPA peripheral
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_disable(OA_Regs *opa)
|
||||
{
|
||||
opa->CTL &= ~(OA_CTL_ENABLE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the OPA peripheral
|
||||
*
|
||||
* Initializes all the common configurable options for the OPA peripheral. Any
|
||||
* other custom configuration can be done after calling this API. The OPA is
|
||||
* not enabled in this API.
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
* @param[in] config Configuration for OPA peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_init(OA_Regs *opa, const DL_OPA_Config *config)
|
||||
{
|
||||
DL_Common_updateReg(&opa->CFG,
|
||||
(uint32_t) config->choppingMode | (uint32_t) config->outputPinState |
|
||||
(uint32_t) config->pselChannel | (uint32_t) config->nselChannel |
|
||||
(uint32_t) config->mselChannel | (uint32_t) config->gain,
|
||||
OA_CFG_CHOP_MASK | OA_CFG_OUTPIN_MASK | OA_CFG_PSEL_MASK |
|
||||
OA_CFG_NSEL_MASK | OA_CFG_MSEL_MASK | OA_CFG_GAIN_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the gain bandwidth (GBW)
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
* @param[in] bandwidth The gain bandwidth to set. One of @ref DL_OPA_GBW
|
||||
*
|
||||
*
|
||||
* @pre The OPA must be ready (STAT.RDY == 1) before setting
|
||||
* this configuration.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_setGainBandwidth(
|
||||
OA_Regs *opa, DL_OPA_GBW bandwidth)
|
||||
{
|
||||
opa->CFGBASE |= ((uint32_t) bandwidth);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the gain bandwidth (GBW)
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The current gain bandwidth
|
||||
*
|
||||
* @retval One of @ref DL_OPA_GBW
|
||||
*/
|
||||
__STATIC_INLINE DL_OPA_GBW DL_OPA_getGainBandwidth(const OA_Regs *opa)
|
||||
{
|
||||
uint32_t bandwidth = (opa->CFGBASE & OA_CFGBASE_GBW_MASK);
|
||||
|
||||
return (DL_OPA_GBW)(bandwidth);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the rail-to-rail input (RRI)
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
*
|
||||
* @pre The OPA must be ready (STAT.RDY == 1) before setting
|
||||
* this configuration.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_enableRailToRailInput(OA_Regs *opa)
|
||||
{
|
||||
opa->CFGBASE |= OA_CFGBASE_RRI_ON;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if the the rail-to-rail input (RRI) is enabled
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return Returns the rail-to-rail input status of the OPA
|
||||
*
|
||||
* @retval true The rail-to-rail input is enabled
|
||||
* @retval false The rail-to-rail input is disabled
|
||||
|
||||
*/
|
||||
__STATIC_INLINE bool DL_OPA_isRailToRailInputEnabled(OA_Regs *opa)
|
||||
{
|
||||
return ((opa->CFGBASE &= OA_CFGBASE_RRI_MASK) == OA_CFGBASE_RRI_ON);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the rail-to-rail input (RRI)
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_disableRailToRailInput(OA_Regs *opa)
|
||||
{
|
||||
opa->CFGBASE &= ~(OA_CFGBASE_RRI_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set and enable the chopping mode
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
* @param[in] mode The chopping mode to set.
|
||||
* One of @ref DL_OPA_CHOPPING_MODE
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_setChoppingMode(
|
||||
OA_Regs *opa, DL_OPA_CHOPPING_MODE mode)
|
||||
{
|
||||
DL_Common_updateReg(&opa->CFG, (uint32_t) mode, OA_CFG_CHOP_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the chopping mode
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The current chopping mode
|
||||
*
|
||||
* @retval One of @ref DL_OPA_CHOPPING_MODE
|
||||
*/
|
||||
__STATIC_INLINE DL_OPA_CHOPPING_MODE DL_OPA_getChoppingMode(const OA_Regs *opa)
|
||||
{
|
||||
uint32_t mode = (opa->CFG & OA_CFG_CHOP_MASK);
|
||||
|
||||
return (DL_OPA_CHOPPING_MODE)(mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the state of the output pin
|
||||
*
|
||||
* When the output pin is enabled, the OPA output goes to the device pin while
|
||||
* still maintaining connection to the programmable gain stage and other analog
|
||||
* peripherals.
|
||||
* When disabled, the OPA output is a purely internal signal and is internally
|
||||
* connected to the programmable gain stage and capable of being routed to
|
||||
* other on-board analog peripherals.
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
* @param[in] state The state to set the output pin to
|
||||
* One of @ref DL_OPA_OUTPUT_PIN_STATE
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_setOutputPinState(
|
||||
OA_Regs *opa, DL_OPA_OUTPUT_PIN_STATE state)
|
||||
{
|
||||
DL_Common_updateReg(&opa->CFG, (uint32_t) state, OA_CFG_OUTPIN_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the state of the output pin
|
||||
*
|
||||
* When the output pin is enabled, the OPA output goes to the device pin while
|
||||
* still maintaining connection to the programmable gain stage and other analog
|
||||
* peripherals.
|
||||
* When disabled, the OPA output is a purely internal signal and is internally
|
||||
* connected to the programmable gain stage and capable of being routed to
|
||||
* other on-board analog peripherals.
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The state of the output pin
|
||||
*
|
||||
* @retval One of @ref DL_OPA_OUTPUT_PIN_STATE
|
||||
*/
|
||||
__STATIC_INLINE DL_OPA_OUTPUT_PIN_STATE DL_OPA_getOutputPinState(
|
||||
const OA_Regs *opa)
|
||||
{
|
||||
uint32_t state = (opa->CFG & OA_CFG_OUTPIN_MASK);
|
||||
|
||||
return (DL_OPA_OUTPUT_PIN_STATE)(state);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the OPA output signal to be accessed by a device pin
|
||||
*
|
||||
* When disabled, the OPA output is a purely internal signal and is internally
|
||||
* connected to the programmable gain stage and capable of being routed to
|
||||
* other on-board analog peripherals.
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_disableOutputPin(OA_Regs *opa)
|
||||
{
|
||||
opa->CFG &= ~(OA_CFG_OUTPIN_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the non-inverting input channel
|
||||
*
|
||||
* This API sets the PSEL control bit to select the non-inverting input
|
||||
* channel of the amplifier.
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
* @param[in] inputChannel The non-inverting input channel to set.
|
||||
* One of @ref DL_OPA_PSEL.
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_setNonInvertingInputChannel(
|
||||
OA_Regs *opa, DL_OPA_PSEL inputChannel)
|
||||
{
|
||||
DL_Common_updateReg(&opa->CFG, (uint32_t) inputChannel, OA_CFG_PSEL_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the non-inverting input channel
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The current non-inverting input channel
|
||||
*
|
||||
* @retval One of @ref DL_OPA_PSEL
|
||||
*/
|
||||
__STATIC_INLINE DL_OPA_PSEL DL_OPA_getNonInvertingInputChannel(
|
||||
const OA_Regs *opa)
|
||||
{
|
||||
uint32_t inputChannel = (opa->CFG & OA_CFG_PSEL_MASK);
|
||||
|
||||
return (DL_OPA_PSEL)(inputChannel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the inverting input channel
|
||||
*
|
||||
* This API sets the NSEL control bit to select the inverting input
|
||||
* channel of the amplifier.
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
* @param[in] inputChannel The inverting input channel to set.
|
||||
* One of @ref DL_OPA_NSEL.
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_setInvertingInputChannel(
|
||||
OA_Regs *opa, DL_OPA_NSEL inputChannel)
|
||||
{
|
||||
DL_Common_updateReg(&opa->CFG, (uint32_t) inputChannel, OA_CFG_NSEL_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the inverting input channel
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The current inverting input channel
|
||||
*
|
||||
* @retval One of @ref DL_OPA_NSEL
|
||||
*/
|
||||
__STATIC_INLINE DL_OPA_NSEL DL_OPA_getInvertingInputChannel(const OA_Regs *opa)
|
||||
{
|
||||
uint32_t inputChannel = (opa->CFG & OA_CFG_NSEL_MASK);
|
||||
|
||||
return (DL_OPA_NSEL)(inputChannel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the M-MUX input channel
|
||||
*
|
||||
* This API sets the MSEL control bit to select the input channel for M-MUX,
|
||||
* which is connected to the programmable gain stage resistor ladder.
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
* @param[in] inputChannel The M-MUX input channel to set.
|
||||
* One of @ref DL_OPA_MSEL.
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_setMMUXInputChannel(
|
||||
OA_Regs *opa, DL_OPA_MSEL inputChannel)
|
||||
{
|
||||
DL_Common_updateReg(&opa->CFG, (uint32_t) inputChannel, OA_CFG_MSEL_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the M-MUX input channel
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The current M-MUX input channel
|
||||
*
|
||||
* @retval One of @ref DL_OPA_MSEL
|
||||
*/
|
||||
__STATIC_INLINE DL_OPA_MSEL DL_OPA_getMMUXInputChannel(const OA_Regs *opa)
|
||||
{
|
||||
uint32_t inputChannel = (opa->CFG & OA_CFG_MSEL_MASK);
|
||||
|
||||
return (DL_OPA_MSEL)(inputChannel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the gain for the programmable gain stage
|
||||
*
|
||||
* The OPA integrates a programmable gain stage in the feedback loop to
|
||||
* configure the OPA as a PGA(programmable gain amplifier). The gain stage
|
||||
* is a feedback resistance ladder and it supports up to 32x amplification.
|
||||
*
|
||||
* Refer to the TRM for gain enumeration information.
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
* @param[in] gain The gain to set. One of @ref DL_OPA_GAIN.
|
||||
*/
|
||||
__STATIC_INLINE void DL_OPA_setGain(OA_Regs *opa, DL_OPA_GAIN gain)
|
||||
{
|
||||
DL_Common_updateReg(&opa->CFG, (uint32_t) gain, OA_CFG_GAIN_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the gain from the programmable gain stage
|
||||
*
|
||||
* Refer to the TRM for gain enumeration information.
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The gain
|
||||
*
|
||||
* @retval The gain. One of @ref DL_OPA_GAIN
|
||||
*/
|
||||
__STATIC_INLINE DL_OPA_GAIN DL_OPA_getGain(const OA_Regs *opa)
|
||||
{
|
||||
uint32_t gain = (opa->CFG & OA_CFG_GAIN_MASK);
|
||||
|
||||
return (DL_OPA_GAIN)(gain);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Increment gain to the next @ref DL_OPA_GAIN enum value
|
||||
*
|
||||
* The OPA allows dynamic gain changes. If the gain is already at the maximum
|
||||
* setting DL_OPA_GAIN_N31_P32 (CFG.GAIN = 0x5), this function does nothing.
|
||||
*
|
||||
* Refer to the TRM for more information about changing gain dynamically.
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The gain at the end of the operation.
|
||||
*
|
||||
* @retval The applied gain. One of @ref DL_OPA_GAIN
|
||||
*/
|
||||
DL_OPA_GAIN DL_OPA_increaseGain(OA_Regs *opa);
|
||||
|
||||
/**
|
||||
* @brief Decrement gain to the next @ref DL_OPA_GAIN enum value
|
||||
*
|
||||
* The OPA allows dynamic gain changes. If the gain is at the minimum setting
|
||||
* DL_OPA_GAIN_N1_P2 (CFG.GAIN = 0x1), this function does nothing.
|
||||
*
|
||||
* Refer to the TRM for more information about changing gain dynamically.
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The gain at the end of the operation.
|
||||
*
|
||||
* @retval The applied gain. One of @ref DL_OPA_GAIN
|
||||
*/
|
||||
DL_OPA_GAIN DL_OPA_decreaseGain(OA_Regs *opa);
|
||||
|
||||
/**
|
||||
* @brief Checks if the OPA is ready
|
||||
*
|
||||
* @param[in] opa Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The status of the OPA ready bit
|
||||
*
|
||||
* @retval true The OPA is ready
|
||||
* @retval false The OPA is not ready
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE bool DL_OPA_isReady(const OA_Regs *opa)
|
||||
{
|
||||
return ((opa->STAT & OA_STAT_RDY_MASK) == OA_STAT_RDY_TRUE);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __MSPM0_HAS_OA__ */
|
||||
|
||||
#endif /* ti_dl_dl_opa__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2025, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_rtc.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_RTC__
|
||||
#endif /* __MSPM0_HAS_RTC__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2025, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_rtc_a.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_RTC_A__
|
||||
#endif /* __MSPM0_HAS_RTC_A__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2025, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_rtc_b.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_RTC_B__
|
||||
#endif /* __MSPM0_HAS_RTC_B__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,281 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_rtc_common.h>
|
||||
|
||||
#if defined __MSPM0_HAS_RTC_A__ || defined __MSPM0_HAS_RTC_B__ || \
|
||||
defined __MSPM0_HAS_RTC__
|
||||
|
||||
void DL_RTC_Common_initCalendar(RTC_Regs *rtc_common,
|
||||
DL_RTC_Common_Calendar calendarTime, DL_RTC_COMMON_FORMAT formatSelect)
|
||||
{
|
||||
DL_RTC_Common_setClockFormat(rtc_common, formatSelect);
|
||||
|
||||
if (formatSelect == DL_RTC_COMMON_FORMAT_BINARY) {
|
||||
DL_RTC_Common_setCalendarSecondsBinary(
|
||||
rtc_common, calendarTime.seconds);
|
||||
DL_RTC_Common_setCalendarMinutesBinary(
|
||||
rtc_common, calendarTime.minutes);
|
||||
DL_RTC_Common_setCalendarHoursBinary(rtc_common, calendarTime.hours);
|
||||
/*
|
||||
* Back to back writes to counter/calendar registers such as
|
||||
* SEC, MIN, HOUR, DAY, MON, YEAR need to be avoided since writes
|
||||
* to calendar registers take 2 to 3 RTCCLK cycles to take effect.
|
||||
*/
|
||||
DL_Common_updateReg(&rtc_common->DAY,
|
||||
(uint32_t) calendarTime.dayOfWeek |
|
||||
((uint32_t) calendarTime.dayOfMonth << RTC_DAY_DOMBIN_OFS),
|
||||
RTC_DAY_DOW_MASK | RTC_DAY_DOMBIN_MASK);
|
||||
DL_RTC_Common_setCalendarMonthBinary(rtc_common, calendarTime.month);
|
||||
DL_RTC_Common_setCalendarYearBinary(rtc_common, calendarTime.year);
|
||||
} else {
|
||||
DL_RTC_Common_setCalendarSecondsBCD(rtc_common, calendarTime.seconds);
|
||||
DL_RTC_Common_setCalendarMinutesBCD(rtc_common, calendarTime.minutes);
|
||||
DL_RTC_Common_setCalendarHoursBCD(rtc_common, calendarTime.hours);
|
||||
DL_Common_updateReg(&rtc_common->DAY,
|
||||
(uint32_t) calendarTime.dayOfWeek |
|
||||
((uint32_t) calendarTime.dayOfMonth << RTC_DAY_DOMLOWBCD_OFS),
|
||||
RTC_DAY_DOW_MASK | RTC_DAY_DOMLOWBCD_MASK |
|
||||
RTC_DAY_DOMHIGHBCD_MASK);
|
||||
DL_RTC_Common_setCalendarMonthBCD(rtc_common, calendarTime.month);
|
||||
DL_RTC_Common_setCalendarYearBCD(rtc_common, calendarTime.year);
|
||||
}
|
||||
}
|
||||
|
||||
DL_RTC_Common_Calendar DL_RTC_Common_getCalendarTime(
|
||||
const RTC_Regs *rtc_common)
|
||||
{
|
||||
DL_RTC_Common_Calendar calendarTime;
|
||||
DL_RTC_COMMON_FORMAT format;
|
||||
|
||||
format = DL_RTC_Common_getClockFormat(rtc_common);
|
||||
|
||||
if (format == DL_RTC_COMMON_FORMAT_BINARY) {
|
||||
calendarTime.seconds =
|
||||
DL_RTC_Common_getCalendarSecondsBinary(rtc_common);
|
||||
calendarTime.minutes =
|
||||
DL_RTC_Common_getCalendarMinutesBinary(rtc_common);
|
||||
calendarTime.hours = DL_RTC_Common_getCalendarHoursBinary(rtc_common);
|
||||
calendarTime.dayOfWeek =
|
||||
DL_RTC_Common_getCalendarDayOfWeekBinary(rtc_common);
|
||||
calendarTime.dayOfMonth =
|
||||
DL_RTC_Common_getCalendarDayOfMonthBinary(rtc_common);
|
||||
calendarTime.month = DL_RTC_Common_getCalendarMonthBinary(rtc_common);
|
||||
calendarTime.year = DL_RTC_Common_getCalendarYearBinary(rtc_common);
|
||||
} else {
|
||||
calendarTime.seconds = DL_RTC_Common_getCalendarSecondsBCD(rtc_common);
|
||||
calendarTime.minutes = DL_RTC_Common_getCalendarMinutesBCD(rtc_common);
|
||||
calendarTime.hours = DL_RTC_Common_getCalendarHoursBCD(rtc_common);
|
||||
calendarTime.dayOfWeek =
|
||||
DL_RTC_Common_getCalendarDayOfWeekBCD(rtc_common);
|
||||
calendarTime.dayOfMonth =
|
||||
DL_RTC_Common_getCalendarDayOfMonthBCD(rtc_common);
|
||||
calendarTime.month = DL_RTC_Common_getCalendarMonthBCD(rtc_common);
|
||||
calendarTime.year = DL_RTC_Common_getCalendarYearBCD(rtc_common);
|
||||
}
|
||||
|
||||
return calendarTime;
|
||||
}
|
||||
|
||||
void DL_RTC_Common_setCalendarAlarm1(
|
||||
RTC_Regs *rtc_common, DL_RTC_Common_CalendarAlarm alarmTime)
|
||||
{
|
||||
DL_RTC_COMMON_FORMAT format;
|
||||
|
||||
format = DL_RTC_Common_getClockFormat(rtc_common);
|
||||
|
||||
if (format == DL_RTC_COMMON_FORMAT_BINARY) {
|
||||
DL_RTC_Common_setAlarm1MinutesBinary(rtc_common, alarmTime.minutes);
|
||||
DL_RTC_Common_setAlarm1HoursBinary(rtc_common, alarmTime.hours);
|
||||
DL_RTC_Common_setAlarm1DayOfWeekBinary(
|
||||
rtc_common, alarmTime.dayOfWeek);
|
||||
DL_RTC_Common_setAlarm1DayOfMonthBinary(
|
||||
rtc_common, alarmTime.dayOfMonth);
|
||||
} else {
|
||||
DL_RTC_Common_setAlarm1MinutesBCD(rtc_common, alarmTime.minutes);
|
||||
DL_RTC_Common_setAlarm1HoursBCD(rtc_common, alarmTime.hours);
|
||||
DL_RTC_Common_setAlarm1DayOfWeekBCD(rtc_common, alarmTime.dayOfWeek);
|
||||
DL_RTC_Common_setAlarm1DayOfMonthBCD(rtc_common, alarmTime.dayOfMonth);
|
||||
}
|
||||
}
|
||||
|
||||
DL_RTC_Common_CalendarAlarm DL_RTC_Common_getCalendarAlarm1(
|
||||
const RTC_Regs *rtc_common)
|
||||
{
|
||||
DL_RTC_Common_CalendarAlarm alarmTime;
|
||||
DL_RTC_COMMON_FORMAT format;
|
||||
|
||||
format = DL_RTC_Common_getClockFormat(rtc_common);
|
||||
|
||||
if (format == DL_RTC_COMMON_FORMAT_BINARY) {
|
||||
alarmTime.minutes = DL_RTC_Common_getAlarm1MinutesBinary(rtc_common);
|
||||
alarmTime.hours = DL_RTC_Common_getAlarm1HoursBinary(rtc_common);
|
||||
alarmTime.dayOfWeek =
|
||||
DL_RTC_Common_getAlarm1DayOfWeekBinary(rtc_common);
|
||||
alarmTime.dayOfMonth =
|
||||
DL_RTC_Common_getAlarm1DayOfMonthBinary(rtc_common);
|
||||
} else {
|
||||
alarmTime.minutes = DL_RTC_Common_getAlarm1MinutesBCD(rtc_common);
|
||||
alarmTime.hours = DL_RTC_Common_getAlarm1HoursBCD(rtc_common);
|
||||
alarmTime.dayOfWeek = DL_RTC_Common_getAlarm1DayOfWeekBCD(rtc_common);
|
||||
alarmTime.dayOfMonth =
|
||||
DL_RTC_Common_getAlarm1DayOfMonthBCD(rtc_common);
|
||||
}
|
||||
|
||||
return alarmTime;
|
||||
}
|
||||
|
||||
void DL_RTC_Common_enableCalendarAlarm1(RTC_Regs *rtc_common)
|
||||
{
|
||||
DL_RTC_COMMON_FORMAT format;
|
||||
|
||||
format = DL_RTC_Common_getClockFormat(rtc_common);
|
||||
|
||||
if (format == DL_RTC_COMMON_FORMAT_BINARY) {
|
||||
DL_RTC_Common_enableAlarm1MinutesBinary(rtc_common);
|
||||
DL_RTC_Common_enableAlarm1HoursBinary(rtc_common);
|
||||
DL_RTC_Common_enableAlarm1DayOfWeekBinary(rtc_common);
|
||||
DL_RTC_Common_enableAlarm1DayOfMonthBinary(rtc_common);
|
||||
} else {
|
||||
DL_RTC_Common_enableAlarm1MinutesBCD(rtc_common);
|
||||
DL_RTC_Common_enableAlarm1HoursBCD(rtc_common);
|
||||
DL_RTC_Common_enableAlarm1DayOfWeekBCD(rtc_common);
|
||||
DL_RTC_Common_enableAlarm1DayOfMonthBCD(rtc_common);
|
||||
}
|
||||
}
|
||||
|
||||
void DL_RTC_Common_disableCalendarAlarm1(RTC_Regs *rtc_common)
|
||||
{
|
||||
DL_RTC_COMMON_FORMAT format;
|
||||
|
||||
format = DL_RTC_Common_getClockFormat(rtc_common);
|
||||
|
||||
if (format == DL_RTC_COMMON_FORMAT_BINARY) {
|
||||
DL_RTC_Common_disableAlarm1MinutesBinary(rtc_common);
|
||||
DL_RTC_Common_disableAlarm1HoursBinary(rtc_common);
|
||||
DL_RTC_Common_disableAlarm1DayOfWeekBinary(rtc_common);
|
||||
DL_RTC_Common_disableAlarm1DayOfMonthBinary(rtc_common);
|
||||
} else {
|
||||
DL_RTC_Common_disableAlarm1MinutesBCD(rtc_common);
|
||||
DL_RTC_Common_disableAlarm1HoursBCD(rtc_common);
|
||||
DL_RTC_Common_disableAlarm1DayOfWeekBCD(rtc_common);
|
||||
DL_RTC_Common_disableAlarm1DayOfMonthBCD(rtc_common);
|
||||
}
|
||||
}
|
||||
|
||||
void DL_RTC_Common_setCalendarAlarm2(
|
||||
RTC_Regs *rtc_common, DL_RTC_Common_CalendarAlarm alarmTime)
|
||||
{
|
||||
DL_RTC_COMMON_FORMAT format;
|
||||
|
||||
format = DL_RTC_Common_getClockFormat(rtc_common);
|
||||
|
||||
if (format == DL_RTC_COMMON_FORMAT_BINARY) {
|
||||
DL_RTC_Common_setAlarm2MinutesBinary(rtc_common, alarmTime.minutes);
|
||||
DL_RTC_Common_setAlarm2HoursBinary(rtc_common, alarmTime.hours);
|
||||
DL_RTC_Common_setAlarm2DayOfWeekBinary(
|
||||
rtc_common, alarmTime.dayOfWeek);
|
||||
DL_RTC_Common_setAlarm2DayOfMonthBinary(
|
||||
rtc_common, alarmTime.dayOfMonth);
|
||||
} else {
|
||||
DL_RTC_Common_setAlarm2MinutesBCD(rtc_common, alarmTime.minutes);
|
||||
DL_RTC_Common_setAlarm2HoursBCD(rtc_common, alarmTime.hours);
|
||||
DL_RTC_Common_setAlarm2DayOfWeekBCD(rtc_common, alarmTime.dayOfWeek);
|
||||
DL_RTC_Common_setAlarm2DayOfMonthBCD(rtc_common, alarmTime.dayOfMonth);
|
||||
}
|
||||
}
|
||||
|
||||
DL_RTC_Common_CalendarAlarm DL_RTC_Common_getCalendarAlarm2(
|
||||
const RTC_Regs *rtc_common)
|
||||
{
|
||||
DL_RTC_Common_CalendarAlarm alarmTime;
|
||||
DL_RTC_COMMON_FORMAT format;
|
||||
|
||||
format = DL_RTC_Common_getClockFormat(rtc_common);
|
||||
|
||||
if (format == DL_RTC_COMMON_FORMAT_BINARY) {
|
||||
alarmTime.minutes = DL_RTC_Common_getAlarm2MinutesBinary(rtc_common);
|
||||
alarmTime.hours = DL_RTC_Common_getAlarm2HoursBinary(rtc_common);
|
||||
alarmTime.dayOfWeek =
|
||||
DL_RTC_Common_getAlarm2DayOfWeekBinary(rtc_common);
|
||||
alarmTime.dayOfMonth =
|
||||
DL_RTC_Common_getAlarm2DayOfMonthBinary(rtc_common);
|
||||
} else {
|
||||
alarmTime.minutes = DL_RTC_Common_getAlarm2MinutesBCD(rtc_common);
|
||||
alarmTime.hours = DL_RTC_Common_getAlarm2HoursBCD(rtc_common);
|
||||
alarmTime.dayOfWeek = DL_RTC_Common_getAlarm2DayOfWeekBCD(rtc_common);
|
||||
alarmTime.dayOfMonth =
|
||||
DL_RTC_Common_getAlarm2DayOfMonthBCD(rtc_common);
|
||||
}
|
||||
|
||||
return alarmTime;
|
||||
}
|
||||
|
||||
void DL_RTC_Common_enableCalendarAlarm2(RTC_Regs *rtc_common)
|
||||
{
|
||||
DL_RTC_COMMON_FORMAT format;
|
||||
|
||||
format = DL_RTC_Common_getClockFormat(rtc_common);
|
||||
|
||||
if (format == DL_RTC_COMMON_FORMAT_BINARY) {
|
||||
DL_RTC_Common_enableAlarm2MinutesBinary(rtc_common);
|
||||
DL_RTC_Common_enableAlarm2HoursBinary(rtc_common);
|
||||
DL_RTC_Common_enableAlarm2DayOfWeekBinary(rtc_common);
|
||||
DL_RTC_Common_enableAlarm2DayOfMonthBinary(rtc_common);
|
||||
} else {
|
||||
DL_RTC_Common_enableAlarm2MinutesBCD(rtc_common);
|
||||
DL_RTC_Common_enableAlarm2HoursBCD(rtc_common);
|
||||
DL_RTC_Common_enableAlarm2DayOfWeekBCD(rtc_common);
|
||||
DL_RTC_Common_enableAlarm2DayOfMonthBCD(rtc_common);
|
||||
}
|
||||
}
|
||||
|
||||
void DL_RTC_Common_disableCalendarAlarm2(RTC_Regs *rtc_common)
|
||||
{
|
||||
DL_RTC_COMMON_FORMAT format;
|
||||
|
||||
format = DL_RTC_Common_getClockFormat(rtc_common);
|
||||
|
||||
if (format == DL_RTC_COMMON_FORMAT_BINARY) {
|
||||
DL_RTC_Common_disableAlarm2MinutesBinary(rtc_common);
|
||||
DL_RTC_Common_disableAlarm2HoursBinary(rtc_common);
|
||||
DL_RTC_Common_disableAlarm2DayOfWeekBinary(rtc_common);
|
||||
DL_RTC_Common_disableAlarm2DayOfMonthBinary(rtc_common);
|
||||
} else {
|
||||
DL_RTC_Common_disableAlarm2MinutesBCD(rtc_common);
|
||||
DL_RTC_Common_disableAlarm2HoursBCD(rtc_common);
|
||||
DL_RTC_Common_disableAlarm2DayOfWeekBCD(rtc_common);
|
||||
DL_RTC_Common_disableAlarm2DayOfMonthBCD(rtc_common);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_RTC_A__ || __MSPM0_HAS_RTC_B__ || defined __MSPM0_HAS_RTC__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2025, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_scratchpad.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_SCRATCHPAD__
|
||||
#endif /* __MSPM0_HAS_SCRATCHPAD__ */
|
||||
@@ -0,0 +1,224 @@
|
||||
/*
|
||||
* Copyright (c) 2023, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_scratchpad.h
|
||||
* @brief Scratchpad Memory Driver Library
|
||||
* @defgroup Scratchpad Memory
|
||||
*
|
||||
* @anchor ti_dl_dl_scratchpad_Overview
|
||||
* # Overview
|
||||
*
|
||||
* The Scratchpad Memory Library allows full configuration of
|
||||
* the MSPM0 Scratchpad Memory within the LFSS IP.
|
||||
*
|
||||
* The LFSS scratch pad memory is a 16- to 128-byte register based memory,
|
||||
* which will retain data similar to a non-volatile memory as long as VBAT is
|
||||
* supplied. The number of implemented bytes shall be configurable in a granularity
|
||||
* of 4 bytes. This means the scratch pad memory retains data when the main VDD supply
|
||||
* is lost or during the SHUTDOWN mode. However, the memory content won’t be retained,
|
||||
* when the VBAT domain itself is lost.
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup Scratchpad Memory
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_dl_scratchpad__include
|
||||
#define ti_dl_dl_scratchpad__include
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/driverlib/dl_lfss.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_SCRATCHPAD__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_SCRATCHPAD_MEM_WORD_0
|
||||
*/
|
||||
#define DL_SCRATCHPAD_MEM_WORD_0 DL_LFSS_SCRATCHPAD_MEM_WORD_0
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_SCRATCHPAD_MEM_WORD_1
|
||||
*/
|
||||
#define DL_SCRATCHPAD_MEM_WORD_1 DL_LFSS_SCRATCHPAD_MEM_WORD_1
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_SCRATCHPAD_MEM_WORD_1
|
||||
*/
|
||||
#define DL_SCRATCHPAD_MEM_WORD_1 DL_LFSS_SCRATCHPAD_MEM_WORD_1
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_SCRATCHPAD_MEM_WORD_2
|
||||
*/
|
||||
#define DL_SCRATCHPAD_MEM_WORD_2 DL_LFSS_SCRATCHPAD_MEM_WORD_2
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_SCRATCHPAD_MEM_WORD_3
|
||||
*/
|
||||
#define DL_SCRATCHPAD_MEM_WORD_3 DL_LFSS_SCRATCHPAD_MEM_WORD_3
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_SCRATCHPAD_MEM_WORD_4
|
||||
*/
|
||||
#define DL_SCRATCHPAD_MEM_WORD_4 DL_LFSS_SCRATCHPAD_MEM_WORD_4
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_SCRATCHPAD_MEM_WORD_5
|
||||
*/
|
||||
#define DL_SCRATCHPAD_MEM_WORD_5 DL_LFSS_SCRATCHPAD_MEM_WORD_5
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_SCRATCHPAD_MEM_WORD_6
|
||||
*/
|
||||
#define DL_SCRATCHPAD_MEM_WORD_6 DL_LFSS_SCRATCHPAD_MEM_WORD_6
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_SCRATCHPAD_MEM_WORD_7
|
||||
*/
|
||||
#define DL_SCRATCHPAD_MEM_WORD_7 DL_LFSS_SCRATCHPAD_MEM_WORD_7
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_SCRATCHPAD_MEM_BYTE_0
|
||||
*/
|
||||
#define DL_SCRATCHPAD_MEM_BYTE_0 DL_LFSS_SCRATCHPAD_MEM_BYTE_0
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_SCRATCHPAD_MEM_BYTE_1
|
||||
*/
|
||||
#define DL_SCRATCHPAD_MEM_BYTE_1 DL_LFSS_SCRATCHPAD_MEM_BYTE_1
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_SCRATCHPAD_MEM_BYTE_2
|
||||
*/
|
||||
#define DL_SCRATCHPAD_MEM_BYTE_2 DL_LFSS_SCRATCHPAD_MEM_BYTE_2
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_SCRATCHPAD_MEM_WORD_2
|
||||
*/
|
||||
#define DL_SCRATCHPAD_MEM_WORD_2 DL_LFSS_SCRATCHPAD_MEM_WORD_2
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_SCRATCHPAD_MEM_BYTE_3
|
||||
*/
|
||||
#define DL_SCRATCHPAD_MEM_BYTE_3 DL_LFSS_SCRATCHPAD_MEM_BYTE_3
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_writeScratchPadData32
|
||||
*/
|
||||
#define DL_ScratchPad_writeDataWord(lfss, memIndex, data) DL_LFSS_writeScratchPadData32(lfss, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_WORD)memIndex, \
|
||||
data)
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_writeScratchPadData8
|
||||
*/
|
||||
#define DL_ScratchPad_writeDataByte(lfss, memIndex, byteIndex, data) DL_LFSS_writeScratchPadData8(lfss, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_WORD)memIndex, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_BYTE)byteIndex, \
|
||||
data)
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_readScratchPadDataWord
|
||||
*/
|
||||
#define DL_ScratchPad_readDataWord(lfss, memIndex) DL_LFSS_readScratchPadDataWord(lfss, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_WORD)memIndex)
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_readScratchPadDataByte
|
||||
*/
|
||||
#define DL_ScratchPad_readDataByte(lfss, memIndex, byteIndex) DL_LFSS_readScratchPadDataByte(lfss, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_WORD)memIndex, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_BYTE)byteIndex)
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_enableScratchPadWriteProtectByte
|
||||
*/
|
||||
#define DL_ScratchPad_enableWriteProtectByte(lfss, memIndex, byteIndex) DL_LFSS_enableScratchPadWriteProtectByte(lfss, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_WORD)memIndex, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_BYTE)byteIndex)
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_isScratchPadWriteProtectByteEnabled
|
||||
*/
|
||||
#define DL_ScratchPad_isWriteProtectByteEnabled(lfss, memIndex, byteIndex) DL_LFSS_isScratchPadWriteProtectByteEnabled(lfss, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_WORD)memIndex, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_BYTE)byteIndex)
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_disableScratchPadWriteProtectByte
|
||||
*/
|
||||
#define DL_ScratchPad_disableWriteProtectByte(lfss, memIndex, byteIndex) DL_LFSS_disableScratchPadWriteProtectByte(lfss, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_WORD)memIndex, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_BYTE)byteIndex)
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_enableScratchPadTamperEraseByte
|
||||
*/
|
||||
#define DL_ScratchPad_enableTamperEraseByte(lfss, memIndex, byteIndex) DL_LFSS_enableScratchPadTamperEraseByte(lfss, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_WORD)memIndex, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_BYTE)byteIndex)
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_isScratchPadTamperEraseByteEnabled
|
||||
*/
|
||||
#define DL_ScratchPad_isTamperEraseByteEnabled(lfss, memIndex, byteIndex) DL_LFSS_isScratchPadTamperEraseByteEnabled(lfss, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_WORD)memIndex, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_BYTE)byteIndex)
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_disableScratchPadTamperEraseByte
|
||||
*/
|
||||
#define DL_ScratchPad_disableTamperEraseByte(lfss, memIndex, byteIndex) DL_LFSS_disableScratchPadTamperEraseByte(lfss, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_WORD)memIndex, \
|
||||
(DL_LFSS_SCRATCHPAD_MEM_BYTE)byteIndex)
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MSPM0_HAS_SCRATCHPAD__ */
|
||||
|
||||
#endif /* ti_dl_dl_scratchpad__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,320 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_spi.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_SPI__
|
||||
|
||||
void DL_SPI_init(SPI_Regs *spi, const DL_SPI_Config *config)
|
||||
{
|
||||
DL_Common_updateReg(&spi->CTL0,
|
||||
(uint32_t) config->chipSelectPin | (uint32_t) config->frameFormat |
|
||||
(uint32_t) config->dataSize,
|
||||
SPI_CTL0_CSSEL_MASK | SPI_CTL0_FRF_MASK | SPI_CTL0_SPO_MASK |
|
||||
SPI_CTL0_SPH_MASK | SPI_CTL0_DSS_MASK);
|
||||
|
||||
DL_Common_updateReg(&spi->CTL1,
|
||||
(uint32_t) config->parity | (uint32_t) config->bitOrder |
|
||||
(uint32_t) config->mode,
|
||||
SPI_CTL1_PES_MASK | SPI_CTL1_PREN_MASK | SPI_CTL1_PTEN_MASK |
|
||||
SPI_CTL1_MSB_MASK | SPI_CTL1_CP_MASK);
|
||||
}
|
||||
|
||||
void DL_SPI_setClockConfig(SPI_Regs *spi, const DL_SPI_ClockConfig *config)
|
||||
{
|
||||
spi->CLKSEL = (uint32_t) config->clockSel;
|
||||
|
||||
spi->CLKDIV = (uint32_t) config->divideRatio;
|
||||
}
|
||||
|
||||
void DL_SPI_getClockConfig(const SPI_Regs *spi, DL_SPI_ClockConfig *config)
|
||||
{
|
||||
config->clockSel = (DL_SPI_CLOCK) spi->CLKSEL;
|
||||
|
||||
config->divideRatio = (DL_SPI_CLOCK_DIVIDE_RATIO) spi->CLKDIV;
|
||||
}
|
||||
|
||||
uint8_t DL_SPI_receiveDataBlocking8(const SPI_Regs *spi)
|
||||
{
|
||||
while (DL_SPI_isRXFIFOEmpty(spi)) {
|
||||
};
|
||||
|
||||
return DL_SPI_receiveData8(spi);
|
||||
}
|
||||
|
||||
uint16_t DL_SPI_receiveDataBlocking16(const SPI_Regs *spi)
|
||||
{
|
||||
while (DL_SPI_isRXFIFOEmpty(spi)) {
|
||||
};
|
||||
return DL_SPI_receiveData16(spi);
|
||||
}
|
||||
|
||||
uint32_t DL_SPI_receiveDataBlocking32(const SPI_Regs *spi)
|
||||
{
|
||||
while (DL_SPI_isRXFIFOEmpty(spi)) {
|
||||
};
|
||||
return DL_SPI_receiveData32(spi);
|
||||
}
|
||||
|
||||
void DL_SPI_transmitDataBlocking8(SPI_Regs *spi, uint8_t data)
|
||||
{
|
||||
while (DL_SPI_isTXFIFOFull(spi)) {
|
||||
};
|
||||
DL_SPI_transmitData8(spi, data);
|
||||
}
|
||||
|
||||
void DL_SPI_transmitDataBlocking16(SPI_Regs *spi, uint16_t data)
|
||||
{
|
||||
while (DL_SPI_isTXFIFOFull(spi)) {
|
||||
};
|
||||
DL_SPI_transmitData16(spi, data);
|
||||
}
|
||||
|
||||
void DL_SPI_transmitDataBlocking32(SPI_Regs *spi, uint32_t data)
|
||||
{
|
||||
while (DL_SPI_isTXFIFOFull(spi)) {
|
||||
};
|
||||
DL_SPI_transmitData32(spi, data);
|
||||
}
|
||||
|
||||
bool DL_SPI_receiveDataCheck8(const SPI_Regs *spi, uint8_t *buffer)
|
||||
{
|
||||
bool status;
|
||||
if (DL_SPI_isRXFIFOEmpty(spi)) {
|
||||
status = false;
|
||||
} else {
|
||||
*buffer = DL_SPI_receiveData8(spi);
|
||||
status = true;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
bool DL_SPI_receiveDataCheck16(const SPI_Regs *spi, uint16_t *buffer)
|
||||
{
|
||||
bool status;
|
||||
if (DL_SPI_isRXFIFOEmpty(spi)) {
|
||||
status = false;
|
||||
} else {
|
||||
*buffer = DL_SPI_receiveData16(spi);
|
||||
status = true;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
bool DL_SPI_receiveDataCheck32(const SPI_Regs *spi, uint32_t *buffer)
|
||||
{
|
||||
bool status;
|
||||
if (DL_SPI_isRXFIFOEmpty(spi)) {
|
||||
status = false;
|
||||
} else {
|
||||
*buffer = DL_SPI_receiveData32(spi);
|
||||
status = true;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
bool DL_SPI_transmitDataCheck8(SPI_Regs *spi, uint8_t data)
|
||||
{
|
||||
bool status;
|
||||
if (DL_SPI_isTXFIFOFull(spi)) {
|
||||
status = false;
|
||||
} else {
|
||||
DL_SPI_transmitData8(spi, data);
|
||||
status = true;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
bool DL_SPI_transmitDataCheck16(SPI_Regs *spi, uint16_t data)
|
||||
{
|
||||
bool status;
|
||||
if (DL_SPI_isTXFIFOFull(spi)) {
|
||||
status = false;
|
||||
} else {
|
||||
DL_SPI_transmitData16(spi, data);
|
||||
status = true;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
bool DL_SPI_transmitDataCheck32(SPI_Regs *spi, uint32_t data)
|
||||
{
|
||||
bool status;
|
||||
if (DL_SPI_isTXFIFOFull(spi)) {
|
||||
status = false;
|
||||
} else {
|
||||
DL_SPI_transmitData32(spi, data);
|
||||
status = true;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
uint32_t DL_SPI_drainRXFIFO8(
|
||||
const SPI_Regs *spi, uint8_t *buffer, uint32_t maxCount)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0; i < maxCount; i++) {
|
||||
if (!DL_SPI_isRXFIFOEmpty(spi)) {
|
||||
buffer[i] = DL_SPI_receiveData8(spi);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
uint32_t DL_SPI_drainRXFIFO16(
|
||||
const SPI_Regs *spi, uint16_t *buffer, uint32_t maxCount)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0; i < maxCount; i++) {
|
||||
if (!DL_SPI_isRXFIFOEmpty(spi)) {
|
||||
buffer[i] = DL_SPI_receiveData16(spi);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
uint32_t DL_SPI_drainRXFIFO32(
|
||||
const SPI_Regs *spi, uint32_t *buffer, uint32_t maxCount)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0; i < maxCount; i++) {
|
||||
if (!DL_SPI_isRXFIFOEmpty(spi)) {
|
||||
buffer[i] = DL_SPI_receiveData32(spi);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
uint32_t DL_SPI_fillTXFIFO8(
|
||||
SPI_Regs *spi, const uint8_t *buffer, uint32_t count)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0; i < count; i++) {
|
||||
if (!DL_SPI_isTXFIFOFull(spi)) {
|
||||
DL_SPI_transmitData8(spi, buffer[i]);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
uint32_t DL_SPI_fillTXFIFO16(
|
||||
SPI_Regs *spi, const uint16_t *buffer, uint32_t count)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0; i < count; i++) {
|
||||
if (!DL_SPI_isTXFIFOFull(spi)) {
|
||||
DL_SPI_transmitData16(spi, buffer[i]);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
bool DL_SPI_saveConfiguration(const SPI_Regs *spi, DL_SPI_backupConfig *ptr)
|
||||
{
|
||||
bool stateSaved = !ptr->backupRdy;
|
||||
if (stateSaved) {
|
||||
ptr->controlWord0 = spi->CTL0;
|
||||
ptr->controlWord1 = spi->CTL1;
|
||||
ptr->clockControl = spi->CLKCTL;
|
||||
ptr->clockSel = spi->CLKSEL;
|
||||
ptr->divideRatio = spi->CLKDIV;
|
||||
ptr->interruptFifoLevelSelectWord = spi->IFLS;
|
||||
ptr->interruptMask0 = spi->CPU_INT.IMASK;
|
||||
ptr->interruptMask1 = spi->DMA_TRIG_RX.IMASK;
|
||||
ptr->interruptMask2 = spi->DMA_TRIG_TX.IMASK;
|
||||
ptr->backupRdy = true;
|
||||
}
|
||||
return stateSaved;
|
||||
}
|
||||
|
||||
bool DL_SPI_restoreConfiguration(SPI_Regs *spi, DL_SPI_backupConfig *ptr)
|
||||
{
|
||||
bool stateRestored = ptr->backupRdy;
|
||||
if (stateRestored) {
|
||||
/* Set CTL1.ENABLE=0 during initialization */
|
||||
spi->CTL1 = ptr->controlWord1 & ~(SPI_CTL1_ENABLE_MASK);
|
||||
spi->CTL0 = ptr->controlWord0;
|
||||
spi->CLKCTL = ptr->clockControl;
|
||||
spi->CLKSEL = ptr->clockSel;
|
||||
spi->CLKDIV = ptr->divideRatio;
|
||||
spi->IFLS = ptr->interruptFifoLevelSelectWord;
|
||||
spi->CPU_INT.IMASK = ptr->interruptMask0;
|
||||
spi->DMA_TRIG_RX.IMASK = ptr->interruptMask1;
|
||||
spi->DMA_TRIG_TX.IMASK = ptr->interruptMask2;
|
||||
|
||||
/* Re-enable SPI if it was originally enabled */
|
||||
if ((ptr->controlWord1 & SPI_CTL1_ENABLE_MASK) ==
|
||||
SPI_CTL1_ENABLE_MASK) {
|
||||
DL_SPI_enable(spi);
|
||||
}
|
||||
ptr->backupRdy = false;
|
||||
}
|
||||
return stateRestored;
|
||||
}
|
||||
|
||||
uint32_t DL_SPI_fillTXFIFO32(
|
||||
SPI_Regs *spi, const uint32_t *buffer, uint32_t count)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0; i < count; i++) {
|
||||
if (!DL_SPI_isTXFIFOFull(spi)) {
|
||||
DL_SPI_transmitData32(spi, buffer[i]);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_SPI__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2025, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_tamperio.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_TIO__
|
||||
#endif /* __MSPM0_HAS_TIO__ */
|
||||
@@ -0,0 +1,828 @@
|
||||
/*
|
||||
* Copyright (c) 2023, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_tamperio.h
|
||||
* @brief Tamper Input/Output (TIO) Driver Library
|
||||
* @defgroup Tamper Input/Output (TIO)
|
||||
*
|
||||
* @anchor ti_dl_dl_tio_Overview
|
||||
* # Overview
|
||||
*
|
||||
* The tamper I/O is a GPIO which is sourced by the VBAT power domain.
|
||||
* The LFSS IP will contain up to 16 I/O’s of this type. The I/O’s have two modes of operation.
|
||||
* In IOMUX mode the tamper I/O input and output path are connected to the SoC IOMUX module
|
||||
* and the I/O’s can be used as a 2nd function like SPI, UART or Timer PWM. The second mode is
|
||||
* the Tamper mode. In this mode the I/O is completely controlled by the LFSS IP and will remain
|
||||
* functional during the power loss of the main supply or during SHUTDOWN mode.
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup TAMPERIO
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_dl_tio__include
|
||||
#define ti_dl_dl_tio__include
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/driverlib/dl_lfss.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_TIO__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_0
|
||||
*/
|
||||
#define DL_TAMPERIO_0 DL_LFSS_TAMPERIO_0
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_1
|
||||
*/
|
||||
#define DL_TAMPERIO_1 DL_LFSS_TAMPERIO_1
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_2
|
||||
*/
|
||||
#define DL_TAMPERIO_2 DL_LFSS_TAMPERIO_2
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_3
|
||||
*/
|
||||
#define DL_TAMPERIO_3 DL_LFSS_TAMPERIO_3
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_4
|
||||
*/
|
||||
#define DL_TAMPERIO_4 DL_LFSS_TAMPERIO_4
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_5
|
||||
*/
|
||||
#define DL_TAMPERIO_5 DL_LFSS_TAMPERIO_5
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_6
|
||||
*/
|
||||
#define DL_TAMPERIO_6 DL_LFSS_TAMPERIO_6
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_7
|
||||
*/
|
||||
#define DL_TAMPERIO_7 DL_LFSS_TAMPERIO_7
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_8
|
||||
*/
|
||||
#define DL_TAMPERIO_8 DL_LFSS_TAMPERIO_8
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_9
|
||||
*/
|
||||
#define DL_TAMPERIO_9 DL_LFSS_TAMPERIO_9
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_10
|
||||
*/
|
||||
#define DL_TAMPERIO_10 DL_LFSS_TAMPERIO_10
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_11
|
||||
*/
|
||||
#define DL_TAMPERIO_11 DL_LFSS_TAMPERIO_11
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_12
|
||||
*/
|
||||
#define DL_TAMPERIO_12 DL_LFSS_TAMPERIO_12
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_13
|
||||
*/
|
||||
#define DL_TAMPERIO_13 DL_LFSS_TAMPERIO_13
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_14
|
||||
*/
|
||||
#define DL_TAMPERIO_14 DL_LFSS_TAMPERIO_14
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_15
|
||||
*/
|
||||
#define DL_TAMPERIO_15 DL_LFSS_TAMPERIO_15
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_VALUE_0
|
||||
*/
|
||||
#define DL_TAMPERIO_VALUE_0 DL_LFSS_TAMPERIO_VALUE_0
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_VALUE_1
|
||||
*/
|
||||
#define DL_TAMPERIO_VALUE_1 DL_LFSS_TAMPERIO_VALUE_1
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_0
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_0 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_0
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_1
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_1 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_1
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_2
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_2 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_2
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_3
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_3 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_3
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_4
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_4 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_4
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_5
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_5 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_5
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_6
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_6 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_6
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_7
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_7 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_8
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_8
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_8 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_8
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_9
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_9 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_9
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_10
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_10 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_10
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_11
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_11 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_11
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_12
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_12 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_12
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_13
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_13 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_13
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_14
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_14 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_14
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_15
|
||||
*/
|
||||
#define DL_TAMPERIO_INTERRUPT_TAMPERIO_15 DL_LFSS_TAMPERIO_INTERRUPT_TAMPERIO_15
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_0
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_0 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_0
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_1
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_1 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_1
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_2
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_2 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_2
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_3
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_3 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_3
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_4
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_4 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_4
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_5
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_5 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_5
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_6
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_6 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_6
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_7
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_7 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_8
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_8
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_8 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_8
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_9
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_9 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_9
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_10
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_10 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_10
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_11
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_11 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_11
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_12
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_12 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_12
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_13
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_13 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_13
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_14
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_14 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_14
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EVENT_TAMPERIO_15
|
||||
*/
|
||||
#define DL_TAMPERIO_EVENT_TAMPERIO_15 DL_LFSS_TAMPERIO_EVENT_TAMPERIO_15
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_0
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_0 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_0
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_1
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_1 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_1
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_2
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_2 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_2
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_3
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_3 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_3
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_4
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_4 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_4
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_5
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_5 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_5
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_6
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_6 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_6
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_7
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_7 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_7
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_8
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_8 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_8
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_9
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_9 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_9
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_10
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_10 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_10
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_11
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_11 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_11
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_12
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_12 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_12
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_13
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_13 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_13
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_14
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_14 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_14
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_15
|
||||
*/
|
||||
#define DL_TAMPERIO_IIDX_TAMPER_IO_15 DL_LFSS_TAMPERIO_IIDX_TAMPER_IO_15
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_OUTPUT_SOURCE_TOUT
|
||||
*/
|
||||
#define DL_TAMPERIO_OUTPUT_SOURCE_TOUT DL_LFSS_TAMPERIO_OUTPUT_SOURCE_TOUT
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_OUTPUT_SOURCE_LFCLK
|
||||
*/
|
||||
#define DL_TAMPERIO_OUTPUT_SOURCE_LFCLK DL_LFSS_TAMPERIO_OUTPUT_SOURCE_LFCLK
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_OUTPUT_SOURCE_HEARTBEAT
|
||||
*/
|
||||
#define DL_TAMPERIO_OUTPUT_SOURCE_HEARTBEAT DL_LFSS_TAMPERIO_OUTPUT_SOURCE_HEARTBEAT
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_OUTPUT_SOURCE_TIME_STAMP_EVENT
|
||||
*/
|
||||
#define DL_TAMPERIO_OUTPUT_SOURCE_TIME_STAMP_EVENT DL_LFSS_TAMPERIO_OUTPUT_SOURCE_TIME_STAMP_EVENT
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH_NONE
|
||||
*/
|
||||
#define DL_TAMPERIO_GLITCH_FILTER_WIDTH_NONE DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH_NONE
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH_30_USEC
|
||||
*/
|
||||
#define DL_TAMPERIO_GLITCH_FILTER_WIDTH_30_USEC DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH_30_USEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH_100_USEC
|
||||
*/
|
||||
#define DL_TAMPERIO_GLITCH_FILTER_WIDTH_100_USEC DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH_100_USEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH_200_USEC
|
||||
*/
|
||||
#define DL_TAMPERIO_GLITCH_FILTER_WIDTH_200_USEC DL_LFSS_TAMPERIO_GLITCH_FILTER_WIDTH_200_USEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY_DISABLE
|
||||
*/
|
||||
#define DL_TAMPERIO_EDGE_DETECTION_POLARITY_DISABLE DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY_DISABLE
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY_RISE
|
||||
*/
|
||||
#define DL_TAMPERIO_EDGE_DETECTION_POLARITY_RISE DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY_RISE
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY_FALL
|
||||
*/
|
||||
#define DL_TAMPERIO_EDGE_DETECTION_POLARITY_FALL DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY_FALL
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY_BOTH
|
||||
*/
|
||||
#define DL_TAMPERIO_EDGE_DETECTION_POLARITY_BOTH DL_LFSS_TAMPERIO_EDGE_DETECTION_POLARITY_BOTH
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_MODE_IOMUX
|
||||
*/
|
||||
#define DL_TAMPERIO_MODE_TAMPER DL_LFSS_TAMPERIO_MODE_TAMPER
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TAMPERIO_MODE_IOMUX
|
||||
*/
|
||||
#define DL_TAMPERIO_MODE_IOMUX DL_LFSS_TAMPERIO_MODE_IOMUX
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_INTERVAL_0_125_SEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_INTERVAL_0_125_SEC DL_LFSS_HEARTBEAT_INTERVAL_0_125_SEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_INTERVAL_0_25_SEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_INTERVAL_0_25_SEC DL_LFSS_HEARTBEAT_INTERVAL_0_25_SEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_INTERVAL_05_SEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_INTERVAL_05_SEC DL_LFSS_HEARTBEAT_INTERVAL_05_SEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_INTERVAL_1_SEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_INTERVAL_1_SEC DL_LFSS_HEARTBEAT_INTERVAL_1_SEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_INTERVAL_2_SEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_INTERVAL_2_SEC DL_LFSS_HEARTBEAT_INTERVAL_2_SEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_INTERVAL_4_SEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_INTERVAL_4_SEC DL_LFSS_HEARTBEAT_INTERVAL_4_SEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_INTERVAL_8_SEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_INTERVAL_8_SEC DL_LFSS_HEARTBEAT_INTERVAL_8_SEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_INTERVAL_16_SEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_INTERVAL_16_SEC DL_LFSS_HEARTBEAT_INTERVAL_16_SEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_PULSE_WIDTH_1_MSEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_PULSE_WIDTH_1_MSEC DL_LFSS_HEARTBEAT_PULSE_WIDTH_1_MSEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_PULSE_WIDTH_2_MSEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_PULSE_WIDTH_2_MSEC DL_LFSS_HEARTBEAT_PULSE_WIDTH_2_MSEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_PULSE_WIDTH_4_MSEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_PULSE_WIDTH_4_MSEC DL_LFSS_HEARTBEAT_PULSE_WIDTH_4_MSEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_PULSE_WIDTH_8_MSEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_PULSE_WIDTH_8_MSEC DL_LFSS_HEARTBEAT_PULSE_WIDTH_8_MSEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_PULSE_WIDTH_16_MSEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_PULSE_WIDTH_16_MSEC DL_LFSS_HEARTBEAT_PULSE_WIDTH_16_MSEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_PULSE_WIDTH_32_MSEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_PULSE_WIDTH_32_MSEC DL_LFSS_HEARTBEAT_PULSE_WIDTH_32_MSEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_PULSE_WIDTH_64_MSEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_PULSE_WIDTH_64_MSEC DL_LFSS_HEARTBEAT_PULSE_WIDTH_64_MSEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_PULSE_WIDTH_128_MSEC
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_PULSE_WIDTH_128_MSEC DL_LFSS_HEARTBEAT_PULSE_WIDTH_128_MSEC
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_MODE_DISABLED
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_MODE_DISABLED DL_LFSS_HEARTBEAT_MODE_DISABLED
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_MODE_ALWAYS_ON
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_MODE_ALWAYS_ON DL_LFSS_HEARTBEAT_MODE_ALWAYS_ON
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_MODE_TIME_STAMP
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_MODE_TIME_STAMP DL_LFSS_HEARTBEAT_MODE_TIME_STAMP
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_HEARTBEAT_MODE_POWER_FAIL
|
||||
*/
|
||||
#define DL_TAMPERIO_HEARTBEAT_MODE_POWER_FAIL DL_LFSS_HEARTBEAT_MODE_POWER_FAIL
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_enableOutputInversion
|
||||
*/
|
||||
#define DL_TamperIO_enableOutputInversion DL_LFSS_TamperIO_enableOutputInversion
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_isOutputInversionEnabled
|
||||
*/
|
||||
#define DL_TamperIO_isOutputInversionEnabled DL_LFSS_TamperIO_isOutputInversionEnabled
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_disableOutputInversion
|
||||
*/
|
||||
#define DL_TamperIO_disableOutputInversion DL_LFSS_TamperIO_disableOutputInversion
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_setOutputSource
|
||||
*/
|
||||
#define DL_TamperIO_setOutputSource DL_LFSS_TamperIO_setOutputSource
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getOutputSource
|
||||
*/
|
||||
#define DL_TamperIO_getOutputSource DL_LFSS_TamperIO_getOutputSource
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_setGlitchFilterWidth
|
||||
*/
|
||||
#define DL_TamperIO_setGlitchFilterWidth DL_LFSS_TamperIO_setGlitchFilterWidth
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getGlitchFilterWidth
|
||||
*/
|
||||
#define DL_TamperIO_getGlitchFilterWidth DL_LFSS_TamperIO_getGlitchFilterWidth
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_setEdgeDetectionPolarity
|
||||
*/
|
||||
#define DL_TamperIO_setEdgeDetectionPolarity DL_LFSS_TamperIO_setEdgeDetectionPolarity
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getEdgeDetectionPolarity
|
||||
*/
|
||||
#define DL_TamperIO_getEdgeDetectionPolarity DL_LFSS_TamperIO_getEdgeDetectionPolarity
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_enableInternalPullUp
|
||||
*/
|
||||
#define DL_TamperIO_enableInternalPullUp DL_LFSS_TamperIO_enableInternalPullUp
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_isInternalPullUpEnabled
|
||||
*/
|
||||
#define DL_TamperIO_isInternalPullUpEnabled DL_LFSS_TamperIO_isInternalPullUpEnabled
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_disableInternalPullUp
|
||||
*/
|
||||
#define DL_TamperIO_disableInternalPullUp DL_LFSS_TamperIO_disableInternalPullUp
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_enableInternalPullDown
|
||||
*/
|
||||
#define DL_TamperIO_enableInternalPullDown DL_LFSS_TamperIO_enableInternalPullDown
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_isInternalPullDownEnabled
|
||||
*/
|
||||
#define DL_TamperIO_isInternalPullDownEnabled DL_LFSS_TamperIO_isInternalPullDownEnabled
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_disableInternalPullDown
|
||||
*/
|
||||
#define DL_TamperIO_disableInternalPullDown DL_LFSS_TamperIO_disableInternalPullDown
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_enableInput
|
||||
*/
|
||||
#define DL_TamperIO_enableInput DL_LFSS_TamperIO_enableInput
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_isInputEnabled
|
||||
*/
|
||||
#define DL_TamperIO_isInputEnabled DL_LFSS_TamperIO_isInputEnabled
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_disableInput
|
||||
*/
|
||||
#define DL_TamperIO_disableInput DL_LFSS_TamperIO_disableInput
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_setMode
|
||||
*/
|
||||
#define DL_TamperIO_setMode DL_LFSS_TamperIO_setMode
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getMode
|
||||
*/
|
||||
#define DL_TamperIO_getMode DL_LFSS_TamperIO_getMode
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_enableOutput
|
||||
*/
|
||||
#define DL_TamperIO_enableOutput DL_LFSS_TamperIO_enableOutput
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_disableOutput
|
||||
*/
|
||||
#define DL_TamperIO_disableOutput DL_LFSS_TamperIO_disableOutput
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_isOutputEnabled
|
||||
*/
|
||||
#define DL_TamperIO_isOutputEnabled DL_LFSS_TamperIO_isOutputEnabled
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_setOutputValue
|
||||
*/
|
||||
#define DL_TamperIO_setOutputValue DL_LFSS_TamperIO_setOutputValue
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getOutputValue
|
||||
*/
|
||||
#define DL_TamperIO_getOutputValue DL_LFSS_TamperIO_getOutputValue
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getInputValue
|
||||
*/
|
||||
#define DL_TamperIO_getInputValue DL_LFSS_TamperIO_getInputValue
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_setHeartBeatInterval
|
||||
*/
|
||||
#define DL_TamperIO_setHeartBeatInterval DL_LFSS_TamperIO_setHeartBeatInterval
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getHeartBeatInterval
|
||||
*/
|
||||
#define DL_TamperIO_getHeartBeatInterval DL_LFSS_TamperIO_getHeartBeatInterval
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_setHeartBeatPulseWidth
|
||||
*/
|
||||
#define DL_TamperIO_setHeartBeatPulseWidth DL_LFSS_TamperIO_setHeartBeatPulseWidth
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getHeartBeatPulseWidth
|
||||
*/
|
||||
#define DL_TamperIO_getHeartBeatPulseWidth DL_LFSS_TamperIO_getHeartBeatPulseWidth
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_setHeartBeatMode
|
||||
*/
|
||||
#define DL_TamperIO_setHeartBeatMode DL_LFSS_TamperIO_setHeartBeatMode
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getHeartBeatMode
|
||||
*/
|
||||
#define DL_TamperIO_getHeartBeatMode DL_LFSS_TamperIO_getHeartBeatMode
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_enableWriteProtectLock
|
||||
*/
|
||||
#define DL_TamperIO_enableWriteProtectLock DL_LFSS_TamperIO_enableWriteProtectLock
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_isWriteProtectLockEnabled
|
||||
*/
|
||||
#define DL_TamperIO_isWriteProtectLockEnabled DL_LFSS_TamperIO_isWriteProtectLockEnabled
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_disableWriteProtectLock
|
||||
*/
|
||||
#define DL_TamperIO_disableWriteProtectLock DL_LFSS_TamperIO_disableWriteProtectLock
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_enableInterrupt
|
||||
*/
|
||||
#define DL_TamperIO_enableInterrupt DL_LFSS_TamperIO_enableInterrupt
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_enableInterrupt
|
||||
*/
|
||||
#define DL_TamperIO_disableInterrupt DL_LFSS_TamperIO_disableInterrupt
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getEnabledInterrupts
|
||||
*/
|
||||
#define DL_TamperIO_getEnabledInterrupts DL_LFSS_TamperIO_getEnabledInterrupts
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getEnabledInterruptStatus
|
||||
*/
|
||||
#define DL_TamperIO_getEnabledInterruptStatus DL_LFSS_TamperIO_getEnabledInterruptStatus
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getRawInterruptStatus
|
||||
*/
|
||||
#define DL_TamperIO_getRawInterruptStatus DL_LFSS_TamperIO_getRawInterruptStatus
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getPendingInterrupt
|
||||
*/
|
||||
#define DL_TamperIO_getPendingInterrupt DL_LFSS_TamperIO_getPendingInterrupt
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_clearInterruptStatus
|
||||
*/
|
||||
#define DL_TamperIO_clearInterruptStatus DL_LFSS_TamperIO_clearInterruptStatus
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_enableEvent
|
||||
*/
|
||||
#define DL_TamperIO_enableEvent DL_LFSS_TamperIO_enableEvent
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_disableEvent
|
||||
*/
|
||||
#define DL_TamperIO_disableEvent DL_LFSS_TamperIO_disableEvent
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getEnabledEvents
|
||||
*/
|
||||
#define DL_TamperIO_getEnabledEvents DL_LFSS_TamperIO_getEnabledEvents
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getEnabledEventStatus
|
||||
*/
|
||||
#define DL_TamperIO_getEnabledEventStatus DL_LFSS_TamperIO_getEnabledEventStatus
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getRawEventsStatus
|
||||
*/
|
||||
#define DL_TamperIO_getRawEventsStatus DL_LFSS_TamperIO_getRawEventsStatus
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_clearEventsStatus
|
||||
*/
|
||||
#define DL_TamperIO_clearEventsStatus DL_LFSS_TamperIO_clearEventsStatus
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_setPublisherChanID
|
||||
*/
|
||||
#define DL_TamperIO_setPublisherChanID DL_LFSS_TamperIO_setPublisherChanID
|
||||
|
||||
/*!
|
||||
* @brief Redirects to common @ref DL_LFSS_TamperIO_getPublisherChanID
|
||||
*/
|
||||
#define DL_TamperIO_getPublisherChanID DL_LFSS_TamperIO_getPublisherChanID
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MSPM0_HAS_TIO__ */
|
||||
|
||||
#endif /* ti_dl_dl_tio__include */
|
||||
/** @}*/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2025, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_timera.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_TIMER_A__
|
||||
#endif /* __MSPM0_HAS_TIMER_A__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2025, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_timerg.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_TIMER_G__
|
||||
#endif /* __MSPM0_HAS_TIMER_G__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_trng.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_TRNG__
|
||||
|
||||
bool DL_TRNG_saveConfiguration(
|
||||
const TRNG_Regs *trng, DL_TRNG_backupConfig *ptr)
|
||||
{
|
||||
bool stateSaved = !ptr->backupRdy;
|
||||
if (stateSaved) {
|
||||
ptr->controlWord = trng->CTL;
|
||||
ptr->clockDivider = trng->CLKDIVIDE;
|
||||
ptr->interruptMask = trng->CPU_INT.IMASK;
|
||||
ptr->backupRdy = true;
|
||||
}
|
||||
return stateSaved;
|
||||
}
|
||||
|
||||
bool DL_TRNG_restoreConfiguration(TRNG_Regs *trng, DL_TRNG_backupConfig *ptr)
|
||||
{
|
||||
bool stateRestored = ptr->backupRdy;
|
||||
if (stateRestored) {
|
||||
DL_Common_updateReg(
|
||||
&trng->CTL, ptr->controlWord, TRNG_CTL_DECIM_RATE_MASK);
|
||||
trng->CLKDIVIDE = ptr->clockDivider;
|
||||
trng->CPU_INT.IMASK = ptr->interruptMask;
|
||||
|
||||
/* If TRNG was originally in OFF state, then send PWROFF command */
|
||||
if (((ptr->controlWord & TRNG_STAT_FSM_STATE_MASK) >>
|
||||
TRNG_STAT_FSM_STATE_OFS) == (uint32_t) DL_TRNG_STATE_OFF) {
|
||||
DL_TRNG_sendCommand(trng, DL_TRNG_CMD_PWROFF);
|
||||
}
|
||||
|
||||
ptr->backupRdy = false;
|
||||
}
|
||||
return stateRestored;
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_TRNG__ */
|
||||
@@ -0,0 +1,684 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_trng.h
|
||||
* @brief True Random Number Generator (TRNG) Driver Library
|
||||
* @defgroup TRNG True Random Number Generator (TRNG)
|
||||
*
|
||||
* @anchor ti_dl_dl_m0p_trng_Overview
|
||||
* # Overview
|
||||
*
|
||||
* The True Random Number Generator Driver Library allows full configuration of
|
||||
* the MSPM0 TRNG module.
|
||||
* The true random number generator (TRNG) block is an entropy source which
|
||||
* can be used to generate random bit sequences.
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup TRNG
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_dl_trng__include
|
||||
#define ti_dl_dl_trng__include
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
#include <ti/driverlib/dl_common.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_TRNG__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/** @addtogroup DL_TRNG_INTERRUPT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief TRNG interrupt definition for health test failed
|
||||
*/
|
||||
#define DL_TRNG_INTERRUPT_HEALTH_FAIL_EVENT (TRNG_IMASK_IRQ_HEALTH_FAIL_MASK)
|
||||
|
||||
/*!
|
||||
* @brief TRNG interrupt definition for commafnd done
|
||||
*/
|
||||
#define DL_TRNG_INTERRUPT_CMD_DONE_EVENT (TRNG_IMASK_IRQ_CMD_DONE_MASK)
|
||||
|
||||
/*!
|
||||
* @brief TRNG interrupt definition for command fail
|
||||
*/
|
||||
#define DL_TRNG_INTERRUPT_CMD_FAIL_EVENT (TRNG_IMASK_IRQ_CMD_FAIL_MASK)
|
||||
|
||||
/*!
|
||||
* @brief TRNG interrupt definition for capture ready
|
||||
*/
|
||||
#define DL_TRNG_INTERRUPT_CAPTURE_RDY_EVENT (TRNG_IMASK_IRQ_CAPTURED_RDY_MASK)
|
||||
/** @}*/
|
||||
|
||||
/** @addtogroup DL_TRNG_HEALTH_TEST_SUCCESS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief TRNG Digital health test success value
|
||||
*/
|
||||
#define DL_TRNG_DIGITAL_HEALTH_TEST_SUCCESS (0xFF)
|
||||
|
||||
/*!
|
||||
* @brief TRNG Analog health test success value
|
||||
*/
|
||||
#define DL_TRNG_ANALOG_HEALTH_TEST_SUCCESS (0x1)
|
||||
/** @}*/
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
/*! @enum DL_TRNG_IIDX */
|
||||
typedef enum {
|
||||
/*! TRNG interrupt index for health fail */
|
||||
DL_TRNG_IIDX_HEALTH_FAIL = TRNG_IIDX_STAT_IRQ_HEALTH_FAIL,
|
||||
/*! TRNG interrupt index for command done */
|
||||
DL_TRNG_IIDX_CMD_DONE = TRNG_IIDX_STAT_IRQ_CMD_DONE,
|
||||
/*! TRNG interrupt index for command fail */
|
||||
DL_TRNG_IIDX_CMD_FAIL = TRNG_IIDX_STAT_IRQ_CMD_FAIL,
|
||||
/*! TRNG interrupt index indicating the capture buffer is ready */
|
||||
DL_TRNG_IIDX_CAPTURED_READY = TRNG_IIDX_STAT_IRQ_CAPTURED_RDY,
|
||||
} DL_TRNG_IIDX;
|
||||
|
||||
/*! @enum DL_TRNG_DECIMATION_RATE */
|
||||
typedef enum {
|
||||
/*! Decimation by 1 (no decimation) */
|
||||
DL_TRNG_DECIMATION_RATE_1 = 0x0,
|
||||
/*! Decimation rate 2 -- take every other sample */
|
||||
DL_TRNG_DECIMATION_RATE_2 = 0x1,
|
||||
/*! Decimation rate 3 -- take every third sample */
|
||||
DL_TRNG_DECIMATION_RATE_3 = 0x2,
|
||||
/*! Decimation rate 4 -- take every fourth sample */
|
||||
DL_TRNG_DECIMATION_RATE_4 = 0x3,
|
||||
/*! Decimation rate 5 -- take every fifth sample */
|
||||
DL_TRNG_DECIMATION_RATE_5 = 0x4,
|
||||
/*! Decimation rate 6 -- take every sixth sample */
|
||||
DL_TRNG_DECIMATION_RATE_6 = 0x5,
|
||||
/*! Decimation rate 7 -- take every seventh sample */
|
||||
DL_TRNG_DECIMATION_RATE_7 = 0x6,
|
||||
/*! Decimation rate 8 -- take every eighth sample */
|
||||
DL_TRNG_DECIMATION_RATE_8 = 0x7,
|
||||
} DL_TRNG_DECIMATION_RATE;
|
||||
|
||||
/*! @enum DL_TRNG_CMD */
|
||||
typedef enum {
|
||||
/*! TRNG command to power off analog blocks and digital blocks are gated */
|
||||
DL_TRNG_CMD_PWROFF = TRNG_CTL_CMD_PWR_OFF,
|
||||
/*! TRNG command to execute digital power-on self-tests */
|
||||
DL_TRNG_CMD_TEST_DIG = TRNG_CTL_CMD_PWRUP_DIG,
|
||||
/*! TRNG command to execute digital power-on self-tests */
|
||||
DL_TRNG_CMD_TEST_ANA = TRNG_CTL_CMD_PWRUP_ANA,
|
||||
/*! TRNG command to go into normal operating mode */
|
||||
DL_TRNG_CMD_NORM_FUNC = TRNG_CTL_CMD_NORM_FUNC,
|
||||
} DL_TRNG_CMD;
|
||||
|
||||
/*! @enum DL_TRNG_CLOCK_DIVIDE */
|
||||
typedef enum {
|
||||
/*! Clock divide by 1 */
|
||||
DL_TRNG_CLOCK_DIVIDE_1 = TRNG_CLKDIVIDE_RATIO_DIV_BY_1,
|
||||
/*! Clock divide by 2 */
|
||||
DL_TRNG_CLOCK_DIVIDE_2 = TRNG_CLKDIVIDE_RATIO_DIV_BY_2,
|
||||
/*! Clock divide by 4 */
|
||||
DL_TRNG_CLOCK_DIVIDE_4 = TRNG_CLKDIVIDE_RATIO_DIV_BY_4,
|
||||
/*! Clock divide by 6 */
|
||||
DL_TRNG_CLOCK_DIVIDE_6 = TRNG_CLKDIVIDE_RATIO_DIV_BY_6,
|
||||
/*! Clock divide by 8 */
|
||||
DL_TRNG_CLOCK_DIVIDE_8 = TRNG_CLKDIVIDE_RATIO_DIV_BY_8,
|
||||
} DL_TRNG_CLOCK_DIVIDE;
|
||||
|
||||
/*! @enum DL_TRNG_STATE */
|
||||
typedef enum {
|
||||
/*! Current state of the TRNG is OFF */
|
||||
DL_TRNG_STATE_OFF = 0x0,
|
||||
/*! Current state of the TRNG is PWRUP_ES */
|
||||
DL_TRNG_STATE_PWRUP_ES = 0x1,
|
||||
/*! Current state of the TRNG is NORM_FUNC */
|
||||
DL_TRNG_STATE_NORM_FUNC = 0x3,
|
||||
/*! Current state of the TRNG is TEST_DIG */
|
||||
DL_TRNG_STATE_TEST_DIG = 0x7,
|
||||
/*! Current state of the TRNG is TEST_ANA */
|
||||
DL_TRNG_STATE_TEST_ANA = 0xB,
|
||||
/*! Current state of the TRNG is ERROR */
|
||||
DL_TRNG_STATE_ERROR = 0xA,
|
||||
/*! Current state of the TRNG is PWRDOWN_ES */
|
||||
DL_TRNG_STATE_PWRDOWN = 0x2,
|
||||
} DL_TRNG_STATE;
|
||||
|
||||
/**
|
||||
* @brief Configuration structure to backup TRNG peripheral state before
|
||||
* going to STOP/STANDBY mode. Used by @ref DL_TRNG_saveConfiguration
|
||||
*/
|
||||
typedef struct {
|
||||
/*! TRNG control word. Combination of @ref DL_TRNG_DECIMATION_RATE and
|
||||
* @ref DL_TRNG_CMD */
|
||||
uint32_t controlWord;
|
||||
/*! TRNG clock divider. Must be one of @ref DL_TRNG_CLOCK_DIVIDE */
|
||||
uint32_t clockDivider;
|
||||
/*! TRNG interrupt status. Must be one of @ref DL_TRNG_IIDX */
|
||||
uint32_t interruptMask;
|
||||
/*! Boolean flag indicating whether or not a valid configuration structure
|
||||
exists. Should not be modified by the user. */
|
||||
bool backupRdy;
|
||||
} DL_TRNG_backupConfig;
|
||||
|
||||
/**
|
||||
* @brief Enables the Peripheral Write Enable (PWREN) register for the TRNG
|
||||
*
|
||||
* Before any peripheral registers can be configured by software, the
|
||||
* peripheral itself must be enabled by writing the ENABLE bit together with
|
||||
* the appropriate KEY value to the peripheral's PWREN register.
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_TRNG_enablePower(TRNG_Regs *trng)
|
||||
{
|
||||
trng->GPRCM.PWREN = TRNG_PWREN_KEY_UNLOCK_W | TRNG_PWREN_ENABLE_ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Peripheral Write Enable (PWREN) register for the TRNG
|
||||
*
|
||||
* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
|
||||
* accessible for read/write operations.
|
||||
*
|
||||
* @note This API does not provide large power savings.
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_TRNG_disablePower(TRNG_Regs *trng)
|
||||
{
|
||||
trng->GPRCM.PWREN = TRNG_PWREN_KEY_UNLOCK_W | TRNG_PWREN_ENABLE_DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if the Peripheral Write Enable (PWREN) register for the TRNG
|
||||
* is enabled
|
||||
*
|
||||
* Before any peripheral registers can be configured by software, the
|
||||
* peripheral itself must be enabled by writing the ENABLE bit together with
|
||||
* the appropriate KEY value to the peripheral's PWREN register.
|
||||
*
|
||||
* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
|
||||
* accessible for read/write operations.
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return true if peripheral register access is enabled
|
||||
* @return false if peripheral register access is disabled
|
||||
*/
|
||||
__STATIC_INLINE bool DL_TRNG_isPowerEnabled(TRNG_Regs *trng)
|
||||
{
|
||||
return ((TRNG->GPRCM.PWREN & TRNG_PWREN_ENABLE_MASK) ==
|
||||
TRNG_PWREN_ENABLE_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the clock divider on the TRNG module
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return Clock divider value for the TRNG module
|
||||
*/
|
||||
__STATIC_INLINE DL_TRNG_CLOCK_DIVIDE DL_TRNG_getClockDivider(
|
||||
const TRNG_Regs *trng)
|
||||
{
|
||||
return (DL_TRNG_CLOCK_DIVIDE) trng->CLKDIVIDE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the clock divider on the TRNG module
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @param clockDivider Clock divider value for the TRNG module.
|
||||
* One of @ref DL_TRNG_CLOCK_DIVIDE
|
||||
*/
|
||||
__STATIC_INLINE void DL_TRNG_setClockDivider(
|
||||
TRNG_Regs *trng, DL_TRNG_CLOCK_DIVIDE clockDivider)
|
||||
{
|
||||
trng->CLKDIVIDE = (uint32_t) clockDivider;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets the TRNG module
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_TRNG_reset(TRNG_Regs *trng)
|
||||
{
|
||||
trng->GPRCM.RSTCTL =
|
||||
TRNG_RSTCTL_RESETASSERT_ASSERT | TRNG_RSTCTL_KEY_UNLOCK_W;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if TRNG peripheral was reset
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return true if peripheral was reset
|
||||
* @return false if peripheral wasn't reset
|
||||
*/
|
||||
__STATIC_INLINE bool DL_TRNG_isReset(const TRNG_Regs *trng)
|
||||
{
|
||||
return (trng->GPRCM.STAT & TRNG_GPRCM_STAT_RESETSTKY_MASK) ==
|
||||
TRNG_GPRCM_STAT_RESETSTKY_RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if the data capture is ready
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return true if the data capture is ready
|
||||
* @return false if the data capture is not ready
|
||||
*/
|
||||
__STATIC_INLINE bool DL_TRNG_isCaptureReady(const TRNG_Regs *trng)
|
||||
{
|
||||
return ((trng->CPU_INT.RIS & TRNG_RIS_IRQ_CAPTURED_RDY_MASK)) ==
|
||||
TRNG_RIS_IRQ_CAPTURED_RDY_SET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if the issued TRNG command is done
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return true if the issued command is done
|
||||
* @return false if the issued command is not done
|
||||
*/
|
||||
__STATIC_INLINE bool DL_TRNG_isCommandDone(const TRNG_Regs *trng)
|
||||
{
|
||||
return ((trng->CPU_INT.RIS & TRNG_RIS_IRQ_CMD_DONE_MASK)) ==
|
||||
TRNG_RIS_IRQ_CMD_DONE_SET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if the issued TRNG command failed
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return true if the issued command failed
|
||||
* @return false if the issued command failed
|
||||
*/
|
||||
__STATIC_INLINE bool DL_TRNG_isCommandFail(const TRNG_Regs *trng)
|
||||
{
|
||||
return ((trng->CPU_INT.RIS & TRNG_RIS_IRQ_CMD_FAIL_MASK)) ==
|
||||
TRNG_RIS_IRQ_CMD_FAIL_SET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if a health test failed
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return true if a health test is failed
|
||||
* @return false if a health test did not fail
|
||||
*/
|
||||
__STATIC_INLINE bool DL_TRNG_isHealthTestFail(const TRNG_Regs *trng)
|
||||
{
|
||||
return ((trng->CPU_INT.RIS & TRNG_RIS_IRQ_HEALTH_FAIL_MASK)) ==
|
||||
TRNG_RIS_IRQ_HEALTH_FAIL_SET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the decimation rate
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @param decimationRate Decimation rate to set.
|
||||
* One of @ref DL_TRNG_DECIMATION_RATE
|
||||
*/
|
||||
__STATIC_INLINE void DL_TRNG_setDecimationRate(
|
||||
TRNG_Regs *trng, DL_TRNG_DECIMATION_RATE decimationRate)
|
||||
{
|
||||
DL_Common_updateReg(&trng->CTL,
|
||||
((uint32_t) decimationRate << TRNG_CTL_DECIM_RATE_OFS),
|
||||
TRNG_CTL_DECIM_RATE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the decimation rate
|
||||
*
|
||||
* @param[in] trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The decimation rate of the TRNG module
|
||||
*
|
||||
* @retval One of @ref DL_TRNG_DECIMATION_RATE
|
||||
*/
|
||||
__STATIC_INLINE DL_TRNG_DECIMATION_RATE DL_TRNG_getDecimationRate(
|
||||
const TRNG_Regs *trng)
|
||||
{
|
||||
uint32_t decimationRate =
|
||||
((trng->CTL & TRNG_CTL_DECIM_RATE_MASK) >> TRNG_CTL_DECIM_RATE_OFS);
|
||||
|
||||
return (DL_TRNG_DECIMATION_RATE)(decimationRate);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the digital health test results
|
||||
*
|
||||
* The test sequence includes eight tests, and each test reports its status in
|
||||
* an individual result bit. As each test passes, the corresponding bit is set.
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The results of the digital health tests
|
||||
*
|
||||
* @retval DL_TRNG_DIGITAL_HEALTH_TEST_SUCCESS if all tests passed,
|
||||
* otherwise a bitmask of which tests passed
|
||||
*/
|
||||
__STATIC_INLINE uint8_t DL_TRNG_getDigitalHealthTestResults(
|
||||
const TRNG_Regs *trng)
|
||||
{
|
||||
return (uint8_t)(trng->TEST_RESULTS & TRNG_TEST_RESULTS_DIG_TEST_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the analog health test results
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The results of the analog health test
|
||||
*
|
||||
* @retval DL_TRNG_ANALOG_HEALTH_TEST_SUCCESS if success
|
||||
* @retval 0 if test failed
|
||||
*/
|
||||
__STATIC_INLINE uint8_t DL_TRNG_getAnalogHealthTestResults(
|
||||
const TRNG_Regs *trng)
|
||||
{
|
||||
return (uint8_t)((trng->TEST_RESULTS & TRNG_TEST_RESULTS_ANA_TEST_MASK) >>
|
||||
TRNG_TEST_RESULTS_ANA_TEST_OFS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the current state of the TRNG front end FSM
|
||||
*
|
||||
* This API should be called twice since two reads of the state are required as
|
||||
* there is a chance of metastability when reading this register.
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The current state of the TRNG
|
||||
*
|
||||
* @retval One of @ref DL_TRNG_STATE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_TRNG_getCurrentState(const TRNG_Regs *trng)
|
||||
{
|
||||
return ((trng->STAT & TRNG_STAT_FSM_STATE_MASK)) >>
|
||||
TRNG_STAT_FSM_STATE_OFS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the last accepted command that was issued to the TRNG
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The last issued accepted command
|
||||
*
|
||||
* @retval One of @ref DL_TRNG_CMD
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_TRNG_getIssuedCommand(const TRNG_Regs *trng)
|
||||
{
|
||||
return ((trng->STAT & TRNG_STAT_ISSUED_CMD_MASK)) >>
|
||||
TRNG_STAT_ISSUED_CMD_OFS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicates if the repetition counter test caused the most recent
|
||||
* failure
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The status of the repetition test
|
||||
*
|
||||
* @retval true if the repetition test failed
|
||||
* @retval false if the repetition test did not fail
|
||||
*/
|
||||
__STATIC_INLINE bool DL_TRNG_isRepetitionTestFail(const TRNG_Regs *trng)
|
||||
{
|
||||
return ((trng->STAT & TRNG_STAT_REP_FAIL_MASK)) == TRNG_STAT_REP_FAIL_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicates if the Adaptive Proportion Test (1,2,3, or 4-bit counters)
|
||||
* caused the most recent failure
|
||||
*
|
||||
* @param trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The status of the Adaptive Proportion Test
|
||||
*
|
||||
* @retval true if the repetition test failed
|
||||
* @retval false if the repetition test did not fail
|
||||
*/
|
||||
__STATIC_INLINE bool DL_TRNG_isAdaptiveTestFail(const TRNG_Regs *trng)
|
||||
{
|
||||
return ((trng->STAT & TRNG_STAT_ADAP_FAIL_MASK)) ==
|
||||
TRNG_STAT_ADAP_FAIL_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable TRNG interrupt
|
||||
*
|
||||
* @param[in] trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of
|
||||
* @ref DL_TRNG_INTERRUPT.
|
||||
*/
|
||||
__STATIC_INLINE void DL_TRNG_enableInterrupt(
|
||||
TRNG_Regs *trng, uint32_t interruptMask)
|
||||
{
|
||||
trng->CPU_INT.IMASK |= interruptMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable TRNG interrupt
|
||||
*
|
||||
* @param[in] trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of
|
||||
* @ref DL_TRNG_INTERRUPT.
|
||||
*/
|
||||
__STATIC_INLINE void DL_TRNG_disableInterrupt(
|
||||
TRNG_Regs *trng, uint32_t interruptMask)
|
||||
{
|
||||
trng->CPU_INT.IMASK &= ~interruptMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check which TRNG interrupts are enabled
|
||||
*
|
||||
* @param[in] trng Pointer to the register overlay for the
|
||||
* peripheral
|
||||
* @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of
|
||||
* @ref DL_TRNG_IIDX.
|
||||
*
|
||||
* @return Which of the requested TRNG interrupts are enabled
|
||||
*
|
||||
* @retval Bitwise OR of @ref DL_TRNG_INTERRUPT values
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_TRNG_getEnabledInterrupts(
|
||||
const TRNG_Regs *trng, uint32_t interruptMask)
|
||||
{
|
||||
return trng->CPU_INT.IMASK & interruptMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check interrupt flag of enabled TRNG interrupt
|
||||
*
|
||||
* Checks if the TRNG interrupt that was previously enabled is pending.
|
||||
*
|
||||
* @param[in] trng Pointer to the register overlay for the
|
||||
* peripheral
|
||||
*
|
||||
* @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of
|
||||
* @ref DL_TRNG_INTERRUPT.
|
||||
*
|
||||
* @return If the enabled TRNG interrupt is pending
|
||||
*
|
||||
* @sa DL_TRNG_enableInterrupt
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_TRNG_getEnabledInterruptStatus(
|
||||
const TRNG_Regs *trng, uint32_t interruptMask)
|
||||
{
|
||||
return (trng->CPU_INT.MIS & interruptMask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check interrupt flag of any TRNG interrupt
|
||||
*
|
||||
* Checks if the TRNG interrupt is pending. Interrupt does not have to
|
||||
* be previously enabled.
|
||||
*
|
||||
* @param[in] trng Pointer to the register overlay for the
|
||||
* peripheral
|
||||
*
|
||||
* @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of
|
||||
* @ref DL_TRNG_INTERRUPT.
|
||||
*
|
||||
* @return If the trng interrupt is pending
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_TRNG_getRawInterruptStatus(
|
||||
const TRNG_Regs *trng, uint32_t interruptMask)
|
||||
{
|
||||
return trng->CPU_INT.RIS & interruptMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get highest priority pending TRNG interrupt
|
||||
*
|
||||
* Checks if any of the TRNG interrupts are pending. Interrupts do not have to
|
||||
* be previously enabled.
|
||||
*
|
||||
* @param[in] trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The highest priority pending TRNG interrupt
|
||||
*
|
||||
* @retval One of @ref DL_TRNG_IIDX
|
||||
*/
|
||||
__STATIC_INLINE DL_TRNG_IIDX DL_TRNG_getPendingInterrupt(const TRNG_Regs *trng)
|
||||
{
|
||||
return (DL_TRNG_IIDX) trng->CPU_INT.IIDX;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear pending TRNG interrupt
|
||||
*
|
||||
* @param[in] trng Pointer to the register overlay for the
|
||||
* peripheral
|
||||
*
|
||||
* @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of
|
||||
* @ref DL_TRNG_INTERRUPT.
|
||||
*/
|
||||
__STATIC_INLINE void DL_TRNG_clearInterruptStatus(
|
||||
TRNG_Regs *trng, uint32_t interruptMask)
|
||||
{
|
||||
trng->CPU_INT.ICLR = interruptMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update control register's command bits to send a TRNG command
|
||||
*
|
||||
* @param[in] trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @param[in] cmd Command to update the control register with
|
||||
*/
|
||||
__STATIC_INLINE void DL_TRNG_sendCommand(TRNG_Regs *trng, DL_TRNG_CMD cmd)
|
||||
{
|
||||
DL_Common_updateReg(&trng->CTL, (uint32_t) cmd, TRNG_CTL_CMD_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get word capture from TRNG
|
||||
*
|
||||
* Gets the captured data from the decimation block.
|
||||
*
|
||||
* @param[in] trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @retval TRNG capture value
|
||||
*
|
||||
* @pre The IRQ_CAPTURED_RDY IRQ should be asserted first, indicating that
|
||||
* random bits are available for read-out.
|
||||
*
|
||||
* @sa DL_TRNG_isCaptureReady
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_TRNG_getCapture(const TRNG_Regs *trng)
|
||||
{
|
||||
return trng->DATA_CAPTURE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Save TRNG configuration before entering a power loss state.
|
||||
*
|
||||
* @param[in] trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @param[in] ptr Configuration backup setup structure. See
|
||||
* @ref DL_TRNG_backupConfig.
|
||||
*
|
||||
* @retval FALSE if a configuration already exists in ptr (will not be
|
||||
* overwritten). TRUE if a configuration was successfully saved
|
||||
*/
|
||||
bool DL_TRNG_saveConfiguration(
|
||||
const TRNG_Regs *trng, DL_TRNG_backupConfig *ptr);
|
||||
|
||||
/**
|
||||
* @brief Restore TRNG configuration after leaving a power loss state.
|
||||
* Upon restoration, if the TRNG was not originally in OFF state,
|
||||
* then the TRNG will be set to the normal operating mode.
|
||||
*
|
||||
* @param[in] trng Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @param[in] ptr Configuration backup setup structure. See
|
||||
* @ref DL_TRNG_backupConfig.
|
||||
*
|
||||
* @retval FALSE if a configuration does not exist in ptr (will not be
|
||||
* loaded). TRUE if a configuration successfully loaded
|
||||
*/
|
||||
bool DL_TRNG_restoreConfiguration(TRNG_Regs *trng, DL_TRNG_backupConfig *ptr);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MSPM0_HAS_TRNG__ */
|
||||
|
||||
#endif /* ti_dl_dl_trng__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,339 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_uart_extend.h>
|
||||
#include <ti/driverlib/dl_uart_main.h>
|
||||
|
||||
#if defined(__MSPM0_HAS_UART_MAIN__) || defined(__MSPM0_HAS_UART_EXTD__)
|
||||
|
||||
void DL_UART_init(UART_Regs *uart, const DL_UART_Config *config)
|
||||
{
|
||||
DL_UART_disable(uart);
|
||||
|
||||
DL_Common_updateReg(&uart->CTL0,
|
||||
(uint32_t) config->mode | (uint32_t) config->direction |
|
||||
(uint32_t) config->flowControl,
|
||||
UART_CTL0_RXE_MASK | UART_CTL0_TXE_MASK | UART_CTL0_MODE_MASK |
|
||||
UART_CTL0_RTSEN_MASK | UART_CTL0_CTSEN_MASK | UART_CTL0_FEN_MASK);
|
||||
|
||||
DL_Common_updateReg(&uart->LCRH,
|
||||
(uint32_t) config->parity | (uint32_t) config->wordLength |
|
||||
(uint32_t) config->stopBits,
|
||||
UART_LCRH_PEN_ENABLE | UART_LCRH_EPS_MASK | UART_LCRH_SPS_MASK |
|
||||
UART_LCRH_WLEN_MASK | UART_LCRH_STP2_MASK);
|
||||
}
|
||||
|
||||
void DL_UART_setClockConfig(UART_Regs *uart, const DL_UART_ClockConfig *config)
|
||||
{
|
||||
uart->CLKSEL = (uint32_t) config->clockSel;
|
||||
|
||||
uart->CLKDIV = (uint32_t) config->divideRatio;
|
||||
}
|
||||
|
||||
void DL_UART_getClockConfig(const UART_Regs *uart, DL_UART_ClockConfig *config)
|
||||
{
|
||||
config->clockSel = (DL_UART_CLOCK) uart->CLKSEL;
|
||||
|
||||
config->divideRatio = (DL_UART_CLOCK_DIVIDE_RATIO) uart->CLKDIV;
|
||||
}
|
||||
|
||||
void DL_UART_configBaudRate(
|
||||
UART_Regs *uart, uint32_t clockFreq, uint32_t baudRate)
|
||||
{
|
||||
uint32_t divisor;
|
||||
|
||||
/*
|
||||
* The baud rate divisor, brd, is calculated with the following formula:
|
||||
* brd = ibrd.fbrd = clockOutput / (OVS * baudRate)
|
||||
* where ibrd is the integer part, fbrd is the fractional part.
|
||||
* Since fbrd is 6 bits, multiply brd by 64:
|
||||
* 64 * brd = (clockOutput * 64) / (16 * baudRate)
|
||||
* = (clockOutput * 4) / baudRate
|
||||
* add 1/2 to round the least significant bit of fbrd:
|
||||
* 64 * brd + 1/2 = (clockOutput * 8 / (2 * baudRate) + 1/2
|
||||
* divisor = 64*brd+1/2 = [(clockOutput * 8)/ baudRate + 1] / 2
|
||||
*
|
||||
* The lower 6 bits is fbrd, upper part is ibrd
|
||||
* Note: If ibrd is 0, FBRD will be ignored and no data will be
|
||||
* transferred.
|
||||
*/
|
||||
|
||||
/* Calculate baud rate divisor based on OVS: */
|
||||
if ((baudRate * (uint32_t) 8) > clockFreq) {
|
||||
DL_UART_setOversampling(uart, DL_UART_OVERSAMPLING_RATE_3X);
|
||||
divisor = ((clockFreq * (uint32_t) 64) / (baudRate * (uint32_t) 3)) +
|
||||
((uint32_t) 1 / (uint32_t) 2);
|
||||
|
||||
} else if ((baudRate * (uint32_t) 16) > clockFreq) {
|
||||
DL_UART_setOversampling(uart, DL_UART_OVERSAMPLING_RATE_8X);
|
||||
baudRate = baudRate / (uint32_t) 2;
|
||||
divisor = (((clockFreq * (uint32_t) 8) / baudRate) + (uint32_t) 1) /
|
||||
(uint32_t) 2;
|
||||
|
||||
} else {
|
||||
DL_UART_setOversampling(uart, DL_UART_OVERSAMPLING_RATE_16X);
|
||||
divisor = (((clockFreq * (uint32_t) 8) / baudRate) + (uint32_t) 1) /
|
||||
(uint32_t) 2;
|
||||
}
|
||||
|
||||
/* Set the integer and fractional parts of the baud rate divisor */
|
||||
DL_UART_setBaudRateDivisor(
|
||||
uart, divisor >> (uint32_t) 6, divisor & (uint32_t) 0x3F);
|
||||
}
|
||||
|
||||
// TODO: Verify parameters and units
|
||||
/**
|
||||
* @brief Set the IrDA configurations
|
||||
*
|
||||
* Calculates the baud rate divisor given the clock output of the UART clock
|
||||
* source and the target baud rate. This API also enables IrDA mode.
|
||||
*
|
||||
* @param[in] uart Pointer to the register overlay for the peripheral
|
||||
* @param[in] polarity The receive input polarity.
|
||||
* One of @DL_UART_IRDA_POLARITY.
|
||||
* @param[in] pulseLength The length of the IrDA transmit pulse.
|
||||
* @param[in] irdaClk The clock used for the transmit pulse.
|
||||
* One of @DL_UART_IRDA_CLOCK.
|
||||
*/
|
||||
void DL_UART_configIrDAMode(UART_Regs *uart, DL_UART_IRDA_POLARITY polarity,
|
||||
uint32_t pulseLength, DL_UART_IRDA_CLOCK irdaClk)
|
||||
{
|
||||
DL_Common_updateReg(&uart->IRCTL,
|
||||
(uint32_t) polarity | UART_IRCTL_IREN_ENABLE,
|
||||
UART_IRCTL_IRRXPL_MASK | UART_IRCTL_IREN_MASK);
|
||||
|
||||
DL_UART_setIrDAPulseLength(uart, pulseLength, irdaClk);
|
||||
}
|
||||
|
||||
void DL_UART_setIrDAPulseLength(
|
||||
UART_Regs *uart, uint32_t pulseLength, DL_UART_IRDA_CLOCK irdaClk)
|
||||
{
|
||||
uint32_t IRTXPL;
|
||||
|
||||
if (pulseLength == DL_UART_PULSE_WIDTH_3_16_BIT_PERIOD) {
|
||||
// Set IRTXCLK = 0 = BITCLK16 and IRTXPL = 5
|
||||
DL_Common_updateReg(&uart->IRCTL, 0x14,
|
||||
UART_IRCTL_IRTXCLK_MASK | UART_IRCTL_IRTXPL_MASK);
|
||||
} else {
|
||||
IRTXPL =
|
||||
pulseLength * (uint32_t) 2 * (uint32_t) irdaClk - (uint32_t) 1;
|
||||
|
||||
DL_Common_updateReg(&uart->IRCTL, IRTXPL,
|
||||
UART_IRCTL_IRTXCLK_MASK | UART_IRCTL_IRTXPL_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t DL_UART_receiveDataBlocking(const UART_Regs *uart)
|
||||
{
|
||||
while (DL_UART_isRXFIFOEmpty(uart)) {
|
||||
};
|
||||
|
||||
return DL_UART_receiveData(uart);
|
||||
}
|
||||
|
||||
void DL_UART_transmitDataBlocking(UART_Regs *uart, uint8_t data)
|
||||
{
|
||||
while (DL_UART_isTXFIFOFull(uart)) {
|
||||
};
|
||||
DL_UART_transmitData(uart, data);
|
||||
}
|
||||
|
||||
bool DL_UART_receiveDataCheck(const UART_Regs *uart, uint8_t *buffer)
|
||||
{
|
||||
bool status;
|
||||
if (DL_UART_isRXFIFOEmpty(uart)) {
|
||||
status = false;
|
||||
} else {
|
||||
*buffer = DL_UART_receiveData(uart);
|
||||
status = true;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
bool DL_UART_transmitDataCheck(UART_Regs *uart, uint8_t data)
|
||||
{
|
||||
bool status;
|
||||
if (DL_UART_isTXFIFOFull(uart)) {
|
||||
status = false;
|
||||
} else {
|
||||
DL_UART_transmitData(uart, data);
|
||||
status = true;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
uint32_t DL_UART_drainRXFIFO(
|
||||
const UART_Regs *uart, uint8_t *buffer, uint32_t maxCount)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0; i < maxCount; i++) {
|
||||
if (!DL_UART_isRXFIFOEmpty(uart)) {
|
||||
buffer[i] = DL_UART_receiveData(uart);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
uint32_t DL_UART_fillTXFIFO(
|
||||
UART_Regs *uart, const uint8_t *buffer, uint32_t count)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0; i < count; i++) {
|
||||
if (!DL_UART_isTXFIFOFull(uart)) {
|
||||
DL_UART_transmitData(uart, buffer[i]);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
#ifdef __MSPM0_HAS_UART_MAIN__
|
||||
|
||||
bool DL_UART_Main_saveConfiguration(
|
||||
const UART_Regs *uart, DL_UART_Main_backupConfig *ptr)
|
||||
{
|
||||
bool stateSaved = !ptr->backupRdy;
|
||||
if (stateSaved) {
|
||||
ptr->controlWord = uart->CTL0;
|
||||
ptr->clockSel = uart->CLKSEL;
|
||||
ptr->divideRatio = uart->CLKDIV;
|
||||
ptr->interruptFifoLevelSelectWord = uart->IFLS;
|
||||
ptr->ibrd = uart->IBRD;
|
||||
ptr->fbrd = uart->FBRD;
|
||||
ptr->lineControlRegisterWord = uart->LCRH;
|
||||
ptr->glitchFilterControlWord = uart->GFCTL;
|
||||
ptr->interruptMask0 = uart->CPU_INT.IMASK;
|
||||
ptr->interruptMask1 = uart->DMA_TRIG_RX.IMASK;
|
||||
ptr->interruptMask2 = uart->DMA_TRIG_TX.IMASK;
|
||||
ptr->backupRdy = true;
|
||||
}
|
||||
return stateSaved;
|
||||
}
|
||||
|
||||
bool DL_UART_Main_restoreConfiguration(
|
||||
UART_Regs *uart, DL_UART_Main_backupConfig *ptr)
|
||||
{
|
||||
bool stateRestored = ptr->backupRdy;
|
||||
if (stateRestored) {
|
||||
/* Set CTL0.ENABLE=0 during initialization */
|
||||
uart->CTL0 = ptr->controlWord & ~(UART_CTL0_ENABLE_MASK);
|
||||
uart->CLKSEL = ptr->clockSel;
|
||||
uart->CLKDIV = ptr->divideRatio;
|
||||
uart->IFLS = ptr->interruptFifoLevelSelectWord;
|
||||
uart->IBRD = ptr->ibrd;
|
||||
uart->FBRD = ptr->fbrd;
|
||||
uart->LCRH = ptr->lineControlRegisterWord;
|
||||
uart->GFCTL = ptr->glitchFilterControlWord;
|
||||
uart->CPU_INT.IMASK = ptr->interruptMask0;
|
||||
uart->DMA_TRIG_RX.IMASK = ptr->interruptMask1;
|
||||
uart->DMA_TRIG_TX.IMASK = ptr->interruptMask2;
|
||||
|
||||
/* Re-enable UART if it was originally enabled */
|
||||
if ((ptr->controlWord & UART_CTL0_ENABLE_MASK) ==
|
||||
UART_CTL0_ENABLE_MASK) {
|
||||
DL_UART_enable(uart);
|
||||
}
|
||||
ptr->backupRdy = false;
|
||||
}
|
||||
return stateRestored;
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_UART_MAIN__ */
|
||||
|
||||
#ifdef __MSPM0_HAS_UART_EXTD__
|
||||
|
||||
bool DL_UART_Extend_saveConfiguration(
|
||||
const UART_Regs *uart, DL_UART_Extend_backupConfig *ptr)
|
||||
{
|
||||
bool stateSaved = !ptr->backupRdy;
|
||||
if (stateSaved) {
|
||||
ptr->controlWord = uart->CTL0;
|
||||
ptr->clockSel = uart->CLKSEL;
|
||||
ptr->divideRatio = uart->CLKDIV;
|
||||
ptr->interruptFifoLevelSelectWord = uart->IFLS;
|
||||
ptr->ibrd = uart->IBRD;
|
||||
ptr->fbrd = uart->FBRD;
|
||||
ptr->lineControlRegisterWord = uart->LCRH;
|
||||
ptr->glitchFilterControlWord = uart->GFCTL;
|
||||
ptr->linControlWord = uart->LINCTL;
|
||||
ptr->irdaControlWord = uart->IRCTL;
|
||||
ptr->addressMask = uart->AMASK;
|
||||
ptr->address = uart->ADDR;
|
||||
ptr->interruptMask0 = uart->CPU_INT.IMASK;
|
||||
ptr->interruptMask1 = uart->DMA_TRIG_RX.IMASK;
|
||||
ptr->interruptMask2 = uart->DMA_TRIG_TX.IMASK;
|
||||
ptr->backupRdy = true;
|
||||
}
|
||||
return stateSaved;
|
||||
}
|
||||
|
||||
bool DL_UART_Extend_restoreConfiguration(
|
||||
UART_Regs *uart, DL_UART_Extend_backupConfig *ptr)
|
||||
{
|
||||
bool stateRestored = ptr->backupRdy;
|
||||
if (stateRestored) {
|
||||
/* Set CTL0.ENABLE=0 during initialization */
|
||||
uart->CTL0 = ptr->controlWord & ~(UART_CTL0_ENABLE_MASK);
|
||||
uart->CLKSEL = ptr->clockSel;
|
||||
uart->CLKDIV = ptr->divideRatio;
|
||||
uart->IFLS = ptr->interruptFifoLevelSelectWord;
|
||||
uart->IBRD = ptr->ibrd;
|
||||
uart->FBRD = ptr->fbrd;
|
||||
uart->LCRH = ptr->lineControlRegisterWord;
|
||||
uart->GFCTL = ptr->glitchFilterControlWord;
|
||||
uart->LCRH = ptr->lineControlRegisterWord;
|
||||
uart->IRCTL = ptr->irdaControlWord;
|
||||
uart->AMASK = ptr->addressMask;
|
||||
uart->ADDR = ptr->address;
|
||||
uart->CPU_INT.IMASK = ptr->interruptMask0;
|
||||
uart->DMA_TRIG_RX.IMASK = ptr->interruptMask1;
|
||||
uart->DMA_TRIG_TX.IMASK = ptr->interruptMask2;
|
||||
|
||||
/* Re-enable UART if it was originally enabled */
|
||||
if ((ptr->controlWord & UART_CTL0_ENABLE_MASK) ==
|
||||
UART_CTL0_ENABLE_MASK) {
|
||||
DL_UART_enable(uart);
|
||||
}
|
||||
ptr->backupRdy = false;
|
||||
}
|
||||
return stateRestored;
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_UART_EXTD__ */
|
||||
|
||||
#endif /* __MSPM0_HAS_UART_MAIN__ || __MSPM0_HAS_UART_EXTD__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_vref.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_VREF__
|
||||
|
||||
void DL_VREF_configReference(VREF_Regs *vref, const DL_VREF_Config *config)
|
||||
{
|
||||
vref->CTL0 = (uint32_t) config->vrefEnable | (uint32_t) config->bufConfig |
|
||||
(uint32_t) config->shModeEnable;
|
||||
vref->CTL2 = (config->shCycleCount << VREF_CTL2_SHCYCLE_OFS) |
|
||||
(config->holdCycleCount << VREF_CTL2_HCYCLE_OFS);
|
||||
}
|
||||
|
||||
void DL_VREF_setClockConfig(VREF_Regs *vref, const DL_VREF_ClockConfig *config)
|
||||
{
|
||||
vref->CLKSEL = (uint32_t) config->clockSel;
|
||||
vref->CLKDIV = (uint32_t) config->divideRatio;
|
||||
}
|
||||
|
||||
void DL_VREF_getClockConfig(const VREF_Regs *vref, DL_VREF_ClockConfig *config)
|
||||
{
|
||||
config->clockSel = (DL_VREF_CLOCK) vref->CLKSEL;
|
||||
config->divideRatio = (DL_VREF_CLOCK_DIVIDE) vref->CLKDIV;
|
||||
}
|
||||
|
||||
#endif /* __MSPM0_HAS_VREF__ */
|
||||
@@ -0,0 +1,405 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_vref.h
|
||||
* @brief Voltage Reference (VREF) Driver Library
|
||||
* @defgroup VREF Voltage Reference (VREF)
|
||||
*
|
||||
* @anchor ti_dl_dl_vref_Overview
|
||||
* # Overview
|
||||
*
|
||||
* The Voltage Reference Driver Library allows full configuration of
|
||||
* the MSPM0 VREF module.
|
||||
* The VREF module contains a configurable voltage reference buffer which
|
||||
* allows users to supply a stable internal reference to on-board analog
|
||||
* peripherals. It also supports bringing in an external reference for
|
||||
* applications where higher accuracy is required.
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup VREF
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_dl_m0p_vref__include
|
||||
#define ti_dl_dl_m0p_vref__include
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
#include <ti/driverlib/dl_common.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_VREF__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/** @addtogroup DL_VREF_CTL1_READY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief VREF bit in CTL1 indicating the module is ready is not set
|
||||
*/
|
||||
#define DL_VREF_CTL1_READY_NOTRDY (VREF_CTL1_READY_NOTRDY)
|
||||
|
||||
/*!
|
||||
* @brief VREF bit in CTL1 indicating the module is ready is set
|
||||
*/
|
||||
#define DL_VREF_CTL1_READY_RDY (VREF_CTL1_READY_RDY)
|
||||
|
||||
|
||||
/** @}*/
|
||||
|
||||
/** @addtogroup DL_VREF_SH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Minimum value for VREF sample and hold, if enabled
|
||||
*/
|
||||
#define DL_VREF_SH_MIN (VREF_CTL2_SHCYCLE_MINIMUM)
|
||||
|
||||
/*!
|
||||
* @brief Maximum value for VREF sample and hold, if enabled
|
||||
*/
|
||||
#define DL_VREF_SH_MAX (VREF_CTL2_SHCYCLE_MAXIMUM)
|
||||
|
||||
/** @}*/
|
||||
|
||||
/** @addtogroup DL_VREF_HOLD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Minimum value for VREF hold, if enabled
|
||||
*/
|
||||
#define DL_VREF_HOLD_MIN (VREF_CTL2_HCYCLE_MINIMUM)
|
||||
|
||||
/*!
|
||||
* @brief Maximum value for VREF hold, if enabled
|
||||
*/
|
||||
#define DL_VREF_HOLD_MAX (VREF_CTL2_HCYCLE_MAXIMUM)
|
||||
|
||||
/** @}*/
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
/*! @enum DL_VREF_CLOCK */
|
||||
typedef enum {
|
||||
/*! Set VREF clock source as LFCLK */
|
||||
DL_VREF_CLOCK_LFCLK = VREF_CLKSEL_LFCLK_SEL_MASK,
|
||||
/*! Set VREF clock source as MFCLK */
|
||||
DL_VREF_CLOCK_MFCLK = VREF_CLKSEL_MFCLK_SEL_MASK,
|
||||
/*! Set VREF clock source as BUSCLK */
|
||||
DL_VREF_CLOCK_BUSCLK = VREF_CLKSEL_BUSCLK_SEL_MASK,
|
||||
} DL_VREF_CLOCK;
|
||||
|
||||
/*! @enum DL_VREF_CLOCK_DIVIDE */
|
||||
typedef enum {
|
||||
/*! Clock divide by 1 */
|
||||
DL_VREF_CLOCK_DIVIDE_1 = 0,
|
||||
/*! Clock divide by 2 */
|
||||
DL_VREF_CLOCK_DIVIDE_2 = 1,
|
||||
/*! Clock divide by 4 */
|
||||
DL_VREF_CLOCK_DIVIDE_4 = 3,
|
||||
/*! Clock divide by 6 */
|
||||
DL_VREF_CLOCK_DIVIDE_6 = 5,
|
||||
/*! Clock divide by 8 */
|
||||
DL_VREF_CLOCK_DIVIDE_8 = 7,
|
||||
} DL_VREF_CLOCK_DIVIDE;
|
||||
|
||||
/*! @enum DL_VREF_ENABLE */
|
||||
typedef enum {
|
||||
/*! VREF control set disabled */
|
||||
DL_VREF_ENABLE_DISABLE = VREF_CTL0_ENABLE_DISABLE,
|
||||
/*! VREF control set enabled */
|
||||
DL_VREF_ENABLE_ENABLE = VREF_CTL0_ENABLE_ENABLE,
|
||||
} DL_VREF_ENABLE;
|
||||
|
||||
/*! @enum DL_VREF_BUFCONFIG */
|
||||
typedef enum {
|
||||
/*! Configure VREF output buffer to 2.5V */
|
||||
DL_VREF_BUFCONFIG_OUTPUT_2_5V = VREF_CTL0_BUFCONFIG_OUTPUT2P5V,
|
||||
/*! Configure VREF output buffer to 1.4V */
|
||||
DL_VREF_BUFCONFIG_OUTPUT_1_4V = VREF_CTL0_BUFCONFIG_OUTPUT1P4V,
|
||||
} DL_VREF_BUFCONFIG;
|
||||
|
||||
/*! @enum DL_VREF_SHMODE */
|
||||
typedef enum {
|
||||
/*! Set VREF sample and hold mode to disabled */
|
||||
DL_VREF_SHMODE_DISABLE = VREF_CTL0_SHMODE_DISABLE,
|
||||
/*! Set VREF sample and hold mode to enabled */
|
||||
DL_VREF_SHMODE_ENABLE = VREF_CTL0_SHMODE_ENABLE,
|
||||
} DL_VREF_SHMODE;
|
||||
|
||||
/*!
|
||||
* @brief Configuration struct for @ref DL_VREF_setClockConfig.
|
||||
*/
|
||||
typedef struct {
|
||||
/*! Selects VREF module clock source @ref DL_VREF_CLOCK */
|
||||
DL_VREF_CLOCK clockSel;
|
||||
/*! Selects the divide ratio. One of @ref DL_VREF_CLOCK_DIVIDE */
|
||||
DL_VREF_CLOCK_DIVIDE divideRatio;
|
||||
} DL_VREF_ClockConfig;
|
||||
|
||||
/**
|
||||
* @brief Configuration struct for @ref DL_VREF_Config.
|
||||
*/
|
||||
typedef struct {
|
||||
/*! VREF enable setting. Either @ref DL_VREF_ENABLE_DISABLE or @ref DL_VREF_ENABLE_ENABLE */
|
||||
DL_VREF_ENABLE vrefEnable;
|
||||
/*! VREF buffer configuration setting. Either @ref DL_VREF_BUFCONFIG_OUTPUT_1_4V or @ref DL_VREF_BUFCONFIG_OUTPUT_2_5V */
|
||||
DL_VREF_BUFCONFIG bufConfig;
|
||||
/*! VREF sample and hold enable configuration setting. Either @ref DL_VREF_SHMODE_DISABLE or @ref DL_VREF_SHMODE_ENABLE */
|
||||
DL_VREF_SHMODE shModeEnable;
|
||||
/*! Number of cycles to sample and hold for, if sample and hold mode is enabled. Minimum @ref DL_VREF_SH_MIN, maximum @ref DL_VREF_SH_MAX */
|
||||
uint32_t shCycleCount;
|
||||
/*! Number of cycles to hold for, if sample and hold mode is enabled. Minimum @ref DL_VREF_HOLD_MIN, maximum @ref DL_VREF_HOLD_MAX */
|
||||
uint32_t holdCycleCount;
|
||||
} DL_VREF_Config;
|
||||
|
||||
/**
|
||||
* @brief Enables the Peripheral Write Enable (PWREN) register for the VREF
|
||||
*
|
||||
* Before any peripheral registers can be configured by software, the
|
||||
* peripheral itself must be enabled by writing the ENABLE bit together with
|
||||
* the appropriate KEY value to the peripheral's PWREN register.
|
||||
*
|
||||
* @note For power savings, please refer to @ref DL_VREF_enableInternalRef
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_VREF_enablePower(VREF_Regs *vref)
|
||||
{
|
||||
vref->GPRCM.PWREN = VREF_PWREN_KEY_UNLOCK_W | VREF_PWREN_ENABLE_ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Peripheral Write Enable (PWREN) register for the VREF
|
||||
*
|
||||
* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
|
||||
* accessible for read/write operations.
|
||||
*
|
||||
* @note This API does not provide large power savings. For power savings,
|
||||
* please refer to @ref DL_VREF_disableInternalRef
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_VREF_disablePower(VREF_Regs *vref)
|
||||
{
|
||||
vref->GPRCM.PWREN = VREF_PWREN_KEY_UNLOCK_W | VREF_PWREN_ENABLE_DISABLE;
|
||||
}
|
||||
/**
|
||||
* @brief Returns if the Peripheral Write Enable (PWREN) register for the VREF
|
||||
* is enabled
|
||||
*
|
||||
* Before any peripheral registers can be configured by software, the
|
||||
* peripheral itself must be enabled by writing the ENABLE bit together with
|
||||
* the appropriate KEY value to the peripheral's PWREN register.
|
||||
*
|
||||
* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
|
||||
* accessible for read/write operations.
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return true if peripheral register access is enabled
|
||||
* @return false if peripheral register access is disabled
|
||||
*/
|
||||
__STATIC_INLINE bool DL_VREF_isPowerEnabled(VREF_Regs *vref)
|
||||
{
|
||||
return ((VREF->GPRCM.PWREN & VREF_PWREN_ENABLE_MASK) ==
|
||||
VREF_PWREN_ENABLE_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables Internal VREF
|
||||
*
|
||||
* This function only enables the internal VREF but doesn't configure all
|
||||
* settings. It's recommended to use @ref DL_VREF_configReference to configure
|
||||
* and enable VREF with all parameters.
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the peripheral
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_VREF_enableInternalRef(VREF_Regs *vref)
|
||||
{
|
||||
vref->CTL0 |= VREF_CTL0_ENABLE_ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables Internal VREF, allows for External VREF
|
||||
*
|
||||
* The internal VREF must be disabled when using external VREF input.
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the peripheral
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_VREF_disableInternalRef(VREF_Regs *vref)
|
||||
{
|
||||
vref->CTL0 &= ~VREF_CTL0_ENABLE_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if the internal VREF is enabled
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return Returns the enabled status of the vref peripheral
|
||||
*
|
||||
* @retval true The internal VREF is enabled
|
||||
* @retval false The internal VREF is disabled, external VREF can be used
|
||||
*/
|
||||
__STATIC_INLINE bool DL_VREF_isEnabled(const VREF_Regs *vref)
|
||||
{
|
||||
return ((vref->CTL0 & VREF_CTL0_ENABLE_MASK) == VREF_CTL0_ENABLE_ENABLE);
|
||||
}
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L122X_L222X)
|
||||
/**
|
||||
* @brief Enable VREF buffer as internal reference input for comparator
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_VREF_enableInternalRefCOMP(VREF_Regs *vref)
|
||||
{
|
||||
vref->CTL0 |= VREF_CTL0_COMP_VREF_ENABLE_ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if VREF buffer for comparator is enabled
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return Returns if VREF buffer for comparator is enabled
|
||||
*
|
||||
* @retval true VREF buffer for comparator is enabled
|
||||
* @retval false VREF buffer for comparator is disabled
|
||||
*/
|
||||
__STATIC_INLINE bool DL_VREF_isInternalRefCOMPEnabled(const VREF_Regs *vref)
|
||||
{
|
||||
return ((vref->CTL0 & VREF_CTL0_COMP_VREF_ENABLE_MASK) ==
|
||||
VREF_CTL0_COMP_VREF_ENABLE_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable VREF buffer as internal reference input for comparator
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_VREF_disableInternalRefCOMP(VREF_Regs *vref)
|
||||
{
|
||||
vref->CTL0 &= ~(VREF_CTL0_COMP_VREF_ENABLE_MASK);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Set the clock select and clock divide fields in VREF
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @param config Pointer to the configuration structure
|
||||
*/
|
||||
void DL_VREF_setClockConfig(
|
||||
VREF_Regs *vref, const DL_VREF_ClockConfig *config);
|
||||
|
||||
/**
|
||||
* @brief Copy the clock select and clock divide fields in VREF to config
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @param config Pointer to the configuration structure
|
||||
*/
|
||||
void DL_VREF_getClockConfig(
|
||||
const VREF_Regs *vref, DL_VREF_ClockConfig *config);
|
||||
|
||||
/**
|
||||
* @brief Resets the VREF module
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_VREF_reset(VREF_Regs *vref)
|
||||
{
|
||||
vref->GPRCM.RSTCTL =
|
||||
VREF_RSTCTL_RESETASSERT_MASK | VREF_RSTCTL_KEY_UNLOCK_W;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if VREF peripheral was reset
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the VREF peripheral
|
||||
*
|
||||
* @return true if peripheral was reset
|
||||
* @return false if peripheral wasn't reset
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE bool DL_VREF_isReset(const VREF_Regs *vref)
|
||||
{
|
||||
return (vref->GPRCM.STAT & VREF_STAT_RESETSTKY_MASK) ==
|
||||
VREF_STAT_RESETSTKY_RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns VREF register status
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the VREF peripheral
|
||||
*
|
||||
* @return VREF status bits set. Either @ref DL_VREF_CTL1_READY_NOTRDY or @ref DL_VREF_CTL1_READY_RDY
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_VREF_getStatus(const VREF_Regs *vref)
|
||||
{
|
||||
return vref->CTL1 & VREF_CTL1_READY_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure VREF enable, control registers
|
||||
*
|
||||
* @param vref Pointer to the register overlay for the VREF peripheral
|
||||
*
|
||||
* @param config Pointer to @ref DL_VREF_Config structure to configure the peripheral
|
||||
*
|
||||
*/
|
||||
void DL_VREF_configReference(VREF_Regs *vref, const DL_VREF_Config *config);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MSPM0_HAS_VREF__ */
|
||||
|
||||
#endif /* ti_dl_dl_m0p_vref__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2025, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <ti/driverlib/dl_wwdt.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_WWDT__
|
||||
#endif /* __MSPM0_HAS_WWDT__ */
|
||||
@@ -0,0 +1,616 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_wwdt.h
|
||||
* @brief Window Watchdog Timer (WWDT) Driver Library
|
||||
* @defgroup WWDT Window Watchdog Timer (WWDT)
|
||||
*
|
||||
* @anchor ti_dl_dl_wwdt_Overview
|
||||
* # Overview
|
||||
*
|
||||
* The Window Watchdog Timer Driver Library allows full configuration of
|
||||
* the MSPM0 WWDT module.
|
||||
* The window watchdog timer (WWDT) supervises code execution.
|
||||
* If the application software does not successfully reset the window
|
||||
* watchdog within the programmed open time window, the window watchdog
|
||||
* generates a SYSRST.
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup WWDT
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_dl_wwdt__include
|
||||
#define ti_dl_dl_wwdt__include
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
|
||||
#ifdef __MSPM0_HAS_WWDT__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/*! @enum DL_WWDT_CLOCK_DIVIDE */
|
||||
typedef enum {
|
||||
/*! Clock source divide by 1 */
|
||||
DL_WWDT_CLOCK_DIVIDE_1 = 0x00000000,
|
||||
/*! Clock source divide by 2 */
|
||||
DL_WWDT_CLOCK_DIVIDE_2 = 0x00000001,
|
||||
/*! Clock source divide by 3 */
|
||||
DL_WWDT_CLOCK_DIVIDE_3 = 0x00000002,
|
||||
/*! Clock source divide by 4 */
|
||||
DL_WWDT_CLOCK_DIVIDE_4 = 0x00000003,
|
||||
/*! Clock source divide by 5 */
|
||||
DL_WWDT_CLOCK_DIVIDE_5 = 0x00000004,
|
||||
/*! Clock source divide by 6 */
|
||||
DL_WWDT_CLOCK_DIVIDE_6 = 0x00000005,
|
||||
/*! Clock source divide by 7 */
|
||||
DL_WWDT_CLOCK_DIVIDE_7 = 0x00000006,
|
||||
/*! Clock source divide by 8 */
|
||||
DL_WWDT_CLOCK_DIVIDE_8 = 0x00000007
|
||||
} DL_WWDT_CLOCK_DIVIDE;
|
||||
|
||||
/*! @enum DL_WWDT_WINDOW */
|
||||
typedef enum {
|
||||
/*! Window 0 active */
|
||||
DL_WWDT_WINDOW0 = WWDT_WWDTCTL1_WINSEL_WIN0,
|
||||
/*! Window 1 active */
|
||||
DL_WWDT_WINDOW1 = WWDT_WWDTCTL1_WINSEL_WIN1
|
||||
} DL_WWDT_WINDOW;
|
||||
|
||||
/*! @enum DL_WWDT_WINDOW_PERIOD */
|
||||
typedef enum {
|
||||
/*! 0% closed window period */
|
||||
DL_WWDT_WINDOW_PERIOD_0 = WWDT_WWDTCTL0_WINDOW0_SIZE_0,
|
||||
/*! 12% closed window period */
|
||||
DL_WWDT_WINDOW_PERIOD_12 = WWDT_WWDTCTL0_WINDOW0_SIZE_12,
|
||||
/*! 18% closed window period */
|
||||
DL_WWDT_WINDOW_PERIOD_18 = WWDT_WWDTCTL0_WINDOW0_SIZE_18,
|
||||
/*! 25% closed window period */
|
||||
DL_WWDT_WINDOW_PERIOD_25 = WWDT_WWDTCTL0_WINDOW0_SIZE_25,
|
||||
/*! 50% closed window period */
|
||||
DL_WWDT_WINDOW_PERIOD_50 = WWDT_WWDTCTL0_WINDOW0_SIZE_50,
|
||||
/*! 75% closed window period */
|
||||
DL_WWDT_WINDOW_PERIOD_75 = WWDT_WWDTCTL0_WINDOW0_SIZE_75,
|
||||
/*! 81% closed window period */
|
||||
DL_WWDT_WINDOW_PERIOD_81 = WWDT_WWDTCTL0_WINDOW0_SIZE_81,
|
||||
/*! 87% closed window period */
|
||||
DL_WWDT_WINDOW_PERIOD_87 = WWDT_WWDTCTL0_WINDOW0_SIZE_87
|
||||
} DL_WWDT_WINDOW_PERIOD;
|
||||
|
||||
/*! @enum DL_WWDT_TIMER_PERIOD */
|
||||
typedef enum {
|
||||
/*! 2^6 timer period count */
|
||||
DL_WWDT_TIMER_PERIOD_6_BITS = WWDT_WWDTCTL0_PER_EN_6,
|
||||
/*! 2^8 timer period count */
|
||||
DL_WWDT_TIMER_PERIOD_8_BITS = WWDT_WWDTCTL0_PER_EN_8,
|
||||
/*! 2^10 timer period count */
|
||||
DL_WWDT_TIMER_PERIOD_10_BITS = WWDT_WWDTCTL0_PER_EN_10,
|
||||
/*! 2^12 timer period count */
|
||||
DL_WWDT_TIMER_PERIOD_12_BITS = WWDT_WWDTCTL0_PER_EN_12,
|
||||
/*! 2^15 timer period count */
|
||||
DL_WWDT_TIMER_PERIOD_15_BITS = WWDT_WWDTCTL0_PER_EN_15,
|
||||
/*! 2^18 timer period count */
|
||||
DL_WWDT_TIMER_PERIOD_18_BITS = WWDT_WWDTCTL0_PER_EN_18,
|
||||
/*! 2^21 timer period count */
|
||||
DL_WWDT_TIMER_PERIOD_21_BITS = WWDT_WWDTCTL0_PER_EN_21,
|
||||
/*! 2^25 timer period count */
|
||||
DL_WWDT_TIMER_PERIOD_25_BITS = WWDT_WWDTCTL0_PER_EN_25
|
||||
} DL_WWDT_TIMER_PERIOD;
|
||||
|
||||
/*! @enum DL_WWDT_SLEEP_MODE */
|
||||
typedef enum {
|
||||
/*! Stop the watchdog while in sleep */
|
||||
DL_WWDT_STOP_IN_SLEEP = WWDT_WWDTCTL0_STISM_STOP,
|
||||
/*! Keep the watchdog running in sleep */
|
||||
DL_WWDT_RUN_IN_SLEEP = WWDT_WWDTCTL0_STISM_CONT
|
||||
} DL_WWDT_SLEEP_MODE;
|
||||
|
||||
/*! @enum DL_WWDT_MODE */
|
||||
typedef enum {
|
||||
/*! The watchdog is in watchdog mode */
|
||||
DL_WWDT_WATCHDOG_MODE = 0x0,
|
||||
/*! The watchdog is in interval timer mode */
|
||||
DL_WWDT_INTERVAL_TIMER_MODE = WWDT_WWDTCTL0_MODE_INTERVAL
|
||||
} DL_WWDT_MODE;
|
||||
|
||||
/*! @enum DL_WWDT_IIDX */
|
||||
typedef enum {
|
||||
/*! Interrupt index for WWDT if no interrupt is pending */
|
||||
DL_WWDT_IIDX_NO_INT = WWDT_IIDX_STAT_NO_INTR,
|
||||
/*! WWDT interrupt index for interval timer */
|
||||
DL_WWDT_IIDX_INTERVAL_TIMER = WWDT_IIDX_STAT_INTTIM
|
||||
} DL_WWDT_IIDX;
|
||||
|
||||
/*! @enum DL_WWDT_CORE_HALT */
|
||||
typedef enum {
|
||||
/*! WWDT will halt with core */
|
||||
DL_WWDT_CORE_HALT_STOP = WWDT_PDBGCTL_FREE_STOP,
|
||||
/*! WWDT ignores the state of the core halted input */
|
||||
DL_WWDT_CORE_HALT_FREE_RUN = WWDT_PDBGCTL_FREE_RUN,
|
||||
} DL_WWDT_CORE_HALT;
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
/*!
|
||||
* @brief Initializes the Window Watchdog Timer in watchdog mode
|
||||
*
|
||||
* While in watchdog mode, the Window Watchdog Timer must be serviced
|
||||
* periodically or the device will be reset. After calling this initialization
|
||||
* API the watchdog will automatically start running with whatever window is
|
||||
* currently selected. See @ref DL_WWDT_setActiveWindow for setting the active
|
||||
* window, this is typically window 0 upon startup.
|
||||
*
|
||||
* Once running, the watchdog will need to be restarted periodically with @ref
|
||||
* DL_WWDT_restart.
|
||||
*
|
||||
* The watchdog can only be initialized once, so this API can only be called
|
||||
* once, and you may not later call @ref DL_WWDT_initIntervalTimerMode.
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for
|
||||
* peripheral
|
||||
* @param[in] divider Clock divider for the timer. One of @ref
|
||||
* DL_WWDT_CLOCK_DIVIDE.
|
||||
* @param[in] period Period for the timer. One of @ref
|
||||
* DL_WWDT_TIMER_PERIOD.
|
||||
* @param[in] sleepMode Enable/disable the timer running in sleep
|
||||
* mode. One of @ref DL_WWDT_SLEEP_MODE.
|
||||
* @param[in] window0ClosedPeriod The percentage of the total period that
|
||||
* reset window 0 should be closed. One of
|
||||
* @ref DL_WWDT_WINDOW_PERIOD.
|
||||
* @param[in] window1ClosedPeriod The percentage of the total period that
|
||||
* reset window 1 should be closed. One of
|
||||
* @ref DL_WWDT_WINDOW_PERIOD.
|
||||
*
|
||||
* @sa DL_WWDT_initIntervalTimerMode
|
||||
* @sa DL_WWDT_setActiveWindow
|
||||
* @sa DL_WWDT_restart
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_WWDT_initWatchdogMode(WWDT_Regs *wwdt,
|
||||
DL_WWDT_CLOCK_DIVIDE divider, DL_WWDT_TIMER_PERIOD period,
|
||||
DL_WWDT_SLEEP_MODE sleepMode, DL_WWDT_WINDOW_PERIOD window0ClosedPeriod,
|
||||
DL_WWDT_WINDOW_PERIOD window1ClosedPeriod)
|
||||
{
|
||||
/* Window1 is shifted because the #defines used as an input are shared
|
||||
between window 0 and window 1 */
|
||||
wwdt->WWDTCTL0 =
|
||||
(WWDT_WWDTCTL0_KEY_UNLOCK_W | (uint32_t) divider | (uint32_t) period |
|
||||
(uint32_t) sleepMode | (uint32_t) window0ClosedPeriod |
|
||||
((uint32_t) window1ClosedPeriod << 4));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Initializes the Window Watchdog Timer in interval timer mode
|
||||
*
|
||||
* The Window Watchdog Timer can be used as a simple interval timer if you do
|
||||
* not need watchdog/reset functionality. After calling this initialization
|
||||
* API the timer will automatically start running and start interrupting
|
||||
* periodically.
|
||||
*
|
||||
* The WWDT can only be initialized once, so this API can only be called once,
|
||||
* and you may not later call @ref DL_WWDT_initWatchdogMode.
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for peripheral
|
||||
* @param[in] divider Clock divider for the timer. One of
|
||||
* @ref DL_WWDT_CLOCK_DIVIDE.
|
||||
* @param[in] period Period for the timer. One of @ref
|
||||
* DL_WWDT_TIMER_PERIOD.
|
||||
* @param[in] sleepMode Enable/disable the timer running in sleep mode. One
|
||||
* of @ref DL_WWDT_SLEEP_MODE.
|
||||
*
|
||||
* @sa DL_WWDT_initWatchdogMode
|
||||
*/
|
||||
__STATIC_INLINE void DL_WWDT_initIntervalTimerMode(WWDT_Regs *wwdt,
|
||||
DL_WWDT_CLOCK_DIVIDE divider, DL_WWDT_TIMER_PERIOD period,
|
||||
DL_WWDT_SLEEP_MODE sleepMode)
|
||||
{
|
||||
wwdt->WWDTCTL0 =
|
||||
(WWDT_WWDTCTL0_KEY_UNLOCK_W | (uint32_t) divider | (uint32_t) period |
|
||||
(uint32_t) sleepMode | WWDT_WWDTCTL0_MODE_INTERVAL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Peripheral Write Enable (PWREN) register for the WWDT
|
||||
*
|
||||
* Before any peripheral registers can be configured by software, the
|
||||
* peripheral itself must be enabled by writing the ENABLE bit together with
|
||||
* the appropriate KEY value to the peripheral's PWREN register.
|
||||
*
|
||||
* @param wwdt Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_WWDT_enablePower(WWDT_Regs *wwdt)
|
||||
{
|
||||
wwdt->GPRCM.PWREN = (WWDT_PWREN_KEY_UNLOCK_W | WWDT_PWREN_ENABLE_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Peripheral Write Enable (PWREN) register for the WWDT
|
||||
*
|
||||
* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
|
||||
* accessible for read/write operations.
|
||||
*
|
||||
* @note This API does not provide large power savings.
|
||||
*
|
||||
* @param wwdt Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_WWDT_disablePower(WWDT_Regs *wwdt)
|
||||
{
|
||||
wwdt->GPRCM.PWREN = (WWDT_PWREN_KEY_UNLOCK_W | WWDT_PWREN_ENABLE_DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if the Peripheral Write Enable (PWREN) register for the WWDT
|
||||
* is enabled
|
||||
*
|
||||
* Before any peripheral registers can be configured by software, the
|
||||
* peripheral itself must be enabled by writing the ENABLE bit together with
|
||||
* the appropriate KEY value to the peripheral's PWREN register.
|
||||
*
|
||||
* When the PWREN.ENABLE bit is cleared, the peripheral's registers are not
|
||||
* accessible for read/write operations.
|
||||
*
|
||||
* @param wwdt Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return true if peripheral register access is enabled
|
||||
* @return false if peripheral register access is disabled
|
||||
*/
|
||||
__STATIC_INLINE bool DL_WWDT_isPowerEnabled(WWDT_Regs *wwdt)
|
||||
{
|
||||
return ((wwdt->GPRCM.PWREN & WWDT_PWREN_ENABLE_MASK) ==
|
||||
WWDT_PWREN_ENABLE_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets wwdt peripheral
|
||||
*
|
||||
* @param wwdt Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_WWDT_reset(WWDT_Regs *wwdt)
|
||||
{
|
||||
wwdt->GPRCM.RSTCTL =
|
||||
(WWDT_RSTCTL_KEY_UNLOCK_W | WWDT_RSTCTL_RESETSTKYCLR_CLR |
|
||||
WWDT_RSTCTL_RESETASSERT_ASSERT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns if wwdt peripheral was reset
|
||||
*
|
||||
* @param wwdt Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return true if peripheral was reset
|
||||
* @return false if peripheral wasn't reset
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE bool DL_WWDT_isReset(WWDT_Regs *wwdt)
|
||||
{
|
||||
return ((wwdt->GPRCM.STAT & WWDT_STAT_RESETSTKY_MASK) ==
|
||||
WWDT_STAT_RESETSTKY_RESET);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Restarts the Window Watchdog
|
||||
*
|
||||
* When the Window Watchdog Timer is in watchdog mode it must be periodically
|
||||
* serviced to avoid a hardware reset. This API must be called after the
|
||||
* closed window of the watchdog has passed but before the watchdog resets the
|
||||
* device.
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_WWDT_restart(WWDT_Regs *wwdt)
|
||||
{
|
||||
wwdt->WWDTCNTRST = 0x00A7;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Checks if the Window Watchdog Timer is actively running
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for peripheral
|
||||
*
|
||||
* @return Returns the running status of the Window Watchdog Timer
|
||||
*
|
||||
* @retval true The Window Watchdog Timer is running
|
||||
* @retval false The Window Watchdog Timer is not running
|
||||
*/
|
||||
__STATIC_INLINE bool DL_WWDT_isRunning(WWDT_Regs *wwdt)
|
||||
{
|
||||
return (wwdt->WWDTSTAT == WWDT_WWDTSTAT_RUN_ON);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set the active window being used
|
||||
*
|
||||
* The Window Watchdog Timer module allows you to switch between two different
|
||||
* configured windows. This allows you to configure the watchdog with two
|
||||
* different window sizes and switch between them during your application.
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for peripheral
|
||||
* @param[in] window The window to set as active. One of @ref
|
||||
* DL_WWDT_WINDOW.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_WWDT_setActiveWindow(
|
||||
WWDT_Regs *wwdt, DL_WWDT_WINDOW window)
|
||||
{
|
||||
wwdt->WWDTCTL1 = (WWDT_WWDTCTL1_KEY_UNLOCK_W | (uint32_t) window);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the active window being used
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for peripheral
|
||||
*
|
||||
* @return The active window being used
|
||||
*
|
||||
* @retval One of @ref DL_WWDT_WINDOW
|
||||
*/
|
||||
__STATIC_INLINE DL_WWDT_WINDOW DL_WWDT_getActiveWindow(WWDT_Regs *wwdt)
|
||||
{
|
||||
uint32_t window = (wwdt->WWDTCTL1 & WWDT_WWDTCTL1_WINSEL_MASK);
|
||||
|
||||
return (DL_WWDT_WINDOW)(window);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the sleep mode being used
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for peripheral
|
||||
*
|
||||
* @return The current sleep mode
|
||||
*
|
||||
* @retval One of @ref DL_WWDT_SLEEP_MODE
|
||||
*/
|
||||
__STATIC_INLINE DL_WWDT_SLEEP_MODE DL_WWDT_getSleepMode(WWDT_Regs *wwdt)
|
||||
{
|
||||
uint32_t mode = (wwdt->WWDTCTL0 & WWDT_WWDTCTL0_STISM_MASK);
|
||||
|
||||
return (DL_WWDT_SLEEP_MODE)(mode);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the mode the watchdog is running in
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for peripheral
|
||||
*
|
||||
* @return The current mode the watchdog is running in
|
||||
*
|
||||
* @retval One of @ref DL_WWDT_MODE
|
||||
*/
|
||||
__STATIC_INLINE DL_WWDT_MODE DL_WWDT_getMode(WWDT_Regs *wwdt)
|
||||
{
|
||||
uint32_t mode = (wwdt->WWDTCTL0 & WWDT_WWDTCTL0_MODE_MASK);
|
||||
|
||||
return (DL_WWDT_MODE)(mode);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the window closed percentage for a watchdog window
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for peripheral
|
||||
* @param[in] window The window to get the closed window percentage of. One
|
||||
* of @ref DL_WWDT_WINDOW.
|
||||
*
|
||||
* @return The desired window's closed percentage
|
||||
*
|
||||
* @retval One of @ref DL_WWDT_WINDOW_PERIOD
|
||||
*/
|
||||
__STATIC_INLINE DL_WWDT_WINDOW_PERIOD DL_WWDT_getWindowPeriod(
|
||||
WWDT_Regs *wwdt, DL_WWDT_WINDOW window)
|
||||
{
|
||||
uint32_t period;
|
||||
|
||||
if (window == DL_WWDT_WINDOW0) {
|
||||
period = (wwdt->WWDTCTL0 & WWDT_WWDTCTL0_WINDOW0_MASK);
|
||||
} else {
|
||||
period = ((wwdt->WWDTCTL0 & WWDT_WWDTCTL0_WINDOW1_MASK) >> 4);
|
||||
}
|
||||
|
||||
return (DL_WWDT_WINDOW_PERIOD)(period);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the timer period for the watchdog
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for peripheral
|
||||
*
|
||||
* @return The current timer period for the watchdog
|
||||
*
|
||||
* @retval One of @ref DL_WWDT_TIMER_PERIOD
|
||||
*/
|
||||
__STATIC_INLINE DL_WWDT_TIMER_PERIOD DL_WWDT_getTimerPeriod(WWDT_Regs *wwdt)
|
||||
{
|
||||
uint32_t period = (wwdt->WWDTCTL0 & WWDT_WWDTCTL0_PER_MASK);
|
||||
|
||||
return (DL_WWDT_TIMER_PERIOD)(period);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the clock divider for the watchdog
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for peripheral
|
||||
*
|
||||
* @return The current clock divider used
|
||||
*
|
||||
* @retval One of @ref DL_WWDT_CLOCK_DIVIDE
|
||||
*/
|
||||
__STATIC_INLINE DL_WWDT_CLOCK_DIVIDE DL_WWDT_getClockDivider(WWDT_Regs *wwdt)
|
||||
{
|
||||
uint32_t clockDivider = (wwdt->WWDTCTL0 & WWDT_WWDTCTL0_CLKDIV_MASK);
|
||||
|
||||
return (DL_WWDT_CLOCK_DIVIDE)(clockDivider);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable WWDT interrupt
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_WWDT_enableInterrupt(WWDT_Regs *wwdt)
|
||||
{
|
||||
wwdt->CPU_INT.IMASK = WWDT_IMASK_INTTIM_SET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable WWDT interrupt
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_WWDT_disableInterrupt(WWDT_Regs *wwdt)
|
||||
{
|
||||
wwdt->CPU_INT.IMASK = WWDT_IMASK_INTTIM_CLR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if WWDT interrupt is enabled
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return If the WWDT interrupt is enabled
|
||||
*
|
||||
* @retval true The WWDT interrupt is enabled
|
||||
* @retval false The WWDT interrupt is disabled
|
||||
*/
|
||||
__STATIC_INLINE bool DL_WWDT_isInterruptEnabled(WWDT_Regs *wwdt)
|
||||
{
|
||||
return ((wwdt->CPU_INT.IMASK & WWDT_IMASK_INTTIM_SET) ==
|
||||
WWDT_IMASK_INTTIM_SET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check interrupt flag of enabled WWDT interrupt
|
||||
*
|
||||
* Checks if the WWDT interrupt that was previously enabled is pending.
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return If the enabled WWDT interrupt is pending
|
||||
*
|
||||
* @retval true The WWDT interrupt is pending
|
||||
* @retval false The WWDT interrupt is not pending
|
||||
*
|
||||
* @sa DL_WWDT_enableInterrupt
|
||||
*/
|
||||
__STATIC_INLINE bool DL_WWDT_getEnabledInterruptStatus(WWDT_Regs *wwdt)
|
||||
{
|
||||
return ((wwdt->CPU_INT.MIS & WWDT_MIS_INTTIM_SET) == WWDT_MIS_INTTIM_SET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check interrupt flag of any WWDT interrupt
|
||||
*
|
||||
* Checks if the WWDT interrupt is pending. Interrupt does not have to
|
||||
* be previously enabled.
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return If the WWDT interrupt is pending
|
||||
*
|
||||
* @retval true The WWDT interrupt is pending
|
||||
* @retval false The WWDT interrupt is not pending
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_WWDT_getRawInterruptStatus(WWDT_Regs *wwdt)
|
||||
{
|
||||
return (wwdt->CPU_INT.RIS & WWDT_RIS_INTTIM_SET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get highest priority pending WWDT interrupt
|
||||
*
|
||||
* Checks if any of the WWDT interrupts are pending. Interrupts do not have to
|
||||
* be previously enabled.
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return The highest priority pending WWDT interrupt
|
||||
*
|
||||
* @retval One of @ref DL_WWDT_IIDX
|
||||
*/
|
||||
__STATIC_INLINE DL_WWDT_IIDX DL_WWDT_getPendingInterrupt(WWDT_Regs *wwdt)
|
||||
{
|
||||
return (DL_WWDT_IIDX)(wwdt->CPU_INT.IIDX);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear pending WWDT interrupt
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for the peripheral
|
||||
*/
|
||||
__STATIC_INLINE void DL_WWDT_clearInterruptStatus(WWDT_Regs *wwdt)
|
||||
{
|
||||
wwdt->CPU_INT.ICLR = WWDT_ICLR_INTTIM_CLR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures WWDT behavior when the core is halted.
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @param[in] haltMode WWDT halt behavior. One of @ref DL_WWDT_CORE_HALT.
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_WWDT_setCoreHaltBehavior(
|
||||
WWDT_Regs *wwdt, DL_WWDT_CORE_HALT haltMode)
|
||||
{
|
||||
wwdt->PDBGCTL = (uint32_t) haltMode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get WWDT behavior when the core is halted.
|
||||
*
|
||||
* @param[in] wwdt Pointer to the register overlay for the peripheral
|
||||
*
|
||||
* @return WWDT bahvior when core is halted. One of
|
||||
* @ref DL_WWDT_CORE_HALT
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE DL_WWDT_CORE_HALT DL_WWDT_getCoreHaltBehavior(WWDT_Regs *wwdt)
|
||||
{
|
||||
uint32_t haltMode = (wwdt->PDBGCTL & WWDT_PDBGCTL_FREE_MASK);
|
||||
return (DL_WWDT_CORE_HALT) haltMode;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MSPM0_HAS_WWDT__ */
|
||||
|
||||
#endif /* ti_dl_dl_wwdt__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,75 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef ti_dl_dl_driverlib__include
|
||||
#define ti_dl_dl_driverlib__include
|
||||
|
||||
#include <ti/driverlib/dl_adc12.h>
|
||||
#include <ti/driverlib/dl_aes.h>
|
||||
#include <ti/driverlib/dl_aesadv.h>
|
||||
#include <ti/driverlib/dl_common.h>
|
||||
#include <ti/driverlib/dl_comp.h>
|
||||
#include <ti/driverlib/dl_crc.h>
|
||||
#include <ti/driverlib/dl_crcp.h>
|
||||
#include <ti/driverlib/dl_dac12.h>
|
||||
#include <ti/driverlib/dl_dma.h>
|
||||
#include <ti/driverlib/dl_flashctl.h>
|
||||
#include <ti/driverlib/dl_gpamp.h>
|
||||
#include <ti/driverlib/dl_gpio.h>
|
||||
#include <ti/driverlib/dl_i2c.h>
|
||||
#include <ti/driverlib/dl_iwdt.h>
|
||||
#include <ti/driverlib/dl_keystorectl.h>
|
||||
#include <ti/driverlib/dl_lcd.h>
|
||||
#include <ti/driverlib/dl_lfss.h>
|
||||
#include <ti/driverlib/dl_mathacl.h>
|
||||
#include <ti/driverlib/dl_mcan.h>
|
||||
#include <ti/driverlib/dl_opa.h>
|
||||
#include <ti/driverlib/dl_rtc.h>
|
||||
#include <ti/driverlib/dl_rtc_a.h>
|
||||
#include <ti/driverlib/dl_rtc_b.h>
|
||||
#include <ti/driverlib/dl_rtc_common.h>
|
||||
#include <ti/driverlib/dl_scratchpad.h>
|
||||
#include <ti/driverlib/dl_spi.h>
|
||||
#include <ti/driverlib/dl_tamperio.h>
|
||||
#include <ti/driverlib/dl_timera.h>
|
||||
#include <ti/driverlib/dl_timerg.h>
|
||||
#include <ti/driverlib/dl_trng.h>
|
||||
#include <ti/driverlib/dl_uart_extend.h>
|
||||
#include <ti/driverlib/dl_uart_main.h>
|
||||
#include <ti/driverlib/dl_vref.h>
|
||||
#include <ti/driverlib/dl_wwdt.h>
|
||||
#include <ti/driverlib/m0p/dl_factoryregion.h>
|
||||
#include <ti/driverlib/m0p/dl_interrupt.h>
|
||||
#include <ti/driverlib/m0p/dl_sysctl.h>
|
||||
#include <ti/driverlib/m0p/dl_systick.h>
|
||||
|
||||
#endif /* ti_dl_dl_driverlib__include */
|
||||
Binary file not shown.
@@ -0,0 +1,215 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_core.h
|
||||
* @brief CPU Core Driver Library
|
||||
* @defgroup CORE M0P Core
|
||||
*
|
||||
* @anchor ti_dl_m0p_dl_core_Overview
|
||||
* # Overview
|
||||
*
|
||||
* The Core module enables software to read from core registers of the CPU to
|
||||
* get more information about the device at runtime.
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup CORE
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_m0p_dl_core__include
|
||||
#define ti_dl_m0p_dl_core__include
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/** @addtogroup DL_CORE_CACHE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables instruction caching on flash access
|
||||
*/
|
||||
#define DL_CORE_CACHE_ENABLED (CPUSS_CTL_ICACHE_ENABLE)
|
||||
|
||||
/*!
|
||||
* @brief Disables instruction caching on flash access
|
||||
*/
|
||||
#define DL_CORE_CACHE_DISABLED (CPUSS_CTL_ICACHE_DISABLE)
|
||||
|
||||
/** @}*/
|
||||
|
||||
/** @addtogroup DL_CORE_PREFETCH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables instruction prefetch to Flash
|
||||
*/
|
||||
#define DL_CORE_PREFETCH_ENABLED (CPUSS_CTL_PREFETCH_ENABLE)
|
||||
|
||||
/*!
|
||||
* @brief Disables instruction prefetch to Flash
|
||||
*/
|
||||
#define DL_CORE_PREFETCH_DISABLED (CPUSS_CTL_PREFETCH_DISABLE)
|
||||
|
||||
/** @}*/
|
||||
|
||||
/** @addtogroup DL_CORE_LITERAL_CACHE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables caching and prefetching of literals.
|
||||
* This is set only if the ICACHE or PREFETCH bits have been set respectively.
|
||||
*/
|
||||
#define DL_CORE_LITERAL_CACHE_ENABLED (CPUSS_CTL_LITEN_ENABLE)
|
||||
|
||||
/*!
|
||||
* @brief Disables caching and prefetching of literals
|
||||
*/
|
||||
#define DL_CORE_LITERAL_CACHE_DISABLED (CPUSS_CTL_LITEN_DISABLE)
|
||||
|
||||
/** @}*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Alias for DL_Common_delayCycles
|
||||
*/
|
||||
#define delay_cycles(cycles) DL_Common_delayCycles(cycles)
|
||||
|
||||
/** @}*/
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the implementer code for the processor
|
||||
*
|
||||
* @return The implementer code
|
||||
*
|
||||
* @retval 0x41 for ARM
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_CORE_getImplementer(void)
|
||||
{
|
||||
return (
|
||||
(SCB->CPUID & SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the major revision number 'n' in the 'npm' revision status
|
||||
*
|
||||
* @return The major revision number
|
||||
*
|
||||
* @retval 0x00 for revision 0
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_CORE_getVariant(void)
|
||||
{
|
||||
return ((SCB->CPUID & SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the architecture of the processor
|
||||
*
|
||||
* @return Value that defines the architecture of the processor
|
||||
*
|
||||
* @retval 0x0C for ARMv6-M architecture
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_CORE_getArchitecture(void)
|
||||
{
|
||||
return ((SCB->CPUID & SCB_CPUID_ARCHITECTURE_Msk) >>
|
||||
SCB_CPUID_ARCHITECTURE_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get part number of the processor (not the device)
|
||||
*
|
||||
* @return Value that defines the processor
|
||||
*
|
||||
* @retval 0x0C60 for Cortex-M0+
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_CORE_getPartNumber(void)
|
||||
{
|
||||
return ((SCB->CPUID & SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the minor revision number 'm' in the 'npm' revision status
|
||||
*
|
||||
* @return The minor revision number
|
||||
*
|
||||
* @retval 0x01 for patch 1
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_CORE_getRevision(void)
|
||||
{
|
||||
return ((SCB->CPUID & (uint32_t)SCB_CPUID_REVISION_Msk) >> (uint32_t)SCB_CPUID_REVISION_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures instruction caching in flash accesses and instruction
|
||||
* prefetch to flash
|
||||
*
|
||||
* @param icache [in] Instruction cache option @ref DL_CORE_CACHE
|
||||
* @param prefetch [in] Instruction prefetch option @ref DL_CORE_PREFETCH
|
||||
* @param litCache [in] Literal cache option @ref DL_CORE_LITERAL_CACHE
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void DL_CORE_configInstruction(uint32_t icache, uint32_t prefetch, uint32_t litCache)
|
||||
{
|
||||
CPUSS->CTL = (icache | prefetch | litCache);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns instruction caching, prefetch, and literal cache configuration
|
||||
*
|
||||
* @return Bitwise OR of @ref DL_CORE_CACHE and @ref DL_CORE_PREFETCH and
|
||||
* @ref DL_CORE_LITERAL_CACHE
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_CORE_getInstructionConfig(void)
|
||||
{
|
||||
return(CPUSS->CTL & (CPUSS_CTL_ICACHE_MASK | CPUSS_CTL_PREFETCH_MASK | CPUSS_CTL_LITEN_MASK));
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* ti_dl_m0p_dl_core__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright (c) 2024, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/driverlib/m0p/dl_factoryregion.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0GX51X)
|
||||
|
||||
/* Creating a section for structure inside SRAM*/
|
||||
__attribute__((section(".TrimTable")))
|
||||
DL_FACTORYREGION_TrimValues DL_FACTORYREGION_TrimTable;
|
||||
/* Creating a pointer to the structure placed inside SRAM*/
|
||||
DL_FACTORYREGION_TrimValues *FACTORYVALUE = &DL_FACTORYREGION_TrimTable;
|
||||
|
||||
void DL_FactoryRegion_initTrimTable(void)
|
||||
{
|
||||
DL_FACTORYREGION_TrimTable.TRACEID = FACTORYREGION->TRACEID;
|
||||
DL_FACTORYREGION_TrimTable.DEVICEID = FACTORYREGION->DEVICEID;
|
||||
DL_FACTORYREGION_TrimTable.USERID = FACTORYREGION->USERID;
|
||||
DL_FACTORYREGION_TrimTable.BSLPIN_UART = FACTORYREGION->BSLPIN_UART;
|
||||
DL_FACTORYREGION_TrimTable.BSLPIN_I2C = FACTORYREGION->BSLPIN_I2C;
|
||||
DL_FACTORYREGION_TrimTable.BSLPIN_INVOKE = FACTORYREGION->BSLPIN_INVOKE;
|
||||
DL_FACTORYREGION_TrimTable.SRAMFLASH = FACTORYREGION->SRAMFLASH;
|
||||
DL_FACTORYREGION_TrimTable.PLLSTARTUP0_4_8MHZ =
|
||||
FACTORYREGION->PLLSTARTUP0_4_8MHZ;
|
||||
DL_FACTORYREGION_TrimTable.PLLSTARTUP1_4_8MHZ =
|
||||
FACTORYREGION->PLLSTARTUP1_4_8MHZ;
|
||||
DL_FACTORYREGION_TrimTable.PLLSTARTUP0_8_16MHZ =
|
||||
FACTORYREGION->PLLSTARTUP0_8_16MHZ;
|
||||
DL_FACTORYREGION_TrimTable.PLLSTARTUP1_8_16MHZ =
|
||||
FACTORYREGION->PLLSTARTUP1_8_16MHZ;
|
||||
DL_FACTORYREGION_TrimTable.PLLSTARTUP0_16_32MHZ =
|
||||
FACTORYREGION->PLLSTARTUP0_16_32MHZ;
|
||||
DL_FACTORYREGION_TrimTable.PLLSTARTUP1_16_32MHZ =
|
||||
FACTORYREGION->PLLSTARTUP1_16_32MHZ;
|
||||
DL_FACTORYREGION_TrimTable.PLLSTARTUP0_32_48MHZ =
|
||||
FACTORYREGION->PLLSTARTUP0_32_48MHZ;
|
||||
DL_FACTORYREGION_TrimTable.PLLSTARTUP1_32_48MHZ =
|
||||
FACTORYREGION->PLLSTARTUP1_32_48MHZ;
|
||||
DL_FACTORYREGION_TrimTable.TEMP_SENSE0 = FACTORYREGION->TEMP_SENSE0;
|
||||
DL_FACTORYREGION_TrimTable.DATA_SET = DL_FACTORYREGION_TRIM_FLAG_IS_SET;
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/driverlib/m0p/dl_interrupt.h>
|
||||
|
||||
/* 32 Device Peripheral Exceptions + 16 reserved M0+ Exceptions */
|
||||
#define NUM_RES_M0_EXC ((uint32_t) 16)
|
||||
#define NUM_DEV_PERIPH_EXC ((uint32_t) 32)
|
||||
#define NUM_INTERRUPTS (NUM_RES_M0_EXC + NUM_DEV_PERIPH_EXC)
|
||||
|
||||
#if defined(__IAR_SYSTEMS_ICC__)
|
||||
#pragma data_alignment = 256
|
||||
static __no_init void (*InterruptRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
|
||||
#else
|
||||
static __attribute__((section(".vtable"))) void (
|
||||
*InterruptRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(256)));
|
||||
#endif
|
||||
void DL_Interrupt_registerInterrupt(
|
||||
uint32_t exceptionNumber, void (*intHandler)(void))
|
||||
{
|
||||
void (**baseAddress)(void);
|
||||
uint32_t i;
|
||||
|
||||
/* See if the RAM vector table has been initialized */
|
||||
if (SCB->VTOR != (uint32_t) InterruptRAMVectors) {
|
||||
baseAddress = (void (**)(void)) SCB->VTOR;
|
||||
|
||||
/* Copy the vector table from Flash to RAM */
|
||||
for (i = 0; i < NUM_INTERRUPTS; i++) {
|
||||
InterruptRAMVectors[i] = baseAddress[i];
|
||||
}
|
||||
|
||||
SCB->VTOR = (uint32_t) InterruptRAMVectors;
|
||||
}
|
||||
|
||||
InterruptRAMVectors[exceptionNumber + NUM_RES_M0_EXC] = intHandler;
|
||||
}
|
||||
|
||||
void DL_Interrupt_unregisterInterrupt(uint32_t exceptionNumber)
|
||||
{
|
||||
InterruptRAMVectors[exceptionNumber + NUM_RES_M0_EXC] = Default_Handler;
|
||||
}
|
||||
@@ -0,0 +1,353 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_interrupt.h
|
||||
* @brief Interrupt Management Driver Library
|
||||
* @defgroup INTERRUPT M0P Interrupts
|
||||
*
|
||||
* @anchor ti_dl_m0p_dl_interrupt_Overview
|
||||
* # Overview
|
||||
*
|
||||
* The Cortex-M0+ architecture is limited to 32 device interrupts. To enable
|
||||
* interrupt handling on devices that need more than 32 interrupts, the
|
||||
* interrupts are grouped together.
|
||||
*
|
||||
* For example, "Group 0" contains the interrupt flags for the WWDT0, WWDT1,
|
||||
* DEBUGSS, FLASH, and SYSCTL peripherals. Once the interrupt fires for Group 0,
|
||||
* the application must check to see which peripheral from Group 0 was the
|
||||
* source using the APIs in this module.
|
||||
*
|
||||
* This PI module is not for controlling the NVIC or the I-bit in the CPSR
|
||||
* register. It's best to use the CMSIS-Core APIs that are delivered as part
|
||||
* of CMSIS-Core in the `source/third_party/CMSIS/Core/Include/core_cm0plus.h`
|
||||
* file within the SDK.
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup INTERRUPT
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_m0p_dl_interrupt__include
|
||||
#define ti_dl_m0p_dl_interrupt__include
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
#include <ti/devices/msp/peripherals/m0p/hw_cpuss.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/** @addtogroup DL_INTERRUPT_GROUP_IIDX
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief WWDT0 Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_IIDX_WWDT0 (CPUSS_INT_GROUP_IIDX_STAT_INT0)
|
||||
|
||||
/*!
|
||||
* @brief WWDT1 Interrupt in Group 0.
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 0 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_IIDX_WWDT1 (CPUSS_INT_GROUP_IIDX_STAT_INT1)
|
||||
|
||||
/*!
|
||||
* @brief DEBUGSS Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_IIDX_DEBUGSS (CPUSS_INT_GROUP_IIDX_STAT_INT2)
|
||||
|
||||
/*!
|
||||
* @brief FLASH Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_IIDX_FLASH (CPUSS_INT_GROUP_IIDX_STAT_INT3)
|
||||
|
||||
/*!
|
||||
* @brief WUC FSUB0 Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_IIDX_WUC_FSUB0 (CPUSS_INT_GROUP_IIDX_STAT_INT4)
|
||||
|
||||
/*!
|
||||
* @brief WUC FSUB0 Interrupt in Group 1
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_IIDX_WUC_FSUB1 (CPUSS_INT_GROUP_IIDX_STAT_INT5)
|
||||
|
||||
/*!
|
||||
* @brief SYSCTL (PMCU) Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_IIDX_SYSCTL (CPUSS_INT_GROUP_IIDX_STAT_INT6)
|
||||
|
||||
/*!
|
||||
* @brief GPIOA Interrupt in Group 1
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_IIDX_GPIOA (CPUSS_INT_GROUP_IIDX_STAT_INT0)
|
||||
|
||||
/*!
|
||||
* @brief GPIOB Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_IIDX_GPIOB (CPUSS_INT_GROUP_IIDX_STAT_INT1)
|
||||
|
||||
/*!
|
||||
* @brief COMP0 Interrupt in Group 1
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_IIDX_COMP0 (CPUSS_INT_GROUP_IIDX_STAT_INT2)
|
||||
|
||||
/*!
|
||||
* @brief COMP1 Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_IIDX_COMP1 (CPUSS_INT_GROUP_IIDX_STAT_INT3)
|
||||
|
||||
/*!
|
||||
* @brief COMP2 Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_IIDX_COMP2 (CPUSS_INT_GROUP_IIDX_STAT_INT4)
|
||||
|
||||
/*!
|
||||
* @brief TRNG Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_IIDX_TRNG (CPUSS_INT_GROUP_IIDX_STAT_INT5)
|
||||
|
||||
/*!
|
||||
* @brief GPIOC Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_IIDX_GPIOC (CPUSS_INT_GROUP_IIDX_STAT_INT6)
|
||||
|
||||
/** @}*/
|
||||
|
||||
/** @addtogroup DL_INTERRUPT_GROUP_INTERRUPTS
|
||||
* @{
|
||||
*/
|
||||
/*!
|
||||
* @brief WWDT0 Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_WWDT0 (CPUSS_INT_GROUP_IMASK_INT_INT0)
|
||||
/*!
|
||||
* @brief WWDT1 Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_WWDT1 (CPUSS_INT_GROUP_IMASK_INT_INT1)
|
||||
/*!
|
||||
* @brief DEBUGSS Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_DEBUGSS (CPUSS_INT_GROUP_IMASK_INT_INT2)
|
||||
/*!
|
||||
* @brief FLASH Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_FLASH (CPUSS_INT_GROUP_IMASK_INT_INT3)
|
||||
/*!
|
||||
* @brief Generic event subscriber 0 in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_WUC_FSUB0 (CPUSS_INT_GROUP_IMASK_INT_INT4)
|
||||
/*!
|
||||
* @brief Generic event subscriber 1 in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_WUC_FSUB1 (CPUSS_INT_GROUP_IMASK_INT_INT5)
|
||||
/*!
|
||||
* @brief PMCU (system controller) in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_PMCU (CPUSS_INT_GROUP_IMASK_INT_INT6)
|
||||
|
||||
/*!
|
||||
* @brief GPIOA Interrupt in Group 1
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_GPIOA (CPUSS_INT_GROUP_IMASK_INT_INT0)
|
||||
/*!
|
||||
* @brief GPIOB Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_GPIOB (CPUSS_INT_GROUP_IMASK_INT_INT1)
|
||||
/*!
|
||||
* @brief COMP0 Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_COMP0 (CPUSS_INT_GROUP_IMASK_INT_INT2)
|
||||
/*!
|
||||
* @brief COMP1 Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_COMP1 (CPUSS_INT_GROUP_IMASK_INT_INT3)
|
||||
/*!
|
||||
* @brief COMP2 Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_COMP2 (CPUSS_INT_GROUP_IMASK_INT_INT4)
|
||||
/*!
|
||||
* @brief TRNG Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_TRNG (CPUSS_INT_GROUP_IMASK_INT_INT5)
|
||||
|
||||
/** @}*/
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
/*! @enum DL_INTERRUPT_GROUP */
|
||||
typedef enum {
|
||||
/*! Selects interrupt group 0 */
|
||||
DL_INTERRUPT_GROUP_0 = 0,
|
||||
/*! Selects interrupt group 1 */
|
||||
DL_INTERRUPT_GROUP_1 = 1
|
||||
} DL_INTERRUPT_GROUP;
|
||||
|
||||
/**
|
||||
* @brief Device default Handler
|
||||
*
|
||||
* This function is defined as part of the device startup file.
|
||||
*/
|
||||
extern void Default_Handler(void);
|
||||
|
||||
/**
|
||||
* @brief Checks interrupt flag status in the selected group of interrupts
|
||||
*
|
||||
* Checks if any of the interrupts in the group are pending. When calling the
|
||||
* function, ensure that the interrupts passed in the mask are applicable to
|
||||
* the requested interrupt group.
|
||||
*
|
||||
* @param[in] group Group of interrupts to check.
|
||||
* @ref DL_INTERRUPT_GROUP
|
||||
* @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of
|
||||
* @ref DL_INTERRUPT_GROUP_INTERRUPTS.
|
||||
*
|
||||
* @return Which of the requested group interrupts are pending
|
||||
*
|
||||
* @retval Bitwise OR of @ref DL_INTERRUPT_GROUP_INTERRUPTS values
|
||||
*/
|
||||
static inline uint32_t DL_Interrupt_getStatusGroup(
|
||||
DL_INTERRUPT_GROUP group, uint32_t interruptMask)
|
||||
{
|
||||
return (CPUSS->INT_GROUP[(uint32_t) group].RIS & interruptMask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get highest priority interrupt pending in the selected interrupt
|
||||
* group
|
||||
*
|
||||
* @param[in] group Group of interrupts to check
|
||||
*
|
||||
* @return The highest priority pending interrupt for the group requested.
|
||||
* One of @ref DL_INTERRUPT_GROUP_IIDX
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_Interrupt_getPendingGroup(DL_INTERRUPT_GROUP group)
|
||||
{
|
||||
return (CPUSS->INT_GROUP[group].IIDX);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear selected interrupt flags in the selected interrupt group
|
||||
*
|
||||
* Clears any of the desired interrupts in the group. When calling the
|
||||
* function, ensure that the interrupts passed in the mask are applicable to
|
||||
* the requested interrupt group.
|
||||
*
|
||||
* @param[in] group Group of interrupts to check.
|
||||
* @ref DL_INTERRUPT_GROUP
|
||||
* @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of
|
||||
* @ref DL_INTERRUPT_GROUP_INTERRUPTS.
|
||||
*/
|
||||
static inline void DL_Interrupt_clearGroup(
|
||||
DL_INTERRUPT_GROUP group, uint32_t interruptMask)
|
||||
{
|
||||
CPUSS->INT_GROUP[(uint32_t) group].ICLR |= interruptMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register a function to be called when an interrupt occurs
|
||||
*
|
||||
* This allows you to register a function to be called during an interrupt,
|
||||
* allowing you to override the interrupt handler at run time. The function
|
||||
* moves the interrupt vector table from Flash to SRAM so that the interrupt
|
||||
* handler functions can be overwritten.
|
||||
*
|
||||
* This function should only be used if the application requires specifying
|
||||
* the interrupt handler at run time. If it does not need to be changed at
|
||||
* run time consider placing the ISR function pointer in the startup file to
|
||||
* link the function into the interrupt table.
|
||||
*
|
||||
* Example of usage:
|
||||
* @code
|
||||
* DL_Interrupt_registerInterrupt(TIMA0_INT_IRQn, redirectedInterruptHandler);
|
||||
* @endcode
|
||||
*
|
||||
* @param[in] exceptionNumber The interrupt number to register the handler.
|
||||
* Interrupt numbers are device specific, please
|
||||
* consult the device datasheet for valid
|
||||
* interrupt numbers.
|
||||
* @param[in] intHandler A pointer to a function to call for the desired
|
||||
* interrupt
|
||||
*/
|
||||
void DL_Interrupt_registerInterrupt(
|
||||
uint32_t exceptionNumber, void (*intHandler)(void));
|
||||
|
||||
/**
|
||||
* @brief Unregister a function to be called when an interrupt occurs
|
||||
*
|
||||
* Overrides the registered interrupt function to jump into a simple while(1)
|
||||
* loop rather than the previously registered interrupt function. Requires
|
||||
* that @ref DL_Interrupt_registerInterrupt was previously called so that the
|
||||
* interrupt vector table has been moved to RAM.
|
||||
*
|
||||
* Example of usage:
|
||||
* @code DL_Interrupt_unregisterInterrupt(TIMA0_INT_IRQn); @endcode
|
||||
*
|
||||
* @param[in] exceptionNumber The interrupt number to unregister.
|
||||
* Interrupt numbers are device specific, please
|
||||
* consult the device datasheet for valid
|
||||
* interrupt numbers.
|
||||
*/
|
||||
void DL_Interrupt_unregisterInterrupt(uint32_t exceptionNumber);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ti_dl_m0p_dl_interrupt__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,75 @@
|
||||
/*****************************************************************************
|
||||
|
||||
Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions
|
||||
are met:
|
||||
|
||||
Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
Neither the name of Texas Instruments Incorporated nor the names of
|
||||
its contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*****************************************************************************/
|
||||
/* This file automatically includes the specific device header file
|
||||
without the need to include a specific device header.
|
||||
The device #define is set automatically through the toolchain on basis
|
||||
of the device chosen in the device selection menu (.e.g -D__MICRO1__). */
|
||||
/** @defgroup SYSCTL M0P System Control (SYSCTL) */
|
||||
/** @addtogroup SYSCTL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef ti_driverlib_m0p_sysctl__include
|
||||
#define ti_driverlib_m0p_sysctl__include
|
||||
|
||||
/******************************************************************************
|
||||
* MSP devices
|
||||
******************************************************************************/
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G1X0X_G3X0X)
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g1x0x_g3x0x.h>
|
||||
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L11XX_L13XX)
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l11xx_l13xx.h>
|
||||
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0C110X) || \
|
||||
(DeviceFamily_PARENT == DeviceFamily_PARENT_MSPS003FX)
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0c110x.h>
|
||||
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L122X_L222X)
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l122x_l222x.h>
|
||||
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0GX51X)
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0gx51x.h>
|
||||
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L111X)
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l111x.h>
|
||||
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0H321X)
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0h321x.h>
|
||||
|
||||
/********************************************************************
|
||||
*
|
||||
********************************************************************/
|
||||
#else
|
||||
#error "Failed to match a default include file"
|
||||
#endif
|
||||
|
||||
#endif /* ti_driverlib_m0p_sysctl__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,193 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_systick.h
|
||||
* @brief System Tick Timer (SysTick) Driver Library
|
||||
* @defgroup SYSTICK M0P System Tick Timer (SysTick)
|
||||
*
|
||||
* @anchor ti_dl_m0p_dl_systick_Overview
|
||||
* # Overview
|
||||
*
|
||||
* SysTick is a simple timer that is part of the Cortex-M architecture. Its
|
||||
* intended purpose is to provide a periodic interrupt for an RTOS, but it can
|
||||
* be used for other simple timing purposes.
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup SYSTICK
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_m0p_dl_systick__include
|
||||
#define ti_dl_m0p_dl_systick__include
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/**
|
||||
* @brief Redirects DL_SYSTICK_config to CMSIS standard SysTick_Config
|
||||
*/
|
||||
#define DL_SYSTICK_config(x) SysTick_Config(x)
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
/**
|
||||
* @brief Initializes the System Tick Timer (SysTick)
|
||||
*
|
||||
* Initializes the System Tick Timer by configuring the desired period. Resets
|
||||
* the counter so that, once enabled, the SysTick starts counting from 0. Does
|
||||
* not start the timer or enable the interrupt.
|
||||
*
|
||||
* @param[in] period The period in ticks for the SysTick to fire. Value
|
||||
* between 0x00000002 - 0x01000000.
|
||||
*/
|
||||
__STATIC_INLINE void DL_SYSTICK_init(uint32_t period)
|
||||
{
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk;
|
||||
SysTick->LOAD = period - (uint32_t) 1;
|
||||
SysTick->VAL = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the period for the SysTick
|
||||
*
|
||||
* Calling this function does not cause the SysTick counter to reload
|
||||
* immediately. If you want to change the period and reset the counter use
|
||||
* the @ref DL_SYSTICK_init function or @ref DL_SYSTICK_resetValue.
|
||||
*
|
||||
* @param[in] period The period in ticks for the SysTick to fire. Value
|
||||
* between 0x00000002 - 0x01000000.
|
||||
*/
|
||||
__STATIC_INLINE void DL_SYSTICK_setPeriod(uint32_t period)
|
||||
{
|
||||
SysTick->LOAD = period - (uint32_t) 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the current value of the SysTick
|
||||
*
|
||||
* Resets the current value of the SysTick back to 0, essentially resetting
|
||||
* the period.
|
||||
*/
|
||||
__STATIC_INLINE void DL_SYSTICK_resetValue(void)
|
||||
{
|
||||
SysTick->VAL = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the period for the SysTick
|
||||
*
|
||||
* @return The period in ticks for the SysTick to fire
|
||||
*
|
||||
* @retval Value between 0x00000002 - 0x01000000.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_SYSTICK_getPeriod(void)
|
||||
{
|
||||
return (SysTick->LOAD + (uint32_t) 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the current value of SysTick counter
|
||||
*
|
||||
* @return The current value of the counter in ticks
|
||||
*
|
||||
* @retval Value between 0x00000000 - 0x00FFFFFF.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_SYSTICK_getValue(void)
|
||||
{
|
||||
return SysTick->VAL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the SysTick interrupt
|
||||
*/
|
||||
__STATIC_INLINE void DL_SYSTICK_enableInterrupt(void)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the SysTick interrupt
|
||||
*/
|
||||
__STATIC_INLINE void DL_SYSTICK_disableInterrupt(void)
|
||||
{
|
||||
SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the SysTick, starts counting once enabled
|
||||
*
|
||||
* Once enabled, the SysTick will start counting from whatever value it was
|
||||
* disabled with. To ensure a full period, use @ref DL_SYSTICK_init
|
||||
* or @ref DL_SYSTICK_resetValue before enabling.
|
||||
*/
|
||||
__STATIC_INLINE void DL_SYSTICK_enable(void)
|
||||
{
|
||||
SysTick->CTRL |= (SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the SysTick, stops counting once disabled
|
||||
*/
|
||||
__STATIC_INLINE void DL_SYSTICK_disable(void)
|
||||
{
|
||||
SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if the SysTick is enabled
|
||||
*
|
||||
* @return Returns the enabled status of the SysTick
|
||||
*
|
||||
* @retval true The SysTick is enabled and counting
|
||||
* @retval false The SysTick is disabled and not counting
|
||||
*/
|
||||
__STATIC_INLINE bool DL_SYSTICK_isEnabled(void)
|
||||
{
|
||||
return (
|
||||
(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) == SysTick_CTRL_ENABLE_Msk);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ti_dl_m0p_dl_systick__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,169 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0C110X)
|
||||
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0c110x.h>
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC)
|
||||
{
|
||||
// Set SYSOSC back to base frequency if left enabled
|
||||
if (disableSYSOSC == false) {
|
||||
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
} else {
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
}
|
||||
|
||||
// Verify LFCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void)
|
||||
{
|
||||
// Only one should have been set, but clear both because unknown incoming state
|
||||
// Clear SYSOSCCFG.DISABLE to get SYSOSC running again
|
||||
// Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(void)
|
||||
{
|
||||
// Switch MCLK to HSCLK
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify HSCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void)
|
||||
{
|
||||
// Switch MCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy =
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED;
|
||||
|
||||
// Check if SLEEP is enabled
|
||||
if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) ==
|
||||
SYSCTL_MCLKCFG_USELFCLK_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STOP policy =
|
||||
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY policy =
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) ==
|
||||
SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY1;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl,
|
||||
DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG,
|
||||
(uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc,
|
||||
SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK |
|
||||
SYSCTL_GENCLKCFG_FCCSELCLK_MASK);
|
||||
}
|
||||
|
||||
#endif /* DeviceFamily_PARENT_MSPM0C110X */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,320 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G1X0X_G3X0X)
|
||||
|
||||
#include <ti/driverlib/m0p/dl_core.h>
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g1x0x_g3x0x.h>
|
||||
|
||||
void DL_SYSCTL_configSYSPLL(const DL_SYSCTL_SYSPLLConfig *config)
|
||||
{
|
||||
/* PLL configurations are retained in lower reset levels. Set default
|
||||
* behavior of disabling the PLL to keep a consistent behavior regardless
|
||||
* of reset level. */
|
||||
DL_SYSCTL_disableSYSPLL();
|
||||
|
||||
/* Check that SYSPLL is disabled before configuration */
|
||||
while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) !=
|
||||
(DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) {
|
||||
;
|
||||
}
|
||||
|
||||
// set SYSPLL reference clock
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0,
|
||||
((uint32_t) config->sysPLLRef), SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK);
|
||||
|
||||
// set predivider PDIV (divides reference clock)
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, ((uint32_t) config->pDiv),
|
||||
SYSCTL_SYSPLLCFG1_PDIV_MASK);
|
||||
|
||||
// save CPUSS CTL state and disable the cache
|
||||
uint32_t ctlTemp = DL_CORE_getInstructionConfig();
|
||||
DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
|
||||
DL_CORE_LITERAL_CACHE_ENABLED);
|
||||
|
||||
// populate SYSPLLPARAM0/1 tuning registers from flash, based on input freq
|
||||
SYSCTL->SOCLOCK.SYSPLLPARAM0 =
|
||||
*(volatile uint32_t *) ((uint32_t) config->inputFreq);
|
||||
SYSCTL->SOCLOCK.SYSPLLPARAM1 =
|
||||
*(volatile uint32_t *) ((uint32_t) config->inputFreq + (uint32_t) 0x4);
|
||||
|
||||
// restore CPUSS CTL state
|
||||
CPUSS->CTL = ctlTemp;
|
||||
|
||||
// set feedback divider QDIV (multiplies to give output frequency)
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1,
|
||||
((config->qDiv << SYSCTL_SYSPLLCFG1_QDIV_OFS) &
|
||||
SYSCTL_SYSPLLCFG1_QDIV_MASK),
|
||||
SYSCTL_SYSPLLCFG1_QDIV_MASK);
|
||||
|
||||
// write clock output dividers, enable outputs, and MCLK source to SYSPLLCFG0
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0,
|
||||
(((config->rDivClk2x << SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS) &
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK) |
|
||||
((config->rDivClk1 << SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS) &
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK) |
|
||||
((config->rDivClk0 << SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS) &
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK) |
|
||||
config->enableCLK2x | config->enableCLK1 | config->enableCLK0 |
|
||||
(uint32_t) config->sysPLLMCLK),
|
||||
(SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK |
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK |
|
||||
SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK |
|
||||
SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK |
|
||||
SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK |
|
||||
SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK));
|
||||
|
||||
// enable SYSPLL
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_SYSPLLEN_ENABLE;
|
||||
|
||||
// wait until SYSPLL startup is stabilized
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG,
|
||||
((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) |
|
||||
(uint32_t) config->xt1Drive,
|
||||
(SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK));
|
||||
// start the LFXT oscillator
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE);
|
||||
// wait until LFXT oscillator is stable
|
||||
// if it does not stabilize, check the hardware/IOMUX settings
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_LFXT_GOOD) {
|
||||
;
|
||||
}
|
||||
if (config->monitor) {
|
||||
// set the LFCLK monitor
|
||||
SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE;
|
||||
}
|
||||
|
||||
// switch LFCLK source from LFOSC to LFXT
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE);
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC)
|
||||
{
|
||||
if (disableSYSOSC == false) {
|
||||
// Set SYSOSC back to base frequency if left enabled
|
||||
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
} else {
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
}
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify LFCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void)
|
||||
{
|
||||
// Only one should have been set, but clear both because unknown incoming state
|
||||
// Clear SYSOSCCFG.DISABLE to get SYSOSC running again
|
||||
// Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while (((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK)) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source)
|
||||
{
|
||||
// Assume desired HS sources already enabled per their requirements (SYSPLL, HFXT, HFCLK_IN)
|
||||
// Selected desired HSCLK source
|
||||
DL_SYSCTL_setHSCLKSource(source);
|
||||
|
||||
// Verify HSCLK source is valid
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HSCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
|
||||
// Switch MCLK to HSCLK
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify HSCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void)
|
||||
{
|
||||
// Switch MCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range)
|
||||
{
|
||||
/* Some crystal configurations are retained in lower reset levels. Set
|
||||
* default behavior of HFXT to keep a consistent behavior regardless of
|
||||
* reset level. */
|
||||
DL_SYSCTL_disableHFXT();
|
||||
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
/* Set startup time to ~0.512ms based on TYP datasheet recommendation */
|
||||
DL_SYSCTL_setHFXTStartupTime(8);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXTParams(
|
||||
DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable)
|
||||
{
|
||||
/* Some crystal configurations are retained in lower reset levels. Set
|
||||
* default behavior of HFXT to keep a consistent behavior regardless of
|
||||
* reset level. */
|
||||
DL_SYSCTL_disableHFXT();
|
||||
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
DL_SYSCTL_setHFXTStartupTime(startupTime);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
|
||||
if (monitorEnable == true) {
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while (
|
||||
(DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
} else {
|
||||
DL_SYSCTL_disableHFCLKStartupMonitor();
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl,
|
||||
DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG,
|
||||
(uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc,
|
||||
SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK |
|
||||
SYSCTL_GENCLKCFG_FCCSELCLK_MASK);
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy =
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED;
|
||||
|
||||
// Check if SLEEP is enabled
|
||||
if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) ==
|
||||
SYSCTL_MCLKCFG_USELFCLK_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STOP policy =
|
||||
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY policy =
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) ==
|
||||
SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY1;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
#endif /* DeviceFamily_PARENT_MSPM0G1X0X_G3X0X */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,382 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0GX51X)
|
||||
|
||||
#include <ti/driverlib/m0p/dl_core.h>
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0gx51x.h>
|
||||
|
||||
void DL_SYSCTL_configSYSPLL(const DL_SYSCTL_SYSPLLConfig *config)
|
||||
{
|
||||
/*
|
||||
* PLL configurations are retained in lower reset levels. Set default
|
||||
* behavior of disabling the PLL to keep a consistent behavior regardless
|
||||
* of reset level.
|
||||
*/
|
||||
DL_SYSCTL_disableSYSPLL();
|
||||
|
||||
/*
|
||||
* Before any configuration is done, a check is performed first to
|
||||
* ensure that the trim table within SRAM has been initialized first.
|
||||
* If it has not been initialized then the table within SRAM will be
|
||||
* populated with values from the TRIM region of memory. Otherwise
|
||||
* if the flag has been set the function will continue as normal.
|
||||
*/
|
||||
if (!DL_FactoryRegion_isTrimTableInSram()) {
|
||||
DL_FactoryRegion_initTrimTable();
|
||||
}
|
||||
|
||||
/* Check that SYSPLL is disabled before configuration */
|
||||
while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) !=
|
||||
(DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) {
|
||||
;
|
||||
}
|
||||
|
||||
// set SYSPLL reference clock
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0,
|
||||
((uint32_t) config->sysPLLRef), SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK);
|
||||
|
||||
// set predivider PDIV (divides reference clock)
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, ((uint32_t) config->pDiv),
|
||||
SYSCTL_SYSPLLCFG1_PDIV_MASK);
|
||||
|
||||
// save CPUSS CTL state and disable the cache
|
||||
uint32_t ctlTemp = DL_CORE_getInstructionConfig();
|
||||
DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
|
||||
DL_CORE_LITERAL_CACHE_ENABLED);
|
||||
|
||||
// populate SYSPLLPARAM0/1 tuning registers from flash, based on input freq
|
||||
SYSCTL->SOCLOCK.SYSPLLPARAM0 =
|
||||
*(volatile uint32_t *) ((uint32_t) config->inputFreq);
|
||||
SYSCTL->SOCLOCK.SYSPLLPARAM1 =
|
||||
*(volatile uint32_t *) ((uint32_t) config->inputFreq + (uint32_t) 0x4);
|
||||
|
||||
// restore CPUSS CTL state
|
||||
CPUSS->CTL = ctlTemp;
|
||||
|
||||
// set feedback divider QDIV (multiplies to give output frequency)
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1,
|
||||
((config->qDiv << SYSCTL_SYSPLLCFG1_QDIV_OFS) &
|
||||
SYSCTL_SYSPLLCFG1_QDIV_MASK),
|
||||
SYSCTL_SYSPLLCFG1_QDIV_MASK);
|
||||
|
||||
// write clock output dividers, enable outputs, and MCLK source to SYSPLLCFG0
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0,
|
||||
(((config->rDivClk2x << SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS) &
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK) |
|
||||
((config->rDivClk1 << SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS) &
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK) |
|
||||
((config->rDivClk0 << SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS) &
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK) |
|
||||
config->enableCLK2x | config->enableCLK1 | config->enableCLK0 |
|
||||
(uint32_t) config->sysPLLMCLK),
|
||||
(SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK |
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK |
|
||||
SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK |
|
||||
SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK |
|
||||
SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK |
|
||||
SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK));
|
||||
|
||||
// enable SYSPLL
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_SYSPLLEN_ENABLE;
|
||||
|
||||
// wait until SYSPLL startup is stabilized
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG,
|
||||
((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) |
|
||||
(uint32_t) config->xt1Drive,
|
||||
(SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK));
|
||||
// start the LFXT oscillator
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE);
|
||||
// wait until LFXT oscillator is stable
|
||||
// if it does not stabilize, check the hardware/IOMUX settings
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_LFXT_GOOD) {
|
||||
;
|
||||
}
|
||||
if (config->monitor) {
|
||||
// set the LFCLK monitor
|
||||
SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE;
|
||||
}
|
||||
|
||||
// switch LFCLK source from LFOSC to LFXT
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE);
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC)
|
||||
{
|
||||
if (disableSYSOSC == false) {
|
||||
// Set SYSOSC back to base frequency if left enabled
|
||||
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
} else {
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
}
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify LFCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void)
|
||||
{
|
||||
// Only one should have been set, but clear both because unknown incoming state
|
||||
// Clear SYSOSCCFG.DISABLE to get SYSOSC running again
|
||||
// Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while (((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK)) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source)
|
||||
{
|
||||
// Assume desired HS sources already enabled per their requirements (SYSPLL, HFXT, HFCLK_IN)
|
||||
// Selected desired HSCLK source
|
||||
DL_SYSCTL_setHSCLKSource(source);
|
||||
|
||||
// Verify HSCLK source is valid
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HSCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
|
||||
// Switch MCLK to HSCLK
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify HSCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void)
|
||||
{
|
||||
// Switch MCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range)
|
||||
{
|
||||
/*
|
||||
* Some crystal configurations are retained in lower reset levels. Set
|
||||
* default behavior of HFXT to keep a consistent behavior regardless of
|
||||
* reset level.
|
||||
*/
|
||||
DL_SYSCTL_disableHFXT();
|
||||
|
||||
/*
|
||||
* Before any configuration is done, a check is performed first to
|
||||
* ensure that the trim table within SRAM has been initialized first.
|
||||
* If it has not been initialized then the table within SRAM will be
|
||||
* populated with values from the TRIM region of memory. Otherwise
|
||||
* if the flag has been set the function will continue as normal.
|
||||
*/
|
||||
if (!DL_FactoryRegion_isTrimTableInSram()) {
|
||||
DL_FactoryRegion_initTrimTable();
|
||||
}
|
||||
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
/* Set startup time to ~0.512ms based on TYP datasheet recommendation */
|
||||
DL_SYSCTL_setHFXTStartupTime(8);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXTParams(
|
||||
DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable)
|
||||
{
|
||||
/*
|
||||
* Before any configuration is done, a check is performed first to
|
||||
* ensure that the trim table within SRAM has been initialized first.
|
||||
* If it has not been initialized then the table within SRAM will be
|
||||
* populated with values from the TRIM region of memory. Otherwise
|
||||
* if the flag has been set the function will continue as normal.
|
||||
*/
|
||||
if (!DL_FactoryRegion_isTrimTableInSram()) {
|
||||
DL_FactoryRegion_initTrimTable();
|
||||
}
|
||||
|
||||
/* Some crystal configurations are retained in lower reset levels. Set
|
||||
* default behavior of HFXT to keep a consistent behavior regardless of
|
||||
* reset level. */
|
||||
DL_SYSCTL_disableHFXT();
|
||||
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
DL_SYSCTL_setHFXTStartupTime(startupTime);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
|
||||
if (monitorEnable == true) {
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while (
|
||||
(DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
} else {
|
||||
DL_SYSCTL_disableHFCLKStartupMonitor();
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl,
|
||||
DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG,
|
||||
(uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc,
|
||||
SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK |
|
||||
SYSCTL_GENCLKCFG_FCCSELCLK_MASK);
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy =
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED;
|
||||
|
||||
// Check if SLEEP is enabled
|
||||
if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) ==
|
||||
SYSCTL_MCLKCFG_USELFCLK_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STOP policy =
|
||||
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY policy =
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) ==
|
||||
SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY1;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
bool DL_SYSCTL_initReadExecuteProtectFirewall(
|
||||
uint32_t startAddr, uint32_t endAddr)
|
||||
{
|
||||
bool status = false;
|
||||
if (!DL_SYSCTL_isINITDONEIssued()) {
|
||||
DL_SYSCTL_setReadExecuteProtectFirewallAddrStart(startAddr);
|
||||
DL_SYSCTL_setReadExecuteProtectFirewallAddrEnd(endAddr);
|
||||
DL_SYSCTL_enableReadExecuteProtectFirewall();
|
||||
status = true;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
bool DL_SYSCTL_initIPProtectFirewall(uint32_t startAddr, uint32_t endAddr)
|
||||
{
|
||||
bool status = false;
|
||||
if (!DL_SYSCTL_isINITDONEIssued()) {
|
||||
DL_SYSCTL_setIPProtectFirewallAddrStart(startAddr);
|
||||
DL_SYSCTL_setIPProtectFirewallAddrEnd(endAddr);
|
||||
DL_SYSCTL_enableIPProtectFirewall();
|
||||
status = true;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
#endif /* DeviceFamily_PARENT_MSPM0GX51X */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,240 @@
|
||||
/*
|
||||
* Copyright (c) 2023, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0H321X)
|
||||
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0h321x.h>
|
||||
|
||||
void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG,
|
||||
((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) |
|
||||
(uint32_t) config->xt1Drive,
|
||||
(SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK));
|
||||
// start the LFXT oscillator
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE);
|
||||
// wait until LFXT oscillator is stable
|
||||
// if it does not stabilize, check the hardware/IOMUX settings
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_LFXT_GOOD) {
|
||||
;
|
||||
}
|
||||
if (config->monitor) {
|
||||
// set the LFCLK monitor
|
||||
SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE;
|
||||
}
|
||||
|
||||
// switch LFCLK source from LFOSC to LFXT
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE);
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC)
|
||||
{
|
||||
// Set SYSOSC back to base frequency if left enabled
|
||||
if (disableSYSOSC == false) {
|
||||
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
} else {
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
}
|
||||
|
||||
// Verify LFCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void)
|
||||
{
|
||||
// Only one should have been set, but clear both because unknown incoming state
|
||||
// Clear SYSOSCCFG.DISABLE to get SYSOSC running again
|
||||
// Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source)
|
||||
{
|
||||
// Assume desired HS sources already enabled per their requirements (SYSPLL, HFXT, HFCLK_IN)
|
||||
// Selected desired HSCLK source
|
||||
DL_SYSCTL_setHSCLKSource(source);
|
||||
|
||||
// Verify HSCLK source is valid
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HSCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
|
||||
// Switch MCLK to HSCLK
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify HSCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void)
|
||||
{
|
||||
// Switch MCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range)
|
||||
{
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
/* Set startup time to ~0.512ms based on TYP datasheet recommendation */
|
||||
DL_SYSCTL_setHFXTStartupTime(8);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXTParams(
|
||||
DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable)
|
||||
{
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
DL_SYSCTL_setHFXTStartupTime(startupTime);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
|
||||
if (monitorEnable == true) {
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while (
|
||||
(DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
} else {
|
||||
DL_SYSCTL_disableHFCLKStartupMonitor();
|
||||
}
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy =
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED;
|
||||
|
||||
// Check if SLEEP is enabled
|
||||
if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) ==
|
||||
SYSCTL_MCLKCFG_USELFCLK_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STOP policy =
|
||||
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY policy =
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) ==
|
||||
SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY1;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl,
|
||||
DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG,
|
||||
(uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc,
|
||||
SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK |
|
||||
SYSCTL_GENCLKCFG_FCCSELCLK_MASK);
|
||||
}
|
||||
|
||||
#endif /* DeviceFamily_PARENT_MSPM0H321X */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,223 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L111X)
|
||||
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l111x.h>
|
||||
|
||||
bool DL_SYSCTL_initReadExecuteProtectFirewall(
|
||||
uint32_t startAddr, uint32_t endAddr)
|
||||
{
|
||||
bool status = false;
|
||||
if (!DL_SYSCTL_isINITDONEIssued()) {
|
||||
DL_SYSCTL_setReadExecuteProtectFirewallAddrStart(startAddr);
|
||||
DL_SYSCTL_setReadExecuteProtectFirewallAddrEnd(endAddr);
|
||||
DL_SYSCTL_enableReadExecuteProtectFirewall();
|
||||
status = true;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
bool DL_SYSCTL_initIPProtectFirewall(uint32_t startAddr, uint32_t endAddr)
|
||||
{
|
||||
bool status = false;
|
||||
if (!DL_SYSCTL_isINITDONEIssued()) {
|
||||
DL_SYSCTL_setIPProtectFirewallAddrStart(startAddr);
|
||||
DL_SYSCTL_setIPProtectFirewallAddrEnd(endAddr);
|
||||
DL_SYSCTL_enableIPProtectFirewall();
|
||||
status = true;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG,
|
||||
((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) |
|
||||
(uint32_t) config->xt1Drive,
|
||||
(SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK));
|
||||
// start the LFXT oscillator
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE);
|
||||
// wait until LFXT oscillator is stable
|
||||
// if it does not stabilize, check the hardware/IOMUX settings
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_LFXT_GOOD) {
|
||||
;
|
||||
}
|
||||
if (config->monitor) {
|
||||
// set the LFCLK monitor
|
||||
SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE;
|
||||
}
|
||||
|
||||
// switch LFCLK source from LFOSC to LFXT
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE);
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC)
|
||||
{
|
||||
// Set SYSOSC back to base frequency if left enabled
|
||||
if (disableSYSOSC == false) {
|
||||
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
} else {
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
}
|
||||
|
||||
// Verify LFCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void)
|
||||
{
|
||||
// Only one should have been set, but clear both because unknown incoming state
|
||||
// Clear SYSOSCCFG.DISABLE to get SYSOSC running again
|
||||
// Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(void)
|
||||
{
|
||||
// Switch MCLK to HSCLK
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify HSCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void)
|
||||
{
|
||||
// Switch MCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl,
|
||||
DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG,
|
||||
(uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc,
|
||||
SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK |
|
||||
SYSCTL_GENCLKCFG_FCCSELCLK_MASK);
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy =
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED;
|
||||
|
||||
// Check if SLEEP is enabled
|
||||
if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) ==
|
||||
SYSCTL_MCLKCFG_USELFCLK_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STOP policy =
|
||||
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY policy =
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) ==
|
||||
SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY1;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
#endif /* DeviceFamily_PARENT_MSPM0L111X */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,146 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L11XX_L13XX)
|
||||
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l11xx_l13xx.h>
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC)
|
||||
{
|
||||
if (disableSYSOSC == false) {
|
||||
// Set SYSOSC back to base frequency if left enabled
|
||||
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
} else {
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
}
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify LFCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void)
|
||||
{
|
||||
// Only one should have been set, but clear both because unknown incoming state
|
||||
// Clear SYSOSCCFG.DISABLE to get SYSOSC running again
|
||||
// Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy =
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED;
|
||||
|
||||
// Check if SLEEP is enabled
|
||||
if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) ==
|
||||
SYSCTL_MCLKCFG_USELFCLK_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STOP policy =
|
||||
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY policy =
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) ==
|
||||
SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY1;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl,
|
||||
DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG,
|
||||
(uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc,
|
||||
SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK |
|
||||
SYSCTL_GENCLKCFG_FCCSELCLK_MASK);
|
||||
}
|
||||
|
||||
#endif /* DeviceFamily_PARENT_MSPM0L11XX_L13XX */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,269 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L122X_L222X)
|
||||
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l122x_l222x.h>
|
||||
|
||||
bool DL_SYSCTL_initReadExecuteProtectFirewall(
|
||||
uint32_t startAddr, uint32_t endAddr)
|
||||
{
|
||||
bool status = false;
|
||||
if (!DL_SYSCTL_isINITDONEIssued()) {
|
||||
DL_SYSCTL_setReadExecuteProtectFirewallAddrStart(startAddr);
|
||||
DL_SYSCTL_setReadExecuteProtectFirewallAddrEnd(endAddr);
|
||||
DL_SYSCTL_enableReadExecuteProtectFirewall();
|
||||
status = true;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
bool DL_SYSCTL_initIPProtectFirewall(uint32_t startAddr, uint32_t endAddr)
|
||||
{
|
||||
bool status = false;
|
||||
if (!DL_SYSCTL_isINITDONEIssued()) {
|
||||
DL_SYSCTL_setIPProtectFirewallAddrStart(startAddr);
|
||||
DL_SYSCTL_setIPProtectFirewallAddrEnd(endAddr);
|
||||
DL_SYSCTL_enableIPProtectFirewall();
|
||||
status = true;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG,
|
||||
((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) |
|
||||
(uint32_t) config->xt1Drive,
|
||||
(SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK));
|
||||
// start the LFXT oscillator
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE);
|
||||
// wait until LFXT oscillator is stable
|
||||
// if it does not stabilize, check the hardware/IOMUX settings
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_LFXT_GOOD) {
|
||||
;
|
||||
}
|
||||
if (config->monitor) {
|
||||
// set the LFCLK monitor
|
||||
SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE;
|
||||
}
|
||||
|
||||
// switch LFCLK source from LFOSC to LFXT
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE);
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC)
|
||||
{
|
||||
// Set SYSOSC back to base frequency if left enabled
|
||||
if (disableSYSOSC == false) {
|
||||
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
} else {
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
}
|
||||
|
||||
// Verify LFCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void)
|
||||
{
|
||||
// Only one should have been set, but clear both because unknown incoming state
|
||||
// Clear SYSOSCCFG.DISABLE to get SYSOSC running again
|
||||
// Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source)
|
||||
{
|
||||
// Assume desired HS sources already enabled per their requirements (SYSPLL, HFXT, HFCLK_IN)
|
||||
// Selected desired HSCLK source
|
||||
DL_SYSCTL_setHSCLKSource(source);
|
||||
|
||||
// Verify HSCLK source is valid
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HSCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
|
||||
// Switch MCLK to HSCLK
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify HSCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void)
|
||||
{
|
||||
// Switch MCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range)
|
||||
{
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
/* Set startup time to ~0.512ms based on TYP datasheet recommendation */
|
||||
DL_SYSCTL_setHFXTStartupTime(8);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXTParams(
|
||||
DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable)
|
||||
{
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
DL_SYSCTL_setHFXTStartupTime(startupTime);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
|
||||
if (monitorEnable == true) {
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while (
|
||||
(DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
} else {
|
||||
DL_SYSCTL_disableHFCLKStartupMonitor();
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl,
|
||||
DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG,
|
||||
(uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc,
|
||||
SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK |
|
||||
SYSCTL_GENCLKCFG_FCCSELCLK_MASK);
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy =
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED;
|
||||
|
||||
// Check if SLEEP is enabled
|
||||
if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) ==
|
||||
SYSCTL_MCLKCFG_USELFCLK_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STOP policy =
|
||||
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY policy =
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) ==
|
||||
SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY1;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
#endif /* DeviceFamily_PARENT_MSPM0L122X_L222X */
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user