init:初始框架
This commit is contained in:
SkyLi
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/*
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* Copyright (c) 2020, Texas Instruments Incorporated
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||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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/*!****************************************************************************
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* @file dl_core.h
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* @brief CPU Core Driver Library
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* @defgroup CORE M0P Core
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*
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* @anchor ti_dl_m0p_dl_core_Overview
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* # Overview
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*
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* The Core module enables software to read from core registers of the CPU to
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* get more information about the device at runtime.
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*
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* <hr>
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******************************************************************************
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*/
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/** @addtogroup CORE
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* @{
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*/
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#ifndef ti_dl_m0p_dl_core__include
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#define ti_dl_m0p_dl_core__include
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#include <stdint.h>
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#include <ti/devices/msp/msp.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* clang-format off */
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/** @addtogroup DL_CORE_CACHE
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* @{
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*/
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/*!
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* @brief Enables instruction caching on flash access
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*/
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#define DL_CORE_CACHE_ENABLED (CPUSS_CTL_ICACHE_ENABLE)
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/*!
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* @brief Disables instruction caching on flash access
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*/
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#define DL_CORE_CACHE_DISABLED (CPUSS_CTL_ICACHE_DISABLE)
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/** @}*/
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/** @addtogroup DL_CORE_PREFETCH
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* @{
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*/
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/*!
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* @brief Enables instruction prefetch to Flash
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*/
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#define DL_CORE_PREFETCH_ENABLED (CPUSS_CTL_PREFETCH_ENABLE)
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/*!
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* @brief Disables instruction prefetch to Flash
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*/
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#define DL_CORE_PREFETCH_DISABLED (CPUSS_CTL_PREFETCH_DISABLE)
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/** @}*/
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/** @addtogroup DL_CORE_LITERAL_CACHE
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* @{
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*/
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/*!
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* @brief Enables caching and prefetching of literals.
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* This is set only if the ICACHE or PREFETCH bits have been set respectively.
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*/
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#define DL_CORE_LITERAL_CACHE_ENABLED (CPUSS_CTL_LITEN_ENABLE)
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/*!
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* @brief Disables caching and prefetching of literals
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*/
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#define DL_CORE_LITERAL_CACHE_DISABLED (CPUSS_CTL_LITEN_DISABLE)
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/** @}*/
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/**
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* @brief Alias for DL_Common_delayCycles
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*/
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#define delay_cycles(cycles) DL_Common_delayCycles(cycles)
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/** @}*/
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/* clang-format on */
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/**
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* @brief Get the implementer code for the processor
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*
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* @return The implementer code
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*
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* @retval 0x41 for ARM
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*/
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__STATIC_INLINE uint32_t DL_CORE_getImplementer(void)
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{
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return (
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(SCB->CPUID & SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
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}
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/**
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* @brief Get the major revision number 'n' in the 'npm' revision status
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*
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* @return The major revision number
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*
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* @retval 0x00 for revision 0
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*/
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__STATIC_INLINE uint32_t DL_CORE_getVariant(void)
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{
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return ((SCB->CPUID & SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
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}
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/**
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* @brief Get the architecture of the processor
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*
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* @return Value that defines the architecture of the processor
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*
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* @retval 0x0C for ARMv6-M architecture
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*/
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__STATIC_INLINE uint32_t DL_CORE_getArchitecture(void)
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{
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return ((SCB->CPUID & SCB_CPUID_ARCHITECTURE_Msk) >>
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SCB_CPUID_ARCHITECTURE_Pos);
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}
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/**
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* @brief Get part number of the processor (not the device)
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*
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* @return Value that defines the processor
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*
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* @retval 0x0C60 for Cortex-M0+
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*/
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__STATIC_INLINE uint32_t DL_CORE_getPartNumber(void)
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{
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return ((SCB->CPUID & SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
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}
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/**
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* @brief Get the minor revision number 'm' in the 'npm' revision status
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*
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* @return The minor revision number
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*
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* @retval 0x01 for patch 1
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*/
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__STATIC_INLINE uint32_t DL_CORE_getRevision(void)
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{
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return ((SCB->CPUID & (uint32_t)SCB_CPUID_REVISION_Msk) >> (uint32_t)SCB_CPUID_REVISION_Pos);
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}
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/**
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* @brief Configures instruction caching in flash accesses and instruction
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* prefetch to flash
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*
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* @param icache [in] Instruction cache option @ref DL_CORE_CACHE
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* @param prefetch [in] Instruction prefetch option @ref DL_CORE_PREFETCH
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* @param litCache [in] Literal cache option @ref DL_CORE_LITERAL_CACHE
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*
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*/
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__STATIC_INLINE void DL_CORE_configInstruction(uint32_t icache, uint32_t prefetch, uint32_t litCache)
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{
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CPUSS->CTL = (icache | prefetch | litCache);
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}
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/**
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* @brief Returns instruction caching, prefetch, and literal cache configuration
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*
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* @return Bitwise OR of @ref DL_CORE_CACHE and @ref DL_CORE_PREFETCH and
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* @ref DL_CORE_LITERAL_CACHE
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*/
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__STATIC_INLINE uint32_t DL_CORE_getInstructionConfig(void)
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{
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return(CPUSS->CTL & (CPUSS_CTL_ICACHE_MASK | CPUSS_CTL_PREFETCH_MASK | CPUSS_CTL_LITEN_MASK));
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* ti_dl_m0p_dl_core__include */
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/** @}*/
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@@ -0,0 +1,74 @@
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/*
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||||
* Copyright (c) 2024, Texas Instruments Incorporated
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||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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||||
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#include <stdint.h>
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#include <ti/driverlib/m0p/dl_factoryregion.h>
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#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0GX51X)
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/* Creating a section for structure inside SRAM*/
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__attribute__((section(".TrimTable")))
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DL_FACTORYREGION_TrimValues DL_FACTORYREGION_TrimTable;
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/* Creating a pointer to the structure placed inside SRAM*/
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DL_FACTORYREGION_TrimValues *FACTORYVALUE = &DL_FACTORYREGION_TrimTable;
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void DL_FactoryRegion_initTrimTable(void)
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{
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DL_FACTORYREGION_TrimTable.TRACEID = FACTORYREGION->TRACEID;
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DL_FACTORYREGION_TrimTable.DEVICEID = FACTORYREGION->DEVICEID;
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DL_FACTORYREGION_TrimTable.USERID = FACTORYREGION->USERID;
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DL_FACTORYREGION_TrimTable.BSLPIN_UART = FACTORYREGION->BSLPIN_UART;
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DL_FACTORYREGION_TrimTable.BSLPIN_I2C = FACTORYREGION->BSLPIN_I2C;
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DL_FACTORYREGION_TrimTable.BSLPIN_INVOKE = FACTORYREGION->BSLPIN_INVOKE;
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DL_FACTORYREGION_TrimTable.SRAMFLASH = FACTORYREGION->SRAMFLASH;
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DL_FACTORYREGION_TrimTable.PLLSTARTUP0_4_8MHZ =
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FACTORYREGION->PLLSTARTUP0_4_8MHZ;
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DL_FACTORYREGION_TrimTable.PLLSTARTUP1_4_8MHZ =
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FACTORYREGION->PLLSTARTUP1_4_8MHZ;
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DL_FACTORYREGION_TrimTable.PLLSTARTUP0_8_16MHZ =
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FACTORYREGION->PLLSTARTUP0_8_16MHZ;
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DL_FACTORYREGION_TrimTable.PLLSTARTUP1_8_16MHZ =
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FACTORYREGION->PLLSTARTUP1_8_16MHZ;
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DL_FACTORYREGION_TrimTable.PLLSTARTUP0_16_32MHZ =
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FACTORYREGION->PLLSTARTUP0_16_32MHZ;
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DL_FACTORYREGION_TrimTable.PLLSTARTUP1_16_32MHZ =
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FACTORYREGION->PLLSTARTUP1_16_32MHZ;
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DL_FACTORYREGION_TrimTable.PLLSTARTUP0_32_48MHZ =
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FACTORYREGION->PLLSTARTUP0_32_48MHZ;
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DL_FACTORYREGION_TrimTable.PLLSTARTUP1_32_48MHZ =
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FACTORYREGION->PLLSTARTUP1_32_48MHZ;
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DL_FACTORYREGION_TrimTable.TEMP_SENSE0 = FACTORYREGION->TEMP_SENSE0;
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DL_FACTORYREGION_TrimTable.DATA_SET = DL_FACTORYREGION_TRIM_FLAG_IS_SET;
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return;
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}
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#endif
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Load Diff
@@ -0,0 +1,73 @@
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/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/driverlib/m0p/dl_interrupt.h>
|
||||
|
||||
/* 32 Device Peripheral Exceptions + 16 reserved M0+ Exceptions */
|
||||
#define NUM_RES_M0_EXC ((uint32_t) 16)
|
||||
#define NUM_DEV_PERIPH_EXC ((uint32_t) 32)
|
||||
#define NUM_INTERRUPTS (NUM_RES_M0_EXC + NUM_DEV_PERIPH_EXC)
|
||||
|
||||
#if defined(__IAR_SYSTEMS_ICC__)
|
||||
#pragma data_alignment = 256
|
||||
static __no_init void (*InterruptRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
|
||||
#else
|
||||
static __attribute__((section(".vtable"))) void (
|
||||
*InterruptRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(256)));
|
||||
#endif
|
||||
void DL_Interrupt_registerInterrupt(
|
||||
uint32_t exceptionNumber, void (*intHandler)(void))
|
||||
{
|
||||
void (**baseAddress)(void);
|
||||
uint32_t i;
|
||||
|
||||
/* See if the RAM vector table has been initialized */
|
||||
if (SCB->VTOR != (uint32_t) InterruptRAMVectors) {
|
||||
baseAddress = (void (**)(void)) SCB->VTOR;
|
||||
|
||||
/* Copy the vector table from Flash to RAM */
|
||||
for (i = 0; i < NUM_INTERRUPTS; i++) {
|
||||
InterruptRAMVectors[i] = baseAddress[i];
|
||||
}
|
||||
|
||||
SCB->VTOR = (uint32_t) InterruptRAMVectors;
|
||||
}
|
||||
|
||||
InterruptRAMVectors[exceptionNumber + NUM_RES_M0_EXC] = intHandler;
|
||||
}
|
||||
|
||||
void DL_Interrupt_unregisterInterrupt(uint32_t exceptionNumber)
|
||||
{
|
||||
InterruptRAMVectors[exceptionNumber + NUM_RES_M0_EXC] = Default_Handler;
|
||||
}
|
||||
@@ -0,0 +1,353 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_interrupt.h
|
||||
* @brief Interrupt Management Driver Library
|
||||
* @defgroup INTERRUPT M0P Interrupts
|
||||
*
|
||||
* @anchor ti_dl_m0p_dl_interrupt_Overview
|
||||
* # Overview
|
||||
*
|
||||
* The Cortex-M0+ architecture is limited to 32 device interrupts. To enable
|
||||
* interrupt handling on devices that need more than 32 interrupts, the
|
||||
* interrupts are grouped together.
|
||||
*
|
||||
* For example, "Group 0" contains the interrupt flags for the WWDT0, WWDT1,
|
||||
* DEBUGSS, FLASH, and SYSCTL peripherals. Once the interrupt fires for Group 0,
|
||||
* the application must check to see which peripheral from Group 0 was the
|
||||
* source using the APIs in this module.
|
||||
*
|
||||
* This PI module is not for controlling the NVIC or the I-bit in the CPSR
|
||||
* register. It's best to use the CMSIS-Core APIs that are delivered as part
|
||||
* of CMSIS-Core in the `source/third_party/CMSIS/Core/Include/core_cm0plus.h`
|
||||
* file within the SDK.
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup INTERRUPT
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_m0p_dl_interrupt__include
|
||||
#define ti_dl_m0p_dl_interrupt__include
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
#include <ti/devices/msp/peripherals/m0p/hw_cpuss.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/** @addtogroup DL_INTERRUPT_GROUP_IIDX
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief WWDT0 Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_IIDX_WWDT0 (CPUSS_INT_GROUP_IIDX_STAT_INT0)
|
||||
|
||||
/*!
|
||||
* @brief WWDT1 Interrupt in Group 0.
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 0 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_IIDX_WWDT1 (CPUSS_INT_GROUP_IIDX_STAT_INT1)
|
||||
|
||||
/*!
|
||||
* @brief DEBUGSS Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_IIDX_DEBUGSS (CPUSS_INT_GROUP_IIDX_STAT_INT2)
|
||||
|
||||
/*!
|
||||
* @brief FLASH Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_IIDX_FLASH (CPUSS_INT_GROUP_IIDX_STAT_INT3)
|
||||
|
||||
/*!
|
||||
* @brief WUC FSUB0 Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_IIDX_WUC_FSUB0 (CPUSS_INT_GROUP_IIDX_STAT_INT4)
|
||||
|
||||
/*!
|
||||
* @brief WUC FSUB0 Interrupt in Group 1
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_IIDX_WUC_FSUB1 (CPUSS_INT_GROUP_IIDX_STAT_INT5)
|
||||
|
||||
/*!
|
||||
* @brief SYSCTL (PMCU) Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_IIDX_SYSCTL (CPUSS_INT_GROUP_IIDX_STAT_INT6)
|
||||
|
||||
/*!
|
||||
* @brief GPIOA Interrupt in Group 1
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_IIDX_GPIOA (CPUSS_INT_GROUP_IIDX_STAT_INT0)
|
||||
|
||||
/*!
|
||||
* @brief GPIOB Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_IIDX_GPIOB (CPUSS_INT_GROUP_IIDX_STAT_INT1)
|
||||
|
||||
/*!
|
||||
* @brief COMP0 Interrupt in Group 1
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_IIDX_COMP0 (CPUSS_INT_GROUP_IIDX_STAT_INT2)
|
||||
|
||||
/*!
|
||||
* @brief COMP1 Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_IIDX_COMP1 (CPUSS_INT_GROUP_IIDX_STAT_INT3)
|
||||
|
||||
/*!
|
||||
* @brief COMP2 Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_IIDX_COMP2 (CPUSS_INT_GROUP_IIDX_STAT_INT4)
|
||||
|
||||
/*!
|
||||
* @brief TRNG Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_IIDX_TRNG (CPUSS_INT_GROUP_IIDX_STAT_INT5)
|
||||
|
||||
/*!
|
||||
* @brief GPIOC Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_IIDX_GPIOC (CPUSS_INT_GROUP_IIDX_STAT_INT6)
|
||||
|
||||
/** @}*/
|
||||
|
||||
/** @addtogroup DL_INTERRUPT_GROUP_INTERRUPTS
|
||||
* @{
|
||||
*/
|
||||
/*!
|
||||
* @brief WWDT0 Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_WWDT0 (CPUSS_INT_GROUP_IMASK_INT_INT0)
|
||||
/*!
|
||||
* @brief WWDT1 Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_WWDT1 (CPUSS_INT_GROUP_IMASK_INT_INT1)
|
||||
/*!
|
||||
* @brief DEBUGSS Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_DEBUGSS (CPUSS_INT_GROUP_IMASK_INT_INT2)
|
||||
/*!
|
||||
* @brief FLASH Interrupt in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_FLASH (CPUSS_INT_GROUP_IMASK_INT_INT3)
|
||||
/*!
|
||||
* @brief Generic event subscriber 0 in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_WUC_FSUB0 (CPUSS_INT_GROUP_IMASK_INT_INT4)
|
||||
/*!
|
||||
* @brief Generic event subscriber 1 in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_WUC_FSUB1 (CPUSS_INT_GROUP_IMASK_INT_INT5)
|
||||
/*!
|
||||
* @brief PMCU (system controller) in Group 0
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP0_PMCU (CPUSS_INT_GROUP_IMASK_INT_INT6)
|
||||
|
||||
/*!
|
||||
* @brief GPIOA Interrupt in Group 1
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_GPIOA (CPUSS_INT_GROUP_IMASK_INT_INT0)
|
||||
/*!
|
||||
* @brief GPIOB Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_GPIOB (CPUSS_INT_GROUP_IMASK_INT_INT1)
|
||||
/*!
|
||||
* @brief COMP0 Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_COMP0 (CPUSS_INT_GROUP_IMASK_INT_INT2)
|
||||
/*!
|
||||
* @brief COMP1 Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_COMP1 (CPUSS_INT_GROUP_IMASK_INT_INT3)
|
||||
/*!
|
||||
* @brief COMP2 Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_COMP2 (CPUSS_INT_GROUP_IMASK_INT_INT4)
|
||||
/*!
|
||||
* @brief TRNG Interrupt in Group 1
|
||||
* @note This is a device specific interrupt. Please consult the device TRM to
|
||||
* determine if the interrupt is enabled as part of Group 1 interrupts.
|
||||
*/
|
||||
#define DL_INTERRUPT_GROUP1_TRNG (CPUSS_INT_GROUP_IMASK_INT_INT5)
|
||||
|
||||
/** @}*/
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
/*! @enum DL_INTERRUPT_GROUP */
|
||||
typedef enum {
|
||||
/*! Selects interrupt group 0 */
|
||||
DL_INTERRUPT_GROUP_0 = 0,
|
||||
/*! Selects interrupt group 1 */
|
||||
DL_INTERRUPT_GROUP_1 = 1
|
||||
} DL_INTERRUPT_GROUP;
|
||||
|
||||
/**
|
||||
* @brief Device default Handler
|
||||
*
|
||||
* This function is defined as part of the device startup file.
|
||||
*/
|
||||
extern void Default_Handler(void);
|
||||
|
||||
/**
|
||||
* @brief Checks interrupt flag status in the selected group of interrupts
|
||||
*
|
||||
* Checks if any of the interrupts in the group are pending. When calling the
|
||||
* function, ensure that the interrupts passed in the mask are applicable to
|
||||
* the requested interrupt group.
|
||||
*
|
||||
* @param[in] group Group of interrupts to check.
|
||||
* @ref DL_INTERRUPT_GROUP
|
||||
* @param[in] interruptMask Bit mask of interrupts to check. Bitwise OR of
|
||||
* @ref DL_INTERRUPT_GROUP_INTERRUPTS.
|
||||
*
|
||||
* @return Which of the requested group interrupts are pending
|
||||
*
|
||||
* @retval Bitwise OR of @ref DL_INTERRUPT_GROUP_INTERRUPTS values
|
||||
*/
|
||||
static inline uint32_t DL_Interrupt_getStatusGroup(
|
||||
DL_INTERRUPT_GROUP group, uint32_t interruptMask)
|
||||
{
|
||||
return (CPUSS->INT_GROUP[(uint32_t) group].RIS & interruptMask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get highest priority interrupt pending in the selected interrupt
|
||||
* group
|
||||
*
|
||||
* @param[in] group Group of interrupts to check
|
||||
*
|
||||
* @return The highest priority pending interrupt for the group requested.
|
||||
* One of @ref DL_INTERRUPT_GROUP_IIDX
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_Interrupt_getPendingGroup(DL_INTERRUPT_GROUP group)
|
||||
{
|
||||
return (CPUSS->INT_GROUP[group].IIDX);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear selected interrupt flags in the selected interrupt group
|
||||
*
|
||||
* Clears any of the desired interrupts in the group. When calling the
|
||||
* function, ensure that the interrupts passed in the mask are applicable to
|
||||
* the requested interrupt group.
|
||||
*
|
||||
* @param[in] group Group of interrupts to check.
|
||||
* @ref DL_INTERRUPT_GROUP
|
||||
* @param[in] interruptMask Bit mask of interrupts to clear. Bitwise OR of
|
||||
* @ref DL_INTERRUPT_GROUP_INTERRUPTS.
|
||||
*/
|
||||
static inline void DL_Interrupt_clearGroup(
|
||||
DL_INTERRUPT_GROUP group, uint32_t interruptMask)
|
||||
{
|
||||
CPUSS->INT_GROUP[(uint32_t) group].ICLR |= interruptMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register a function to be called when an interrupt occurs
|
||||
*
|
||||
* This allows you to register a function to be called during an interrupt,
|
||||
* allowing you to override the interrupt handler at run time. The function
|
||||
* moves the interrupt vector table from Flash to SRAM so that the interrupt
|
||||
* handler functions can be overwritten.
|
||||
*
|
||||
* This function should only be used if the application requires specifying
|
||||
* the interrupt handler at run time. If it does not need to be changed at
|
||||
* run time consider placing the ISR function pointer in the startup file to
|
||||
* link the function into the interrupt table.
|
||||
*
|
||||
* Example of usage:
|
||||
* @code
|
||||
* DL_Interrupt_registerInterrupt(TIMA0_INT_IRQn, redirectedInterruptHandler);
|
||||
* @endcode
|
||||
*
|
||||
* @param[in] exceptionNumber The interrupt number to register the handler.
|
||||
* Interrupt numbers are device specific, please
|
||||
* consult the device datasheet for valid
|
||||
* interrupt numbers.
|
||||
* @param[in] intHandler A pointer to a function to call for the desired
|
||||
* interrupt
|
||||
*/
|
||||
void DL_Interrupt_registerInterrupt(
|
||||
uint32_t exceptionNumber, void (*intHandler)(void));
|
||||
|
||||
/**
|
||||
* @brief Unregister a function to be called when an interrupt occurs
|
||||
*
|
||||
* Overrides the registered interrupt function to jump into a simple while(1)
|
||||
* loop rather than the previously registered interrupt function. Requires
|
||||
* that @ref DL_Interrupt_registerInterrupt was previously called so that the
|
||||
* interrupt vector table has been moved to RAM.
|
||||
*
|
||||
* Example of usage:
|
||||
* @code DL_Interrupt_unregisterInterrupt(TIMA0_INT_IRQn); @endcode
|
||||
*
|
||||
* @param[in] exceptionNumber The interrupt number to unregister.
|
||||
* Interrupt numbers are device specific, please
|
||||
* consult the device datasheet for valid
|
||||
* interrupt numbers.
|
||||
*/
|
||||
void DL_Interrupt_unregisterInterrupt(uint32_t exceptionNumber);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ti_dl_m0p_dl_interrupt__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,75 @@
|
||||
/*****************************************************************************
|
||||
|
||||
Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions
|
||||
are met:
|
||||
|
||||
Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the
|
||||
distribution.
|
||||
|
||||
Neither the name of Texas Instruments Incorporated nor the names of
|
||||
its contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*****************************************************************************/
|
||||
/* This file automatically includes the specific device header file
|
||||
without the need to include a specific device header.
|
||||
The device #define is set automatically through the toolchain on basis
|
||||
of the device chosen in the device selection menu (.e.g -D__MICRO1__). */
|
||||
/** @defgroup SYSCTL M0P System Control (SYSCTL) */
|
||||
/** @addtogroup SYSCTL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef ti_driverlib_m0p_sysctl__include
|
||||
#define ti_driverlib_m0p_sysctl__include
|
||||
|
||||
/******************************************************************************
|
||||
* MSP devices
|
||||
******************************************************************************/
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G1X0X_G3X0X)
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g1x0x_g3x0x.h>
|
||||
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L11XX_L13XX)
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l11xx_l13xx.h>
|
||||
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0C110X) || \
|
||||
(DeviceFamily_PARENT == DeviceFamily_PARENT_MSPS003FX)
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0c110x.h>
|
||||
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L122X_L222X)
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l122x_l222x.h>
|
||||
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0GX51X)
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0gx51x.h>
|
||||
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L111X)
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l111x.h>
|
||||
#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0H321X)
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0h321x.h>
|
||||
|
||||
/********************************************************************
|
||||
*
|
||||
********************************************************************/
|
||||
#else
|
||||
#error "Failed to match a default include file"
|
||||
#endif
|
||||
|
||||
#endif /* ti_driverlib_m0p_sysctl__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,193 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*!****************************************************************************
|
||||
* @file dl_systick.h
|
||||
* @brief System Tick Timer (SysTick) Driver Library
|
||||
* @defgroup SYSTICK M0P System Tick Timer (SysTick)
|
||||
*
|
||||
* @anchor ti_dl_m0p_dl_systick_Overview
|
||||
* # Overview
|
||||
*
|
||||
* SysTick is a simple timer that is part of the Cortex-M architecture. Its
|
||||
* intended purpose is to provide a periodic interrupt for an RTOS, but it can
|
||||
* be used for other simple timing purposes.
|
||||
*
|
||||
* <hr>
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup SYSTICK
|
||||
* @{
|
||||
*/
|
||||
#ifndef ti_dl_m0p_dl_systick__include
|
||||
#define ti_dl_m0p_dl_systick__include
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <ti/devices/msp/msp.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
/**
|
||||
* @brief Redirects DL_SYSTICK_config to CMSIS standard SysTick_Config
|
||||
*/
|
||||
#define DL_SYSTICK_config(x) SysTick_Config(x)
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
/**
|
||||
* @brief Initializes the System Tick Timer (SysTick)
|
||||
*
|
||||
* Initializes the System Tick Timer by configuring the desired period. Resets
|
||||
* the counter so that, once enabled, the SysTick starts counting from 0. Does
|
||||
* not start the timer or enable the interrupt.
|
||||
*
|
||||
* @param[in] period The period in ticks for the SysTick to fire. Value
|
||||
* between 0x00000002 - 0x01000000.
|
||||
*/
|
||||
__STATIC_INLINE void DL_SYSTICK_init(uint32_t period)
|
||||
{
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk;
|
||||
SysTick->LOAD = period - (uint32_t) 1;
|
||||
SysTick->VAL = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the period for the SysTick
|
||||
*
|
||||
* Calling this function does not cause the SysTick counter to reload
|
||||
* immediately. If you want to change the period and reset the counter use
|
||||
* the @ref DL_SYSTICK_init function or @ref DL_SYSTICK_resetValue.
|
||||
*
|
||||
* @param[in] period The period in ticks for the SysTick to fire. Value
|
||||
* between 0x00000002 - 0x01000000.
|
||||
*/
|
||||
__STATIC_INLINE void DL_SYSTICK_setPeriod(uint32_t period)
|
||||
{
|
||||
SysTick->LOAD = period - (uint32_t) 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the current value of the SysTick
|
||||
*
|
||||
* Resets the current value of the SysTick back to 0, essentially resetting
|
||||
* the period.
|
||||
*/
|
||||
__STATIC_INLINE void DL_SYSTICK_resetValue(void)
|
||||
{
|
||||
SysTick->VAL = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the period for the SysTick
|
||||
*
|
||||
* @return The period in ticks for the SysTick to fire
|
||||
*
|
||||
* @retval Value between 0x00000002 - 0x01000000.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_SYSTICK_getPeriod(void)
|
||||
{
|
||||
return (SysTick->LOAD + (uint32_t) 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the current value of SysTick counter
|
||||
*
|
||||
* @return The current value of the counter in ticks
|
||||
*
|
||||
* @retval Value between 0x00000000 - 0x00FFFFFF.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t DL_SYSTICK_getValue(void)
|
||||
{
|
||||
return SysTick->VAL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the SysTick interrupt
|
||||
*/
|
||||
__STATIC_INLINE void DL_SYSTICK_enableInterrupt(void)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the SysTick interrupt
|
||||
*/
|
||||
__STATIC_INLINE void DL_SYSTICK_disableInterrupt(void)
|
||||
{
|
||||
SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the SysTick, starts counting once enabled
|
||||
*
|
||||
* Once enabled, the SysTick will start counting from whatever value it was
|
||||
* disabled with. To ensure a full period, use @ref DL_SYSTICK_init
|
||||
* or @ref DL_SYSTICK_resetValue before enabling.
|
||||
*/
|
||||
__STATIC_INLINE void DL_SYSTICK_enable(void)
|
||||
{
|
||||
SysTick->CTRL |= (SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the SysTick, stops counting once disabled
|
||||
*/
|
||||
__STATIC_INLINE void DL_SYSTICK_disable(void)
|
||||
{
|
||||
SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if the SysTick is enabled
|
||||
*
|
||||
* @return Returns the enabled status of the SysTick
|
||||
*
|
||||
* @retval true The SysTick is enabled and counting
|
||||
* @retval false The SysTick is disabled and not counting
|
||||
*/
|
||||
__STATIC_INLINE bool DL_SYSTICK_isEnabled(void)
|
||||
{
|
||||
return (
|
||||
(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) == SysTick_CTRL_ENABLE_Msk);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ti_dl_m0p_dl_systick__include */
|
||||
/** @}*/
|
||||
@@ -0,0 +1,169 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0C110X)
|
||||
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0c110x.h>
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC)
|
||||
{
|
||||
// Set SYSOSC back to base frequency if left enabled
|
||||
if (disableSYSOSC == false) {
|
||||
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
} else {
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
}
|
||||
|
||||
// Verify LFCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void)
|
||||
{
|
||||
// Only one should have been set, but clear both because unknown incoming state
|
||||
// Clear SYSOSCCFG.DISABLE to get SYSOSC running again
|
||||
// Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(void)
|
||||
{
|
||||
// Switch MCLK to HSCLK
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify HSCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void)
|
||||
{
|
||||
// Switch MCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy =
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED;
|
||||
|
||||
// Check if SLEEP is enabled
|
||||
if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) ==
|
||||
SYSCTL_MCLKCFG_USELFCLK_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STOP policy =
|
||||
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY policy =
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) ==
|
||||
SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY1;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl,
|
||||
DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG,
|
||||
(uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc,
|
||||
SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK |
|
||||
SYSCTL_GENCLKCFG_FCCSELCLK_MASK);
|
||||
}
|
||||
|
||||
#endif /* DeviceFamily_PARENT_MSPM0C110X */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,320 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0G1X0X_G3X0X)
|
||||
|
||||
#include <ti/driverlib/m0p/dl_core.h>
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0g1x0x_g3x0x.h>
|
||||
|
||||
void DL_SYSCTL_configSYSPLL(const DL_SYSCTL_SYSPLLConfig *config)
|
||||
{
|
||||
/* PLL configurations are retained in lower reset levels. Set default
|
||||
* behavior of disabling the PLL to keep a consistent behavior regardless
|
||||
* of reset level. */
|
||||
DL_SYSCTL_disableSYSPLL();
|
||||
|
||||
/* Check that SYSPLL is disabled before configuration */
|
||||
while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) !=
|
||||
(DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) {
|
||||
;
|
||||
}
|
||||
|
||||
// set SYSPLL reference clock
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0,
|
||||
((uint32_t) config->sysPLLRef), SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK);
|
||||
|
||||
// set predivider PDIV (divides reference clock)
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, ((uint32_t) config->pDiv),
|
||||
SYSCTL_SYSPLLCFG1_PDIV_MASK);
|
||||
|
||||
// save CPUSS CTL state and disable the cache
|
||||
uint32_t ctlTemp = DL_CORE_getInstructionConfig();
|
||||
DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
|
||||
DL_CORE_LITERAL_CACHE_ENABLED);
|
||||
|
||||
// populate SYSPLLPARAM0/1 tuning registers from flash, based on input freq
|
||||
SYSCTL->SOCLOCK.SYSPLLPARAM0 =
|
||||
*(volatile uint32_t *) ((uint32_t) config->inputFreq);
|
||||
SYSCTL->SOCLOCK.SYSPLLPARAM1 =
|
||||
*(volatile uint32_t *) ((uint32_t) config->inputFreq + (uint32_t) 0x4);
|
||||
|
||||
// restore CPUSS CTL state
|
||||
CPUSS->CTL = ctlTemp;
|
||||
|
||||
// set feedback divider QDIV (multiplies to give output frequency)
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1,
|
||||
((config->qDiv << SYSCTL_SYSPLLCFG1_QDIV_OFS) &
|
||||
SYSCTL_SYSPLLCFG1_QDIV_MASK),
|
||||
SYSCTL_SYSPLLCFG1_QDIV_MASK);
|
||||
|
||||
// write clock output dividers, enable outputs, and MCLK source to SYSPLLCFG0
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0,
|
||||
(((config->rDivClk2x << SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS) &
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK) |
|
||||
((config->rDivClk1 << SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS) &
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK) |
|
||||
((config->rDivClk0 << SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS) &
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK) |
|
||||
config->enableCLK2x | config->enableCLK1 | config->enableCLK0 |
|
||||
(uint32_t) config->sysPLLMCLK),
|
||||
(SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK |
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK |
|
||||
SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK |
|
||||
SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK |
|
||||
SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK |
|
||||
SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK));
|
||||
|
||||
// enable SYSPLL
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_SYSPLLEN_ENABLE;
|
||||
|
||||
// wait until SYSPLL startup is stabilized
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG,
|
||||
((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) |
|
||||
(uint32_t) config->xt1Drive,
|
||||
(SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK));
|
||||
// start the LFXT oscillator
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE);
|
||||
// wait until LFXT oscillator is stable
|
||||
// if it does not stabilize, check the hardware/IOMUX settings
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_LFXT_GOOD) {
|
||||
;
|
||||
}
|
||||
if (config->monitor) {
|
||||
// set the LFCLK monitor
|
||||
SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE;
|
||||
}
|
||||
|
||||
// switch LFCLK source from LFOSC to LFXT
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE);
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC)
|
||||
{
|
||||
if (disableSYSOSC == false) {
|
||||
// Set SYSOSC back to base frequency if left enabled
|
||||
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
} else {
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
}
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify LFCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void)
|
||||
{
|
||||
// Only one should have been set, but clear both because unknown incoming state
|
||||
// Clear SYSOSCCFG.DISABLE to get SYSOSC running again
|
||||
// Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while (((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK)) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source)
|
||||
{
|
||||
// Assume desired HS sources already enabled per their requirements (SYSPLL, HFXT, HFCLK_IN)
|
||||
// Selected desired HSCLK source
|
||||
DL_SYSCTL_setHSCLKSource(source);
|
||||
|
||||
// Verify HSCLK source is valid
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HSCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
|
||||
// Switch MCLK to HSCLK
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify HSCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void)
|
||||
{
|
||||
// Switch MCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range)
|
||||
{
|
||||
/* Some crystal configurations are retained in lower reset levels. Set
|
||||
* default behavior of HFXT to keep a consistent behavior regardless of
|
||||
* reset level. */
|
||||
DL_SYSCTL_disableHFXT();
|
||||
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
/* Set startup time to ~0.512ms based on TYP datasheet recommendation */
|
||||
DL_SYSCTL_setHFXTStartupTime(8);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXTParams(
|
||||
DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable)
|
||||
{
|
||||
/* Some crystal configurations are retained in lower reset levels. Set
|
||||
* default behavior of HFXT to keep a consistent behavior regardless of
|
||||
* reset level. */
|
||||
DL_SYSCTL_disableHFXT();
|
||||
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
DL_SYSCTL_setHFXTStartupTime(startupTime);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
|
||||
if (monitorEnable == true) {
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while (
|
||||
(DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
} else {
|
||||
DL_SYSCTL_disableHFCLKStartupMonitor();
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl,
|
||||
DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG,
|
||||
(uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc,
|
||||
SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK |
|
||||
SYSCTL_GENCLKCFG_FCCSELCLK_MASK);
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy =
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED;
|
||||
|
||||
// Check if SLEEP is enabled
|
||||
if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) ==
|
||||
SYSCTL_MCLKCFG_USELFCLK_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STOP policy =
|
||||
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY policy =
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) ==
|
||||
SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY1;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
#endif /* DeviceFamily_PARENT_MSPM0G1X0X_G3X0X */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,382 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0GX51X)
|
||||
|
||||
#include <ti/driverlib/m0p/dl_core.h>
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0gx51x.h>
|
||||
|
||||
void DL_SYSCTL_configSYSPLL(const DL_SYSCTL_SYSPLLConfig *config)
|
||||
{
|
||||
/*
|
||||
* PLL configurations are retained in lower reset levels. Set default
|
||||
* behavior of disabling the PLL to keep a consistent behavior regardless
|
||||
* of reset level.
|
||||
*/
|
||||
DL_SYSCTL_disableSYSPLL();
|
||||
|
||||
/*
|
||||
* Before any configuration is done, a check is performed first to
|
||||
* ensure that the trim table within SRAM has been initialized first.
|
||||
* If it has not been initialized then the table within SRAM will be
|
||||
* populated with values from the TRIM region of memory. Otherwise
|
||||
* if the flag has been set the function will continue as normal.
|
||||
*/
|
||||
if (!DL_FactoryRegion_isTrimTableInSram()) {
|
||||
DL_FactoryRegion_initTrimTable();
|
||||
}
|
||||
|
||||
/* Check that SYSPLL is disabled before configuration */
|
||||
while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) !=
|
||||
(DL_SYSCTL_CLK_STATUS_SYSPLL_OFF)) {
|
||||
;
|
||||
}
|
||||
|
||||
// set SYSPLL reference clock
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0,
|
||||
((uint32_t) config->sysPLLRef), SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK);
|
||||
|
||||
// set predivider PDIV (divides reference clock)
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1, ((uint32_t) config->pDiv),
|
||||
SYSCTL_SYSPLLCFG1_PDIV_MASK);
|
||||
|
||||
// save CPUSS CTL state and disable the cache
|
||||
uint32_t ctlTemp = DL_CORE_getInstructionConfig();
|
||||
DL_CORE_configInstruction(DL_CORE_PREFETCH_ENABLED, DL_CORE_CACHE_DISABLED,
|
||||
DL_CORE_LITERAL_CACHE_ENABLED);
|
||||
|
||||
// populate SYSPLLPARAM0/1 tuning registers from flash, based on input freq
|
||||
SYSCTL->SOCLOCK.SYSPLLPARAM0 =
|
||||
*(volatile uint32_t *) ((uint32_t) config->inputFreq);
|
||||
SYSCTL->SOCLOCK.SYSPLLPARAM1 =
|
||||
*(volatile uint32_t *) ((uint32_t) config->inputFreq + (uint32_t) 0x4);
|
||||
|
||||
// restore CPUSS CTL state
|
||||
CPUSS->CTL = ctlTemp;
|
||||
|
||||
// set feedback divider QDIV (multiplies to give output frequency)
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG1,
|
||||
((config->qDiv << SYSCTL_SYSPLLCFG1_QDIV_OFS) &
|
||||
SYSCTL_SYSPLLCFG1_QDIV_MASK),
|
||||
SYSCTL_SYSPLLCFG1_QDIV_MASK);
|
||||
|
||||
// write clock output dividers, enable outputs, and MCLK source to SYSPLLCFG0
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.SYSPLLCFG0,
|
||||
(((config->rDivClk2x << SYSCTL_SYSPLLCFG0_RDIVCLK2X_OFS) &
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK) |
|
||||
((config->rDivClk1 << SYSCTL_SYSPLLCFG0_RDIVCLK1_OFS) &
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK) |
|
||||
((config->rDivClk0 << SYSCTL_SYSPLLCFG0_RDIVCLK0_OFS) &
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK) |
|
||||
config->enableCLK2x | config->enableCLK1 | config->enableCLK0 |
|
||||
(uint32_t) config->sysPLLMCLK),
|
||||
(SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK |
|
||||
SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK |
|
||||
SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK |
|
||||
SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK |
|
||||
SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK |
|
||||
SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK));
|
||||
|
||||
// enable SYSPLL
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_SYSPLLEN_ENABLE;
|
||||
|
||||
// wait until SYSPLL startup is stabilized
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG,
|
||||
((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) |
|
||||
(uint32_t) config->xt1Drive,
|
||||
(SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK));
|
||||
// start the LFXT oscillator
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE);
|
||||
// wait until LFXT oscillator is stable
|
||||
// if it does not stabilize, check the hardware/IOMUX settings
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_LFXT_GOOD) {
|
||||
;
|
||||
}
|
||||
if (config->monitor) {
|
||||
// set the LFCLK monitor
|
||||
SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE;
|
||||
}
|
||||
|
||||
// switch LFCLK source from LFOSC to LFXT
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE);
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC)
|
||||
{
|
||||
if (disableSYSOSC == false) {
|
||||
// Set SYSOSC back to base frequency if left enabled
|
||||
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
} else {
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
}
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify LFCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void)
|
||||
{
|
||||
// Only one should have been set, but clear both because unknown incoming state
|
||||
// Clear SYSOSCCFG.DISABLE to get SYSOSC running again
|
||||
// Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while (((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK)) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source)
|
||||
{
|
||||
// Assume desired HS sources already enabled per their requirements (SYSPLL, HFXT, HFCLK_IN)
|
||||
// Selected desired HSCLK source
|
||||
DL_SYSCTL_setHSCLKSource(source);
|
||||
|
||||
// Verify HSCLK source is valid
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HSCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
|
||||
// Switch MCLK to HSCLK
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify HSCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void)
|
||||
{
|
||||
// Switch MCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range)
|
||||
{
|
||||
/*
|
||||
* Some crystal configurations are retained in lower reset levels. Set
|
||||
* default behavior of HFXT to keep a consistent behavior regardless of
|
||||
* reset level.
|
||||
*/
|
||||
DL_SYSCTL_disableHFXT();
|
||||
|
||||
/*
|
||||
* Before any configuration is done, a check is performed first to
|
||||
* ensure that the trim table within SRAM has been initialized first.
|
||||
* If it has not been initialized then the table within SRAM will be
|
||||
* populated with values from the TRIM region of memory. Otherwise
|
||||
* if the flag has been set the function will continue as normal.
|
||||
*/
|
||||
if (!DL_FactoryRegion_isTrimTableInSram()) {
|
||||
DL_FactoryRegion_initTrimTable();
|
||||
}
|
||||
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
/* Set startup time to ~0.512ms based on TYP datasheet recommendation */
|
||||
DL_SYSCTL_setHFXTStartupTime(8);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXTParams(
|
||||
DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable)
|
||||
{
|
||||
/*
|
||||
* Before any configuration is done, a check is performed first to
|
||||
* ensure that the trim table within SRAM has been initialized first.
|
||||
* If it has not been initialized then the table within SRAM will be
|
||||
* populated with values from the TRIM region of memory. Otherwise
|
||||
* if the flag has been set the function will continue as normal.
|
||||
*/
|
||||
if (!DL_FactoryRegion_isTrimTableInSram()) {
|
||||
DL_FactoryRegion_initTrimTable();
|
||||
}
|
||||
|
||||
/* Some crystal configurations are retained in lower reset levels. Set
|
||||
* default behavior of HFXT to keep a consistent behavior regardless of
|
||||
* reset level. */
|
||||
DL_SYSCTL_disableHFXT();
|
||||
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
DL_SYSCTL_setHFXTStartupTime(startupTime);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
|
||||
if (monitorEnable == true) {
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while (
|
||||
(DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
} else {
|
||||
DL_SYSCTL_disableHFCLKStartupMonitor();
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl,
|
||||
DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG,
|
||||
(uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc,
|
||||
SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK |
|
||||
SYSCTL_GENCLKCFG_FCCSELCLK_MASK);
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy =
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED;
|
||||
|
||||
// Check if SLEEP is enabled
|
||||
if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) ==
|
||||
SYSCTL_MCLKCFG_USELFCLK_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STOP policy =
|
||||
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY policy =
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) ==
|
||||
SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY1;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
bool DL_SYSCTL_initReadExecuteProtectFirewall(
|
||||
uint32_t startAddr, uint32_t endAddr)
|
||||
{
|
||||
bool status = false;
|
||||
if (!DL_SYSCTL_isINITDONEIssued()) {
|
||||
DL_SYSCTL_setReadExecuteProtectFirewallAddrStart(startAddr);
|
||||
DL_SYSCTL_setReadExecuteProtectFirewallAddrEnd(endAddr);
|
||||
DL_SYSCTL_enableReadExecuteProtectFirewall();
|
||||
status = true;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
bool DL_SYSCTL_initIPProtectFirewall(uint32_t startAddr, uint32_t endAddr)
|
||||
{
|
||||
bool status = false;
|
||||
if (!DL_SYSCTL_isINITDONEIssued()) {
|
||||
DL_SYSCTL_setIPProtectFirewallAddrStart(startAddr);
|
||||
DL_SYSCTL_setIPProtectFirewallAddrEnd(endAddr);
|
||||
DL_SYSCTL_enableIPProtectFirewall();
|
||||
status = true;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
#endif /* DeviceFamily_PARENT_MSPM0GX51X */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,240 @@
|
||||
/*
|
||||
* Copyright (c) 2023, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0H321X)
|
||||
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0h321x.h>
|
||||
|
||||
void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG,
|
||||
((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) |
|
||||
(uint32_t) config->xt1Drive,
|
||||
(SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK));
|
||||
// start the LFXT oscillator
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE);
|
||||
// wait until LFXT oscillator is stable
|
||||
// if it does not stabilize, check the hardware/IOMUX settings
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_LFXT_GOOD) {
|
||||
;
|
||||
}
|
||||
if (config->monitor) {
|
||||
// set the LFCLK monitor
|
||||
SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE;
|
||||
}
|
||||
|
||||
// switch LFCLK source from LFOSC to LFXT
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE);
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC)
|
||||
{
|
||||
// Set SYSOSC back to base frequency if left enabled
|
||||
if (disableSYSOSC == false) {
|
||||
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
} else {
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
}
|
||||
|
||||
// Verify LFCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void)
|
||||
{
|
||||
// Only one should have been set, but clear both because unknown incoming state
|
||||
// Clear SYSOSCCFG.DISABLE to get SYSOSC running again
|
||||
// Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source)
|
||||
{
|
||||
// Assume desired HS sources already enabled per their requirements (SYSPLL, HFXT, HFCLK_IN)
|
||||
// Selected desired HSCLK source
|
||||
DL_SYSCTL_setHSCLKSource(source);
|
||||
|
||||
// Verify HSCLK source is valid
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HSCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
|
||||
// Switch MCLK to HSCLK
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify HSCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void)
|
||||
{
|
||||
// Switch MCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range)
|
||||
{
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
/* Set startup time to ~0.512ms based on TYP datasheet recommendation */
|
||||
DL_SYSCTL_setHFXTStartupTime(8);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXTParams(
|
||||
DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable)
|
||||
{
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
DL_SYSCTL_setHFXTStartupTime(startupTime);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
|
||||
if (monitorEnable == true) {
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while (
|
||||
(DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
} else {
|
||||
DL_SYSCTL_disableHFCLKStartupMonitor();
|
||||
}
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy =
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED;
|
||||
|
||||
// Check if SLEEP is enabled
|
||||
if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) ==
|
||||
SYSCTL_MCLKCFG_USELFCLK_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STOP policy =
|
||||
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY policy =
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) ==
|
||||
SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY1;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl,
|
||||
DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG,
|
||||
(uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc,
|
||||
SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK |
|
||||
SYSCTL_GENCLKCFG_FCCSELCLK_MASK);
|
||||
}
|
||||
|
||||
#endif /* DeviceFamily_PARENT_MSPM0H321X */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,223 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L111X)
|
||||
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l111x.h>
|
||||
|
||||
bool DL_SYSCTL_initReadExecuteProtectFirewall(
|
||||
uint32_t startAddr, uint32_t endAddr)
|
||||
{
|
||||
bool status = false;
|
||||
if (!DL_SYSCTL_isINITDONEIssued()) {
|
||||
DL_SYSCTL_setReadExecuteProtectFirewallAddrStart(startAddr);
|
||||
DL_SYSCTL_setReadExecuteProtectFirewallAddrEnd(endAddr);
|
||||
DL_SYSCTL_enableReadExecuteProtectFirewall();
|
||||
status = true;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
bool DL_SYSCTL_initIPProtectFirewall(uint32_t startAddr, uint32_t endAddr)
|
||||
{
|
||||
bool status = false;
|
||||
if (!DL_SYSCTL_isINITDONEIssued()) {
|
||||
DL_SYSCTL_setIPProtectFirewallAddrStart(startAddr);
|
||||
DL_SYSCTL_setIPProtectFirewallAddrEnd(endAddr);
|
||||
DL_SYSCTL_enableIPProtectFirewall();
|
||||
status = true;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG,
|
||||
((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) |
|
||||
(uint32_t) config->xt1Drive,
|
||||
(SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK));
|
||||
// start the LFXT oscillator
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE);
|
||||
// wait until LFXT oscillator is stable
|
||||
// if it does not stabilize, check the hardware/IOMUX settings
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_LFXT_GOOD) {
|
||||
;
|
||||
}
|
||||
if (config->monitor) {
|
||||
// set the LFCLK monitor
|
||||
SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE;
|
||||
}
|
||||
|
||||
// switch LFCLK source from LFOSC to LFXT
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE);
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC)
|
||||
{
|
||||
// Set SYSOSC back to base frequency if left enabled
|
||||
if (disableSYSOSC == false) {
|
||||
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
} else {
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
}
|
||||
|
||||
// Verify LFCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void)
|
||||
{
|
||||
// Only one should have been set, but clear both because unknown incoming state
|
||||
// Clear SYSOSCCFG.DISABLE to get SYSOSC running again
|
||||
// Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(void)
|
||||
{
|
||||
// Switch MCLK to HSCLK
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify HSCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void)
|
||||
{
|
||||
// Switch MCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl,
|
||||
DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG,
|
||||
(uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc,
|
||||
SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK |
|
||||
SYSCTL_GENCLKCFG_FCCSELCLK_MASK);
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy =
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED;
|
||||
|
||||
// Check if SLEEP is enabled
|
||||
if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) ==
|
||||
SYSCTL_MCLKCFG_USELFCLK_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STOP policy =
|
||||
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY policy =
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) ==
|
||||
SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY1;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
#endif /* DeviceFamily_PARENT_MSPM0L111X */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,146 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L11XX_L13XX)
|
||||
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l11xx_l13xx.h>
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC)
|
||||
{
|
||||
if (disableSYSOSC == false) {
|
||||
// Set SYSOSC back to base frequency if left enabled
|
||||
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
} else {
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
}
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify LFCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void)
|
||||
{
|
||||
// Only one should have been set, but clear both because unknown incoming state
|
||||
// Clear SYSOSCCFG.DISABLE to get SYSOSC running again
|
||||
// Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy =
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED;
|
||||
|
||||
// Check if SLEEP is enabled
|
||||
if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) ==
|
||||
SYSCTL_MCLKCFG_USELFCLK_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STOP policy =
|
||||
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY policy =
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) ==
|
||||
SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY1;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl,
|
||||
DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG,
|
||||
(uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc,
|
||||
SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK |
|
||||
SYSCTL_GENCLKCFG_FCCSELCLK_MASK);
|
||||
}
|
||||
|
||||
#endif /* DeviceFamily_PARENT_MSPM0L11XX_L13XX */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,269 @@
|
||||
/*
|
||||
* Copyright (c) 2020, Texas Instruments Incorporated
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <ti/devices/DeviceFamily.h>
|
||||
|
||||
#if (DeviceFamily_PARENT == DeviceFamily_PARENT_MSPM0L122X_L222X)
|
||||
|
||||
#include <ti/driverlib/m0p/sysctl/dl_sysctl_mspm0l122x_l222x.h>
|
||||
|
||||
bool DL_SYSCTL_initReadExecuteProtectFirewall(
|
||||
uint32_t startAddr, uint32_t endAddr)
|
||||
{
|
||||
bool status = false;
|
||||
if (!DL_SYSCTL_isINITDONEIssued()) {
|
||||
DL_SYSCTL_setReadExecuteProtectFirewallAddrStart(startAddr);
|
||||
DL_SYSCTL_setReadExecuteProtectFirewallAddrEnd(endAddr);
|
||||
DL_SYSCTL_enableReadExecuteProtectFirewall();
|
||||
status = true;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
bool DL_SYSCTL_initIPProtectFirewall(uint32_t startAddr, uint32_t endAddr)
|
||||
{
|
||||
bool status = false;
|
||||
if (!DL_SYSCTL_isINITDONEIssued()) {
|
||||
DL_SYSCTL_setIPProtectFirewallAddrStart(startAddr);
|
||||
DL_SYSCTL_setIPProtectFirewallAddrEnd(endAddr);
|
||||
DL_SYSCTL_enableIPProtectFirewall();
|
||||
status = true;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setLFCLKSourceLFXT(const DL_SYSCTL_LFCLKConfig *config)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.LFCLKCFG,
|
||||
((uint32_t) config->lowCap << SYSCTL_LFCLKCFG_LOWCAP_OFS) |
|
||||
(uint32_t) config->xt1Drive,
|
||||
(SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK));
|
||||
// start the LFXT oscillator
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_STARTLFXT_TRUE);
|
||||
// wait until LFXT oscillator is stable
|
||||
// if it does not stabilize, check the hardware/IOMUX settings
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_LFXTGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_LFXT_GOOD) {
|
||||
;
|
||||
}
|
||||
if (config->monitor) {
|
||||
// set the LFCLK monitor
|
||||
SYSCTL->SOCLOCK.LFCLKCFG |= SYSCTL_LFCLKCFG_MONITOR_ENABLE;
|
||||
}
|
||||
|
||||
// switch LFCLK source from LFOSC to LFXT
|
||||
SYSCTL->SOCLOCK.LFXTCTL =
|
||||
(SYSCTL_LFXTCTL_KEY_VALUE | SYSCTL_LFXTCTL_SETUSELFXT_TRUE);
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoLFCLK(bool disableSYSOSC)
|
||||
{
|
||||
// Set SYSOSC back to base frequency if left enabled
|
||||
if (disableSYSOSC == false) {
|
||||
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
} else {
|
||||
// Do not set both bits
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG |= SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
}
|
||||
|
||||
// Verify LFCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromLFCLKtoSYSOSC(void)
|
||||
{
|
||||
// Only one should have been set, but clear both because unknown incoming state
|
||||
// Clear SYSOSCCFG.DISABLE to get SYSOSC running again
|
||||
// Clear MCLKCFG.USELFCLK to switch MCLK source from LFCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.SYSOSCCFG &= ~SYSCTL_SYSOSCCFG_DISABLE_ENABLE;
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USELFCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_CURMCLKSEL_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_LFCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK(DL_SYSCTL_HSCLK_SOURCE source)
|
||||
{
|
||||
// Assume desired HS sources already enabled per their requirements (SYSPLL, HFXT, HFCLK_IN)
|
||||
// Selected desired HSCLK source
|
||||
DL_SYSCTL_setHSCLKSource(source);
|
||||
|
||||
// Verify HSCLK source is valid
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HSCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
|
||||
// Switch MCLK to HSCLK
|
||||
SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify HSCLK -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_switchMCLKfromHSCLKtoSYSOSC(void)
|
||||
{
|
||||
// Switch MCLK to SYSOSC
|
||||
SYSCTL->SOCLOCK.MCLKCFG &= ~SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
|
||||
|
||||
// Verify SYSOSC -> MCLK
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HSCLKMUX_MASK) ==
|
||||
DL_SYSCTL_CLK_STATUS_MCLK_SOURCE_HSCLK) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXT(DL_SYSCTL_HFXT_RANGE range)
|
||||
{
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
/* Set startup time to ~0.512ms based on TYP datasheet recommendation */
|
||||
DL_SYSCTL_setHFXTStartupTime(8);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_setHFCLKSourceHFXTParams(
|
||||
DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable)
|
||||
{
|
||||
DL_SYSCTL_setHFXTFrequencyRange(range);
|
||||
DL_SYSCTL_setHFXTStartupTime(startupTime);
|
||||
SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE;
|
||||
|
||||
if (monitorEnable == true) {
|
||||
DL_SYSCTL_enableHFCLKStartupMonitor();
|
||||
/* Wait until HFXT oscillator is stable. If it does not stabilize, check the
|
||||
hardware/IOMUX settings */
|
||||
while (
|
||||
(DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_HFCLKGOOD_MASK) !=
|
||||
DL_SYSCTL_CLK_STATUS_HFCLK_GOOD) {
|
||||
;
|
||||
}
|
||||
} else {
|
||||
DL_SYSCTL_disableHFCLKStartupMonitor();
|
||||
}
|
||||
}
|
||||
|
||||
void DL_SYSCTL_configFCC(DL_SYSCTL_FCC_TRIG_TYPE trigLvl,
|
||||
DL_SYSCTL_FCC_TRIG_SOURCE trigSrc, DL_SYSCTL_FCC_CLOCK_SOURCE clkSrc)
|
||||
{
|
||||
DL_Common_updateReg(&SYSCTL->SOCLOCK.GENCLKCFG,
|
||||
(uint32_t) trigLvl | (uint32_t) trigSrc | (uint32_t) clkSrc,
|
||||
SYSCTL_GENCLKCFG_FCCLVLTRIG_MASK | SYSCTL_GENCLKCFG_FCCTRIGSRC_MASK |
|
||||
SYSCTL_GENCLKCFG_FCCSELCLK_MASK);
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP DL_SYSCTL_getPowerPolicyRUNSLEEP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP policy =
|
||||
DL_SYSCTL_POWER_POLICY_RUN_SLEEP_NOT_ENABLED;
|
||||
|
||||
// Check if SLEEP is enabled
|
||||
if ((SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) != SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_USELFCLK_MASK) ==
|
||||
SYSCTL_MCLKCFG_USELFCLK_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_RUN_SLEEP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STOP DL_SYSCTL_getPowerPolicySTOP(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STOP policy =
|
||||
DL_SYSCTL_POWER_POLICY_STOP_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STOP) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.SYSOSCCFG & SYSCTL_SYSOSCCFG_USE4MHZSTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_USE4MHZSTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP1;
|
||||
} else if ((SYSCTL->SOCLOCK.SYSOSCCFG &
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_MASK) ==
|
||||
SYSCTL_SYSOSCCFG_DISABLESTOP_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP2;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STOP0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY DL_SYSCTL_getPowerPolicySTANDBY(void)
|
||||
{
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY policy =
|
||||
DL_SYSCTL_POWER_POLICY_STANDBY_NOT_ENABLED;
|
||||
|
||||
// Check if STOP is enabled
|
||||
if ((SYSCTL->SOCLOCK.PMODECFG == SYSCTL_PMODECFG_DSLEEP_STANDBY) &&
|
||||
(SCB->SCR & SCB_SCR_SLEEPDEEP_Msk) == SCB_SCR_SLEEPDEEP_Msk) {
|
||||
// Check which policy is enabled
|
||||
if ((SYSCTL->SOCLOCK.MCLKCFG & SYSCTL_MCLKCFG_STOPCLKSTBY_MASK) ==
|
||||
SYSCTL_MCLKCFG_STOPCLKSTBY_ENABLE) {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY1;
|
||||
} else {
|
||||
policy = DL_SYSCTL_POWER_POLICY_STANDBY0;
|
||||
}
|
||||
}
|
||||
return policy;
|
||||
}
|
||||
|
||||
#endif /* DeviceFamily_PARENT_MSPM0L122X_L222X */
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user