init:全链路闭环控制调通
This commit is contained in:
SkyLi
@@ -5,16 +5,25 @@
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* @v2CliArgs --device "MSPM0G3507" --package "LQFP-64(PM)" --product "mspm0_sdk@2.04.00.06"
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* @versions {"tool":"1.23.1+4034"}
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*/
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scripting.excludeFromBuild("device_linker.cmd");
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scripting.excludeFromBuild("device_linker.lds");
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scripting.excludeFromBuild("device.opt");
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scripting.excludeFromBuild("device.cmd.genlibs");
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scripting.excludeFromBuild("device.lds.genlibs");
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scripting.excludeFromBuild("Event.dot");
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/**
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* Import the modules used in this configuration.
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*/
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const GPIO = scripting.addModule("/ti/driverlib/GPIO", {}, false);
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const GPIO1 = GPIO.addInstance();
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const GPIO2 = GPIO.addInstance();
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const SYSCTL = scripting.addModule("/ti/driverlib/SYSCTL");
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const SYSTICK = scripting.addModule("/ti/driverlib/SYSTICK");
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const VREF = scripting.addModule("/ti/driverlib/VREF");
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const GPIO = scripting.addModule("/ti/driverlib/GPIO", {}, false);
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const GPIO1 = GPIO.addInstance();
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const GPIO2 = GPIO.addInstance();
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const QEI = scripting.addModule("/ti/driverlib/QEI", {}, false);
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const QEI1 = QEI.addInstance();
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const SYSCTL = scripting.addModule("/ti/driverlib/SYSCTL");
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const SYSTICK = scripting.addModule("/ti/driverlib/SYSTICK");
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const VREF = scripting.addModule("/ti/driverlib/VREF");
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const ProjectConfig = scripting.addModule("/ti/project_config/ProjectConfig");
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/**
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* Write custom configuration values to the imported modules.
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@@ -79,6 +88,13 @@ GPIO2.associatedPins[0].interruptEn = true;
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GPIO2.associatedPins[0].polarity = "RISE";
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GPIO2.associatedPins[0].pin.$assign = "PA18";
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QEI1.$name = "QEI_0";
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QEI1.peripheral.$assign = "TIMG8";
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QEI1.peripheral.ccp0Pin.$assign = "PB6";
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QEI1.peripheral.ccp1Pin.$assign = "PB7";
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QEI1.ccp0PinConfig.$name = "ti_driverlib_gpio_GPIOPinGeneric0";
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QEI1.ccp1PinConfig.$name = "ti_driverlib_gpio_GPIOPinGeneric1";
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SYSCTL.forceDefaultClkConfig = true;
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SYSCTL.clockTreeEn = true;
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scripting.suppress("For best practices when the CPUCLK is running at 32MHz and above, clear the flash status bit using DL_FlashCTL_executeClearStatus\\(\\) before executing any flash operation\\. Otherwise there may be false positives\\.", SYSCTL);
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@@ -98,6 +114,8 @@ VREF.peripheral.vrefPosPin.$assign = "PA23";
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VREF.peripheral.vrefNegPin.$assign = "PA21";
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VREF.vrefNegPinConfig.$name = "ti_driverlib_gpio_GPIOPinGeneric30";
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ProjectConfig.genLibIQVersion = "MATHACL";
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/**
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* Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
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* version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to
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@@ -40,6 +40,8 @@
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#include "ti_msp_dl_config.h"
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DL_TimerG_backupConfig gQEI_0Backup;
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/*
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* ======== SYSCFG_DL_init ========
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* Perform any initialization needed before using any board APIs
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@@ -50,19 +52,47 @@ SYSCONFIG_WEAK void SYSCFG_DL_init(void)
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SYSCFG_DL_GPIO_init();
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/* Module-Specific Initializations*/
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SYSCFG_DL_SYSCTL_init();
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SYSCFG_DL_QEI_0_init();
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SYSCFG_DL_VREF_init();
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SYSCFG_DL_SYSTICK_init();
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/* Ensure backup structures have no valid state */
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gQEI_0Backup.backupRdy = false;
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}
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/*
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* User should take care to save and restore register configuration in application.
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* See Retention Configuration section for more details.
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*/
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SYSCONFIG_WEAK bool SYSCFG_DL_saveConfiguration(void)
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{
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bool retStatus = true;
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retStatus &= DL_TimerG_saveConfiguration(QEI_0_INST, &gQEI_0Backup);
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return retStatus;
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}
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SYSCONFIG_WEAK bool SYSCFG_DL_restoreConfiguration(void)
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{
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bool retStatus = true;
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retStatus &= DL_TimerG_restoreConfiguration(QEI_0_INST, &gQEI_0Backup, false);
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return retStatus;
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}
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SYSCONFIG_WEAK void SYSCFG_DL_initPower(void)
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{
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DL_GPIO_reset(GPIOA);
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DL_GPIO_reset(GPIOB);
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DL_TimerG_reset(QEI_0_INST);
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DL_VREF_reset(VREF);
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DL_GPIO_enablePower(GPIOA);
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DL_GPIO_enablePower(GPIOB);
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DL_TimerG_enablePower(QEI_0_INST);
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DL_VREF_enablePower(VREF);
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delay_cycles(POWER_STARTUP_DELAY);
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@@ -76,6 +106,9 @@ SYSCONFIG_WEAK void SYSCFG_DL_GPIO_init(void)
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DL_GPIO_initPeripheralAnalogFunction(GPIO_LFXIN_IOMUX);
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DL_GPIO_initPeripheralAnalogFunction(GPIO_LFXOUT_IOMUX);
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DL_GPIO_initPeripheralInputFunction(GPIO_QEI_0_PHA_IOMUX,GPIO_QEI_0_PHA_IOMUX_FUNC);
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DL_GPIO_initPeripheralInputFunction(GPIO_QEI_0_PHB_IOMUX,GPIO_QEI_0_PHB_IOMUX_FUNC);
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DL_GPIO_initDigitalOutputFeatures(LED_A14_PIN_14_IOMUX,
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DL_GPIO_INVERSION_DISABLE, DL_GPIO_RESISTOR_PULL_DOWN,
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DL_GPIO_DRIVE_STRENGTH_LOW, DL_GPIO_HIZ_DISABLE);
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@@ -111,128 +144,6 @@ static const DL_SYSCTL_LFCLKConfig gLFCLKConfig = {
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.monitor = false,
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.xt1Drive = DL_SYSCTL_LFXT_DRIVE_STRENGTH_HIGHEST,
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};
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///////////////////////////////////////////////////////////////
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void DL_SYSCTL_setHFCLKSourceHFXTParams (DL_SYSCTL_HFXT_RANGE range, uint32_t startupTime, bool monitorEnable)
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{
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uint32_t register_temp = SYSCTL->SOCLOCK.HFCLKCLKCFG;
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register_temp &= ~(SYSCTL_HFCLKCLKCFG_HFXTRSEL_MASK | SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_MASK);
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switch(range)
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{
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case DL_SYSCTL_HFXT_RANGE_4_8_MHZ : register_temp |= (SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE4TO8); break;
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case DL_SYSCTL_HFXT_RANGE_8_16_MHZ : register_temp |= (SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE8TO16); break;
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case DL_SYSCTL_HFXT_RANGE_16_32_MHZ: register_temp |= (SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE16TO32); break;
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case DL_SYSCTL_HFXT_RANGE_32_48_MHZ: register_temp |= (SYSCTL_HFCLKCLKCFG_HFXTRSEL_RANGE32TO48); break;
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}
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register_temp |= (monitorEnable) ? (SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_ENABLE) : (SYSCTL_HFCLKCLKCFG_HFCLKFLTCHK_DISABLE);
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SYSCTL->SOCLOCK.HFCLKCLKCFG = register_temp;
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SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_HFXTEN_ENABLE; // 必须启动 否则频率不准
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SYSCTL->SOCLOCK.HSCLKEN = SYSCTL_HSCLKEN_SYSPLLEN_ENABLE | SYSCTL_HSCLKEN_USEEXTHFCLK_ENABLE;
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SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKCFG_HSCLKSEL_HFCLKCLK;
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}
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void DL_SYSCTL_configSYSPLL (const DL_SYSCTL_SYSPLLConfig *config)
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{
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uint32_t register_temp = 0;
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SYSCTL->SOCLOCK.HSCLKEN &= ~(SYSCTL_HSCLKEN_SYSPLLEN_MASK);
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{
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register_temp = SYSCTL->SOCLOCK.SYSPLLCFG0;
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register_temp &= ~(SYSCTL_SYSPLLCFG0_SYSPLLREF_MASK | SYSCTL_SYSPLLCFG0_MCLK2XVCO_MASK
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| SYSCTL_SYSPLLCFG0_ENABLECLK0_MASK | SYSCTL_SYSPLLCFG0_ENABLECLK1_MASK | SYSCTL_SYSPLLCFG0_ENABLECLK2X_MASK
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| SYSCTL_SYSPLLCFG0_RDIVCLK0_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK1_MASK | SYSCTL_SYSPLLCFG0_RDIVCLK2X_MASK );
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register_temp |= config->rDivClk2x ;
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register_temp |= config->rDivClk1 ;
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register_temp |= config->rDivClk0 ;
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register_temp |= config->enableCLK2x ;
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register_temp |= config->enableCLK1 ;
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register_temp |= config->enableCLK0 ;
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register_temp |= config->sysPLLMCLK ;
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register_temp |= config->sysPLLRef ;
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SYSCTL->SOCLOCK.SYSPLLCFG0 = register_temp;
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}
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{
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register_temp = SYSCTL->SOCLOCK.SYSPLLCFG1;
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register_temp &= ~(SYSCTL_SYSPLLCFG1_PDIV_MASK | SYSCTL_SYSPLLCFG1_QDIV_MASK);
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register_temp |= (config->qDiv << SYSCTL_SYSPLLCFG1_QDIV_OFS );
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register_temp |= (config->pDiv);
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SYSCTL->SOCLOCK.SYSPLLCFG1 = register_temp;
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}
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{
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SYSCTL->SOCLOCK.SYSPLLPARAM0 =
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*(volatile uint32_t *) ((uint32_t) config->inputFreq);
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SYSCTL->SOCLOCK.SYSPLLPARAM1 =
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*(volatile uint32_t *) ((uint32_t) config->inputFreq + (uint32_t) 0x4);
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}
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SYSCTL->SOCLOCK.HSCLKEN |= SYSCTL_HSCLKEN_SYSPLLEN_ENABLE;
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while ((DL_SYSCTL_getClockStatus() & SYSCTL_CLKSTATUS_SYSPLLGOOD_MASK) !=
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DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD) {
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;
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}
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}
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void DL_SYSCTL_setLFCLKSourceLFXT (const DL_SYSCTL_LFCLKConfig *config)
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{
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uint32_t register_temp = SYSCTL->SOCLOCK.LFCLKCFG;
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register_temp &= ~(SYSCTL_LFCLKCFG_XT1DRIVE_MASK | SYSCTL_LFCLKCFG_MONITOR_MASK | SYSCTL_LFCLKCFG_LOWCAP_MASK);
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register_temp |= (config->lowCap) ? (SYSCTL_LFCLKCFG_LOWCAP_ENABLE) : (SYSCTL_LFCLKCFG_LOWCAP_DISABLE);
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register_temp |= (config->monitor) ? (SYSCTL_LFCLKCFG_MONITOR_ENABLE) : (SYSCTL_LFCLKCFG_MONITOR_DISABLE);
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register_temp |= (config->xt1Drive);
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SYSCTL->SOCLOCK.LFCLKCFG = register_temp;
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}
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void DL_SYSCTL_switchMCLKfromSYSOSCtoHSCLK (DL_SYSCTL_HSCLK_SOURCE source)
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{
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SYSCTL->SOCLOCK.HSCLKCFG = (uint32_t) source;
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SYSCTL->SOCLOCK.MCLKCFG |= SYSCTL_MCLKCFG_USEHSCLK_ENABLE;
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}
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////////////////////////////////////////////////////////////////////////////
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SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_init(void)
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{
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@@ -258,6 +169,27 @@ SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_init(void)
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}
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static const DL_TimerG_ClockConfig gQEI_0ClockConfig = {
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.clockSel = DL_TIMER_CLOCK_BUSCLK,
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.divideRatio = DL_TIMER_CLOCK_DIVIDE_1,
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.prescale = 0U
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};
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SYSCONFIG_WEAK void SYSCFG_DL_QEI_0_init(void) {
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DL_TimerG_setClockConfig(
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QEI_0_INST, (DL_TimerG_ClockConfig *) &gQEI_0ClockConfig);
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DL_TimerG_configQEI(QEI_0_INST, DL_TIMER_QEI_MODE_2_INPUT,
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DL_TIMER_CC_INPUT_INV_NOINVERT, DL_TIMER_CC_0_INDEX);
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DL_TimerG_configQEI(QEI_0_INST, DL_TIMER_QEI_MODE_2_INPUT,
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DL_TIMER_CC_INPUT_INV_NOINVERT, DL_TIMER_CC_1_INDEX);
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DL_TimerG_setLoadValue(QEI_0_INST, 65535);
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DL_TimerG_enableClock(QEI_0_INST);
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}
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static const DL_VREF_Config gVREFConfig = {
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.vrefEnable = DL_VREF_ENABLE_DISABLE,
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@@ -87,6 +87,23 @@ extern "C" {
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/* Defines for QEI_0 */
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#define QEI_0_INST TIMG8
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#define QEI_0_INST_IRQHandler TIMG8_IRQHandler
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#define QEI_0_INST_INT_IRQN (TIMG8_INT_IRQn)
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/* Pin configuration defines for QEI_0 PHA Pin */
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#define GPIO_QEI_0_PHA_PORT GPIOB
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#define GPIO_QEI_0_PHA_PIN DL_GPIO_PIN_6
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#define GPIO_QEI_0_PHA_IOMUX (IOMUX_PINCM23)
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#define GPIO_QEI_0_PHA_IOMUX_FUNC IOMUX_PINCM23_PF_TIMG8_CCP0
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/* Pin configuration defines for QEI_0 PHB Pin */
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#define GPIO_QEI_0_PHB_PORT GPIOB
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#define GPIO_QEI_0_PHB_PIN DL_GPIO_PIN_7
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#define GPIO_QEI_0_PHB_IOMUX (IOMUX_PINCM24)
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#define GPIO_QEI_0_PHB_IOMUX_FUNC IOMUX_PINCM24_PF_TIMG8_CCP1
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/* Defines for VREF */
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#define VREF_VOLTAGE_MV 3300
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#define GPIO_VREF_VREFPOS_PORT GPIOA
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@@ -126,10 +143,13 @@ void SYSCFG_DL_init(void);
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void SYSCFG_DL_initPower(void);
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void SYSCFG_DL_GPIO_init(void);
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void SYSCFG_DL_SYSCTL_init(void);
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void SYSCFG_DL_QEI_0_init(void);
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void SYSCFG_DL_VREF_init(void);
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void SYSCFG_DL_SYSTICK_init(void);
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bool SYSCFG_DL_saveConfiguration(void);
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bool SYSCFG_DL_restoreConfiguration(void);
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#ifdef __cplusplus
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}
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